SEL EXHIBIT NO. 2013
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`INNOLUX CORP. v. PATENT OF SEMICONDUCTOR ENERGY
`LABORATORY CO., LTD.
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`IPR2013-00038
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`INNOLUX CORP. v. PATENT OF SEMICONDUCTOR ENERGY
`LABORATORY CO., LTD.
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`IPR2013-00038
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`IN THE UNITED STATES PATENT TRIAL AND APPEAL BOARD
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`8,068,204
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`
`In re Inter Partes Review of:
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`U.S. Patent No.
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` Nov. 29, 2011
`Issued:
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`
` Yoshiharu Hirakata
`Inventors:
` Shunpei Yamazaki
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`
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`Application No.: 13/009,980
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`
`Jan. 20, 2011
`Filed:
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`For: Semiconductor Energy
` Laboratory Co., Ltd.
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`Mail Stop Patent Board (37 C.F.R. § 42.6(b)(2))
`Patent Trial and Appeal Board
`U.S.P.T.O.
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`) FILED ELECTRONICALLY
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` DECLARATION OF MILTIADIS HATALIS, Ph.D.
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`I.
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`Background and Qualifications
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`(1) My name is Miltiadis Hatalis. I am currently a Professor at Lehigh
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`University in the Department of Electrical and Computer Engineering. I have
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`studied, taught, and practiced in the relevant flat panel display technology for over
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`25 years.
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`(2)
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`I received my Doctor of Philosophy (Ph.D.) degree in the field of
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`Electrical and Computer Engineering from Carnegie Mellon University in 1987.
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`The topic of my Ph.D. dissertation research was “Crystallization of Amorphous
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`Silicon Films and its Application in Bipolar and Thin Film Transistors.” I received
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`my Masters of Science (M.S.) degree in Electrical and Computer Engineering in
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`1984 from the State University of New York at Buffalo and my Bachelor of
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`Science (B.S.) degree in Physics in 1982 from the Aristotle University of
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`Thessaloniki in Greece.
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`(3) Upon receiving my Ph.D. degree, I joined the faculty of Lehigh
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`University in the Department of Electrical and Computer Engineering as an
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`Assistant Professor. I was promoted to the rank of Associate Professor with tenure
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`in 1991 and to the rank of Professor in 1995. From 1987-1992, I served as
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`Associate Director of Lehigh's “Microelectronics Research Laboratory.”
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`(4)
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`In 1992, I founded and became Director of the “Display Research
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`Laboratory,” which was the first academic laboratory in the United States
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`dedicated to research and development of Thin Film Transistors (TFTs) for Active
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`Matrix Liquid Crystal Displays (AMLCDs) and Active Matrix Organic Light
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`Emitting Diode (AMOLEDs) displays. As Director of Lehigh's “Display Research
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`Laboratory,” I have raised over $10 million through research contracts and grants
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`to support the laboratory's research and development activities on thin film
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`transistors and their application to flat panel displays. These contracts and grants
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`were funded by the Defense Advanced Research Program Agency (DARPA), the
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`Army Research Laboratory (ARL), the National Science Foundation (NSF), the
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`National Aeronautics and Space Administration (NASA), the State of
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`Pennsylvania, and a variety of industrial companies including IBM, Kodak, Sharp,
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`Northrop Grumman, and others.
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`(5) As a faculty member, I supervised the research of eighteen Ph.D.
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`dissertations in the technical field of TFTs and, along with my graduate students,
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`published over 150 technical publications in scientific journals or conferences in
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`the field of thin film transistors and their applications in flat panel displays. 1 In
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`addition to the aforementioned Ph.D. dissertations, I have also supervised a large
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`number of graduate student master’s theses and undergraduate research projects. I
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`have taught a number of different undergraduate and graduate level courses in the
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`Electrical and Computer Engineering department at the Lehigh University dealing
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`with the physics, technology, and the design of solid-state devices and circuits. I
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`have also introduced and regularly teach a course on “Semiconductor Material and
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`Device Characterization,” and I have also reorganized a course on “Introduction to
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`Design of Very Large Scale Integration (VLSI).”
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`(6) As part of my research, I utilize much of the same equipment and
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`many of the same microfabrication processes that are relevant to U.S. Patent No.
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`1 More information on this subject can be found on my research group web pages:
`www.ece.lehigh.edu/DRL
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`8,068,204 (hereinafter referred to as the “‘204 patent”), including: Plasma-
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`Enhanced Chemical Vapor Deposition (PECVD) for intrinsic hydrogenated-
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`amorphous silicon, silicon nitride and silicon dioxide films; sputter and e-beam
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`deposition tools for aluminum, indium-tin-oxide, tantalum and other metallic thin
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`films; photolithographic tools for spinning, exposure and developing photoresist
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`patterns; as well as plasma or wet etching tools for removing various thin film
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`materials from the substrate. Furthermore, I also utilize several tools for the
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`characterization of the materials and structures used in thin film transistors
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`including: optical microscopes, Scanning Electron Microscopy (SEM),
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`Transmission Electron Microscopy (TEM), and Atomic Force Microscopy (AFM).
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`I also utilize a variety of electrical characterization techniques and instruments for
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`testing the electrical performance of completed TFT circuits and flat panel
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`displays.
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`(7) As part of my research, I pioneered a technique for crystallizing
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`amorphous silicon. The technique I pioneered has been used in the manufacture of
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`small polysilicon TFT AMLCDs for over a dozen years, and, more recently,
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`polysilicon TFTs have also been used for AMOLED displays. In addition, many
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`industrial and academic laboratories have recently initiated R&D activities related
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`to the fabrication of polysilicon thin film transistors on flexible metal foil
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`substrates and their application to flexible displays. Such research flows from the
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`accomplishments of my research group in this technical field.
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`(8) My industrial experience includes work at the XEROX Palo Alto
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`Research Laboratory and various consulting projects with flat panel display
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`companies as well as companies producing equipment for the manufacture of flat
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`panel displays. All of these projects were related to the thin film transistors and
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`their application to flat panel displays.
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`(9)
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`I am a member of several professional organizations including the
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`Society for Information Display (SID), and the Electron Device Society of the
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`Institute of Electrical and Electronics Engineers (IEEE). I have also been the chair
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`or co-chair at numerous national and international conferences/symposiums
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`including several SID sponsored Workshops on Active Matrix Liquid Crystal
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`Displays and a Materials Research Society Symposium on Flat Panel Displays. I
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`have co-authored two book chapters, one dealing with the “Polysilicon TFT
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`Technology” and another on application of “Polysilicon TFTs in AMOLED
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`Displays.” I have served as a reviewer for technical papers submitted to several
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`scientific journals and have also served as a reviewer for several years for the
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`National Science Foundation Small Business Innovative Research (SBIR)
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`program.
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`(10) A copy of my latest curriculum vitae (C.V.) is attached as Appendix
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`A and includes a list of my publications.
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`II. My Status as an Independent Expert Witness
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`(11) I have been retained in this matter by Chimei Innolux Corp.
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`(“Petitioner”) to provide an analysis of the scope and content of the ‘204 patent
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`relative to the state of the art at the time of the earliest application underlying the
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`‘204 patent.
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`(12) I am being compensated at the rate of $300 per hour for my work. My
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`fee is not contingent on the outcome of any matter or on any of the technical
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`positions I explain in this declaration. I have no financial interest in Petitioner.
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`(13) I have been informed that Semiconductor Energy Laboratory Co., Ltd.
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`(hereinafter referred to as “Patentee”) owns the ‘204 patent. I have no financial
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`interest in the Patentee or the ‘204 patent nor have I ever had any contact with the
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`Patentee, or the inventors of the ‘204 patent, Yoshiharu Hirakata and Shunpei
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`Yamazaki.
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`III. Description of the Relevant Field and the Relevant Timeframe
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`(14) I have carefully reviewed the ‘204 patent.
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`(15) For convenience, all of the information that I considered in arriving at
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`my opinions is listed in Appendix B.
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`(16) Based on my review of these materials, I believe that the relevant field
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`for purposes of the ‘204 patent is microelectronic fabrication processes and devices
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`related to flat panel displays and in particular to Active Matrix Liquid Crystal
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`Displays (AMLCD) . I have been informed that the relevant timeframe is October
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`6, 1997.
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`(17) As described in Section I above, I have extensive experience in the
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`relevant field. Based on my experience, I have a good understanding of the
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`relevant field in the relevant timeframe.
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`IV. The Person of Ordinary Skill in the Relevant Field in the Relevant
`Timeframe
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`
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`(18) I have been informed that “a person of ordinary skill in the relevant
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`field” is a hypothetical person to whom an expert in the relevant field could assign
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`a routine task with reasonable confidence that the task would be successfully
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`carried out. I have been informed that the level of skill in the art is evidenced by
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`the prior art references. The prior art discussed herein demonstrates that a person
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`of ordinary skill in the art, at the time the ‘204 patent was filed, was aware of
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`liquid crystal display structures, including techniques for providing connections
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`therein and to circuits outside a sealant.
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`(19) Based on my experience, I have an understanding of the capabilities
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`of a person of ordinary skill in the relevant filed. I have supervised and directed
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`many such persons over the course of my career.
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`V. Background of the Technology
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`(20) In an active matrix LCD, an image is divided into small elements
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`called pixels. In a color active matrix LCD , each pixel is further divided into three
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`sub-pixels, one for each of the three primary colors red, green, and blue. Each
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`pixel (in a monochrome display) or sub-pixel (in a color display) contains a thin
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`film transistor TFT, a capacitor, and a pixel electrode.
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`(21) The TFT serves as a switch that, when turned ON, allows an electrical
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`current to flow into and charge the capacitor to a specific voltage. When the TFT
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`switch is turned OFF, current cannot flow through it and thus, the voltage
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`established at the capacitor is maintained until the next frame period, at which time
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`the switch will be turned on again in order to update the voltage stored in the
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`capacitor.
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`(22) The voltage stored in the pixel capacitor also appears to the pixel
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`electrode. This voltage sets an electric field across the liquid crystal material that
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`is on-top of the electrode; the higher the stored voltage the higher the electric field.
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`The magnitude of the electric field across the pixel electrode will determine the
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`optical properties of the LCD material and this, in turn, will determine the amount
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`of light that will pass through the pixel or sub-pixel.
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`(23) Individual pixels are switched by way of the TFTs in accordance with
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`scan and signal drive control circuitry. In certain, active matrix LCD the scan and
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`signal drive control circuitry are fabricated on the glass substrate at the periphery
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`of the active matrix pixel array. Such circuitry typically consists of a shift register
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`fabricated with TFTs and wiring using the same materials as those used in the
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`array of pixels. The number of pixels depends upon the display format. For
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`example, the VGA format contains 640x480 pixels in a monochrome display, and
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`640x480x3 in a color display. There are many display formats that include the
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`aforementioned VGA (640x480) format and the High Definition TV format,
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`which includes up to 1920x1080x3 pixels with over six million thin film transistors
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`(TFTs).
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`VI. The ‘204 Patent
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`(24) As shown below in Fig. 13, the ‘204 patent describes that prior art
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`active matrix LCD devices are known to include peripheral driving circuits 1504
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`that may be enclosed by a sealant 1505. In these prior art devices, external
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`connection lines 1508 have to cross the sealant to exchange signals with a flexible
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`printed circuit (FPC) 1507.
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`(25) When external connection line 1508 is present in an area of the seal
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`area, a height difference ‘d’ may be found in comparison to an area of the seal area
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`that does not include external connection line 1508, resulting in undesirable
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`display properties such as an uneven color and brightness. ‘204 patent, col. 2, ll.
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`59-61, fig. 14A. The ‘204 patent attempts to minimize the height difference
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`through the use of adjustment layers. ‘204 patent, fig. 2B.
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`(26) The ‘204 patent also describes a configuration of the external
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`connection lines that “makes it possible to reduce electrical resistance of the
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`external connection lines 403 significantly … to provide preferable display when
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`driven at a high frequency and a high speed.” ‘204 patent, col. 9, ll. 6-11. The ‘204
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`patent accomplishes this by including a layer with an auxiliary line 401 that runs
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`parallel with external connection line 403. ‘204 patent, fig. 4A.
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`(27) However, the ‘204 patent recognizes that the inclusion of the auxiliary
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`line 401 in parallel with external connection line 403 increases the height
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`difference that causes undesired display properties. ‘204 patent, col. 9, ll. 12-19.
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`Thus, the ‘204 patent features adjustment layers that are provided to minimize
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`height differences. ‘204 patent, fig. 4B.
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`VII. Claim Interpretation
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`(28) In proceedings before the USPTO, I understand that the claims of an
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`unexpired patent are to be given their broadest reasonable interpretation in view of
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`the specification from the perspective of one skilled in the art. I have been
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`informed that the ‘204 patent has not expired. In comparing the claims of the ‘204
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`patent to the known prior art, I have carefully considered the ‘204 patent, and the
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`‘204 file history based upon my experience and knowledge in the relevant field. I
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`have not encountered any “coined” terms or terms that require consideration of a
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`special or explicitly defined meaning. Instead, the claim terms of the ‘204 patent
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`are used in their ordinary and customary sense as one skilled in the relevant field
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`would understand them.
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`VIII. Unpatentability Based on Prior Art in the Present Proceedings
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`(29) I am informed that the ‘204 patent is a continuation of U.S. Patent
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`Application No. 12/252,793, filed on Oct. 16, 2008, which is a continuation of U.S.
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`Patent Application No. 11/837,588, filed on Aug. 13, 2007, which is a continuation
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`of U.S. Patent Application No. 10/384,943, filed on Mar. 10, 2003, which is a
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`continuation of U.S. Patent Application No. 09/865,081, filed on May. 24, 2001,
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`which is a continuation of U.S. Patent Application No. 09/481,278, filed on Jan.
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`11, 2000, which is a continuation of U.S. Patent Application No. 09/165,628, filed
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`on Oct. 1, 1998. Additionally, ‘204 patent claims priority to a foreign patent,
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`Japanese Patent Application No. 09-289160, filed on Oct. 6, 1997. I am further
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`informed that this means that the ‘204 patent is considered to have been filed on
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`Oct. 6, 1997 for purposes of determining whether a reference constitutes prior art.
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`Thus, a reference will qualify as prior art if it disclosed or suggested the claimed
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`invention of the ‘204 patent prior to Oct. 6, 1997.
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`(30) I have been informed that a patent claim can be found unpatentable as
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`obvious where the differences between the subject matter sought to be patented
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`and the prior art are such that the subject matter as a whole would have been
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`obvious at the time the invention was made to a person having ordinary skill in the
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`relevant field. I understand that an obviousness analysis involves a consideration
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`of (1) the scope and content of the prior art; (2) the differences between the
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`claimed inventions and the prior art; (3) the level of ordinary skill in the pertinent
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`art; and (4) secondary considerations of non-obviousness.
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`IX. U.S. Patent No. 5,684,555 to Shiba et al. (“Shiba”) in Combination With
`U.S. Patent No. 5,504,601 to Watanabe et al. (“Watanabe”) and U.S. Patent
`No. 5,636,329 to Sukegawa et al. (“Sukegawa”)
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`(31) I have been asked to consider Shiba, Watanabe, and Sukegawa, and to
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`compare the combined teachings of the Shiba, Watanabe, and Sukegawa to claims
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`31, 33, 36, 38, 40, 43, 45, 46, 48, 51, 53, 54, 56, 59, 61, 63, 66, 68, 70, 73, 75, 76,
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`78, 81, and 83 of the ‘204 patent (the “Asserted Claims”). Shiba, Watanabe, and
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`Sukegawa are each directed to an LCD device, the same field of endeavor as the
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`‘204 patent.
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`(32) Paragraph 2 of Claims 31, 38, 46, 54, 61, 68, and 76 and paragraph 3
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`of Claims 46, 54, 61, 68, and 76 require a substrate and thin film transistors over
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`the substrate.
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`(33) Shiba shows an LCD display device having a substrate with thin film
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`transistors. See Shiba col. 3, ll. 58-59, col. 1, ll. 34-36; col. 1, l. 67 to col. 2, l. 1;
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`Fig. 1 and 4.
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`(34) I see no discernable difference between the substrate and thin film
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`transistors of Shiba and the ‘204 patent, which I understand to be referenced by the
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`claim features “a substrate having thin film transistors”.
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`(35) Paragraph 3 of Claims 31 and 38, and paragraph 4 of Claims 46, 54,
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`61, 68, and 76 require “pixel electrodes each electrically connected to one of the
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`thin film transistors.”
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`(36) Shiba describes pixel electrodes each electrically connected to one of
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`the thin film transistors. See Shiba col. 4, ll. 2-4.
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`(37) I see no discernable difference between the pixel electrodes of Shiba
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`and the ‘204 patent, which I understand to be referenced by the claim feature
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`“pixel electrodes each electrically connected to one of the thin film transistors.”
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`(38) Paragraph 4 of Claims 31 and 38, and paragraph 5 of Claims 46, 54,
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`61, 68, and 76 require “a counter substrate facing the substrate.”
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`(39) Shiba describes a counter substrate facing the substrate. See Shiba col.
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`4, ll. 47-49.
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`(40) I see no discernable difference between the counter substrate of Shiba
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`and the ‘204 patent, which I understand to be referenced by the claim feature “a
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`counter substrate facing the substrate.”
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`(41) Paragraph 5 of Claims 31 and 38, and paragraph 6 of Claims 46, 54,
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`61, 68, and 76 require “a liquid crystal material provided between the substrate and
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`the counter substrate.”
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`(42) Shiba describes a liquid crystal material provided between the
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`substrates. See Shiba col. 4, ll. 47-53.
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`(43) I see no discernable difference between the liquid crystal material of
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`Shiba and the ‘204 patent, which I understand to be referenced by the claim feature
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`“a liquid crystal material provided between the substrate and the counter
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`substrate.”
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`(44) Paragraph 6 of Claims 31 and 38, and paragraph 7 of Claim 46 require
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`“a sealant provided between the substrate and the counter substrate, and
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`surrounding the liquid crystal material.”
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`(45) Shiba describes that a sealing agent is used to seal the substrates,
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`surrounding the liquid crystal material. See col. 4, ll. 49-53.
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`(46) I see no discernable difference between the sealant of Shiba and the
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`‘204 patent, which I understand to be referenced by the claim feature “a sealant
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`provided between the substrate and the counter substrate, and surrounding the
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`liquid crystal material.”
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`(47) Paragraphs 7-9 of Claims 31 and 38, paragraph 11 of Claim 31, and
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`paragraph 13 of Claim 38 require “an auxiliary line,” “an external connection line
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`overlapping the auxiliary line with a first insulating film interposed therebetween,”
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`“at least part of the external connection line and at least part of the auxiliary line
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`extending under the sealant,” and “a second insulating film interposed between the
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`sealant and the external connection line.”
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`(48) Shiba describes wiring lines 127 under sealant 113 in a seal region
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`111 that include a two-layered structure of an auxiliary line (bottom conductive
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`layer of wiring lines 127 formed in the step of forming scanning lines Yj) and
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`external connection line (top conductive layer of wiring lines 127 formed in the
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`step of forming data lines Xj) that are partially connected to each other, such that
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`wiring defects can be prevented and manufacturing yield can be improved. Shiba
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`also describes that a first insulating film (gate dielectric 211) is formed on the
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`auxiliary line (bottom conductive layer of wiring lines 127 formed in the step of
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`forming scanning lines Yj) and a second insulating film (protective overcoat 241)
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`is between the sealing agent 113 and the external connection line (top conductive
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`layer of wiring lines 127 formed in the step of forming data lines Xj). See Shiba
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`col. 4, ll. 15-17, col. 6, ll. 37-42; Fig. 3, 4, and 6.
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`(49) I see no discernable difference between the auxiliary line, the external
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`connection line, the first insulating film, and the second insulating film of Shiba
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`and the multilayer structure of the ‘204 patent, which I understand to be referenced
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`by the claim features “an auxiliary line,” “an external connection line overlapping
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`the auxiliary line with a first insulating film interposed therebetween,” “at least
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`part of the external connection line and at least part of the auxiliary line extending
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`under the sealant,” and “a second insulating film interposed between the sealant
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`and the external connection line.”
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`(50) Similarly, paragraphs 8 and 10 of Claim 46 require “a first conductive
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`line and a second conductive line stacked in this order over the substrate and
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`extending under the sealant” and “a first insulating film interposed between the
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`first conductive line and the second conductive line,” and paragraphs 7-9 of Claims
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`54, 61, 68, and 76 require “a first conductive line over the substrate,” “a first
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`insulating film over the first conductive line,” and “a second conductive line over
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`the first insulating film.”
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`(51) While paragraphs 8 and 10 of Claim 46 and paragraphs 7-9 of Claims
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`54, 61, 68, and 76 use different terms than Paragraphs 7-9 of Claims 31 and 38,
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`paragraph 11 of Claim 31, and paragraph 13 of Claim 38, I see no discernable
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`difference between Shiba and the claimed subject matter of the ‘204 patent as
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`explained above. For example, the “auxiliary line” of Claim 31 is a trivial variation
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`to the “first conductive line” of Claim 46.
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`(52) Paragraph 11 of Claims 54, 61, 68, and 76 require “a transparent
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`conductive layer over a first region of the second conductive line.”
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`(53) Shiba shows that external electrical connections are formed over a
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`first region (common pad 751) of the second conductive line (top conductive layer
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`of wiring lines 127 formed in the step of forming the data lines Xj). The common
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`pad 751 is formed by an extension of the top conductive layer of wiring lines 127
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`formed in the step of forming the data liens Xj). See Shiba fig. 3.
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`(54) Shiba teaches that a two layered structure consisting of two
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`conductive layers that are partially connected improves yield. Such a two layered
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`structure has been shown in forming the wirings 127 using one layer formed in the
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`step of forming the scanning lines and one layer formed in the step of forming the
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`data lines. See Shiba col. 6, ll. 37-42.
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`(55) A person with ordinary skill in the art would understand that a two
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`layered structure consisting of two conductive layers that are partially connected
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`can also be used in forming the pads where external electrical connections are
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`made. In these pads a person with ordinary skill in the art would select the top
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`layer of the pad to be formed from a transparent conductive film such as indium tin
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`oxide. Transparent conductive films were well known to be materials that resist
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`oxidation and thus reliable electrical connections can be formed.
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`(56) Sukegawa explains that in a multilayer structure for providing an
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`external connection through a flexible wiring substrate 31 and anisotropic
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`conductive film 10, a transparent conductive layer over a first region of the second
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`conductive line is included to provide connectivity to external circuits and to
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`provide a layer of protection against oxidation or corrosion. See Sukegawa, col. 3,
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`ll. 37-38; col. 6, ll. 9-20; Fig. 2C, showing a transparent conductive layer
`
`(transparent conductive film 8) over a first region of the second wiring (upper layer
`
`metal wiring 7).
`
`
`
`20
`
`CMI Exhibit 1007
`20
`
`
`
`
`
`(57) I see no discernable difference between the transparent conductive
`
`layer of Sukegawa and the transparent conductive layer of the ‘204 patent, which I
`
`understand to be referenced by the claim feature “a transparent conductive layer
`
`over a first region of the second conductive line.” One of ordinary skill in the art
`
`would have included the transparent conductive film of Sukegawa in the common
`
`pad of Shiba, thus creating a reliable electrical connection as the transparent
`
`conductive film was well known to form a layer of protection from oxidation.
`
`(58) Paragraph 10 of Claims 31 and 38 and paragraph 11 of Claim 38
`
`requires “an adjustment layer, at least part of the adjustment layer extending under
`
`the sealant.” Paragraphs 11, 12, and 13 of Claim 38 further require a second
`
`adjustment layer overlapping the first adjustment layer with the first insulating film
`
`interposed therebetween, at least part of the second adjustment layer extending
`
`under the sealant, and a second insulating film interposed between the sealant and
`
`the second adjustment layer.
`
`(59) Watanabe explains that a structure having a first adjustment layer and
`
`
`
`21
`
`CMI Exhibit 1007
`21
`
`
`
`a second adjustment layer, with the first insulating film interposed therebetween,
`
`and at least part of the second adjustment layer extending under the sealant,
`
`provides an even cell gap height to the display device, resulting in a high quality
`
`image. See Watanabe Abstract, col. 12, ll. 52-59; Fig. 5, enlarged below, showing
`
`a first adjustment layer (first conducting layer of substrate gap adjusting layer 25
`
`formed with the material of the scanning lines 9) and second adjustment layer
`
`(second conducting layer of substrate gap adjusting layer 25 formed with the
`
`material of the signal lines 5) under sealing member 19.
`
`
`
`(60)
`
` The substrate gap adjusting layers 25 and 27 are multilayer structures
`
`consisting of alternating conducting and insulating films. The first conducting layer
`
`is made from material which is the same as that of the scanning lines 9. On top of
`
`the first conducting layer, there is the first insulating layer (material of the layer
`
`insulating film 201). On top of the first insulating film there is the second
`
`conducting layer (material of the signal lines 5) and on top of the second
`
`
`
`22
`
`CMI Exhibit 1007
`22
`
`
`
`conducting layer there is the second insulating layer (material of the protecting
`
`film 205). See Watanabe, col. 12, ll. 52-59. Though Watanabe does not include a
`
`cross section specifically for the substrate gap adjusting layers 25 and 27, based on
`
`the text description a person with ordinary skill will understand that the order of
`
`the various conducting and insulating layers will be as shown in Fig. 2B, which is
`
`of the first embodiment. As shown in Fig. 2B the material of the insulating film
`
`201 is interposed between substrate gap adjusting layer 21 which is formed from
`
`the same material as the scanning lines 9, and the lead portions 13 formed from the
`
`same material as the signal lines 5. Furthermore, the top layer of the substrate gap
`
`adjusting layers 25 and 27 is the second insulating film (material of the protecting
`
`film 205).
`
`
`(61) I see no discernable difference between the first and second
`
`adjustment layers of Watanabe and the first and second adjustment layers of the
`
`‘204 patent, which I understand to be referenced by the claim features of “an
`
`
`
`23
`
`CMI Exhibit 1007
`23
`
`
`
`adjustment layer, at least part of the adjustment layer extending under the sealant,”
`
`“a second adjustment layer overlapping the first adjustment layer with the first
`
`insulating film interposed therebetween, at least part of the second adjustment
`
`layer extending under the sealant,” or “a second insulating film interposed between
`
`the sealant and … the second adjustment layer” One of ordinary skill in the art
`
`would have included substrate gap adjustment layers under the sealant, as shown
`
`by Watanabe, into the display of Shiba, thus providing an even cell gap height and
`
`a high quality image.
`
`(62) Similarly, paragraphs 9-11 of Claim 46 require “a third conductive
`
`line and a fourth conductive line stacked in this order over the substrate and
`
`extending under the sealant” and that the first insulating film is interposed between
`
`the third conductive line and the fourth conductive line.
`
`(63) While paragraphs 9-11 of Claim 46 use different terms than
`
`paragraphs 10-11 of Claim 38, I see no discernable difference between Watanabe
`
`and the claimed subject matter of those paragraphs as explained above. For
`
`example, the “first adjustment layer” of Claim 38 is a trivial variation to the “third
`
`conductive line” of Claim 46.
`
`(64) Paragraph 14 of Claims 54 and 61 require “a conductive layer over the
`
`substrate.”
`
`(65) While paragraph 14 of Claims 54 and 61 use different terms than
`
`
`
`24
`
`CMI Exhibit 1007
`24
`
`
`
`paragraph 10 of Claim 38, I see no discernible difference between Watanabe and
`
`the claimed subject matter of those paragraphs as explained above. For example,
`
`the “first adjustment layer” of Claim 38 is a trivial variation to the “conductive
`
`layer” of Claims 54 and 61.
`
`(66) Paragraph 12 of Claim 31, paragraph 14 of Claim 38, and paragraph
`
`13 of Claim 46 require “a flexible printed circuit over and in electrical contact with
`
`the external connection line through a transparent conductive film.”
`
`(67) Shiba describes that a flexible printed circuit (wiring film 711) is over
`
`and in electrical contact with the external connection line (top conducting layer of
`
`wirings 127 formed in the step of forming data lines Xj) through anisotropic film
`
`881. The top conducting layer of wirings 127 formed in the step of forming data
`
`lines Xj, is extended and forms the pad 751 as shown in Fig 3 and 4 which is
`
`electrically connected to the flexible printed circuit. See Shiba Figs. 3 and 4.
`
`
`
`25
`
`CMI Exhibit 1007
`25
`
`
`
`
`
`(68) Shiba teaches that a two layered structure consisting of two
`
`
`
`conductive layers that are partially connected improves yield. Such a two layered
`
`structure has been shown in forming the wirings 127 using one layer formed in the
`
`step of forming the scanning lines and one layer formed in the step of forming the
`
`data lines. See Shiba col. 6, ll. 37-42.
`
`(69) A person with ordinary skill in the art would understand that a two
`
`layered structure consisting of two conductive layers that are partially connected
`
`can also be used in forming the pads where the connections with the flexible
`
`printed circuit are made. In these pads a person with ordinary skill in the art would
`
`select the top layer of the pad to be formed from a transparent conductive film such
`
`as indium tin oxide. Transparent conductive films were well known to be
`
`
`
`26
`
`CMI Exhibit 1007
`26
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`
`
`materials that resist oxidation and thus reliable electrical connections can be
`
`formed.
`
`(70) Sukegawa explains that in a multilayer wiring structure for providing
`
`an external connection, electrical contact from the flexible printed circuit to the
`
`external connection line is through a transparent conductive film that provides
`
`connectivity and a layer of protection against corrosion. See Sukegawa col. 3, ll.
`
`37-38; col. 6, ll. 9-20; Fig. 2C, showing the second wiring (upper layer metal
`
`wiring 7) a
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