`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`6,404,480
`
`June 11, 2002
`
`In re Inter Partes Review of:
`
`U.S. Patent No.
`
`
`Issued:
`
`
` Yoshiharu Hirakata
`Inventor:
` Shunpei Yamazaki
`
`
`
`Application No.: 09/734,177
`
`
`Filed:
`
`Assignee:
`
`
`
`Title:
`
`
`)
`)
`) TRIAL NUMBER: IPR2013-00028
`)
`)
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`)
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`December 12, 2000
`) FILED ELECTRONICALLY
`
`Semiconductor Energy) PER 37 C.F.R. § 42.6(b)
`Laboratory Co., Ltd. )
`)
`)
`)
`
`Contact Structure
`
`
`
`
`Mail Stop Patent Board (37 C.F.R. § 42.6(b)(2))
`Patent Trial and Appeal Board
`U.S.P.T.O.
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`DECLARATION OF MILTIADIS HATALIS, Ph.D.
`
`I.
`
`Background and Qualifications
`
`(1) My name is Miltiadis Hatalis. I am currently a Professor at Lehigh
`
`University in the Department of Electrical and Computer Engineering. I have
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`studied, taught, and practiced in the relevant flat panel display technology for over
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`1
`
`EXHIBIT 1007
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`
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`25 years.
`
`(2)
`
`I received my Doctor of Philosophy (Ph.D.) degree in the field of
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`Electrical and Computer Engineering from Carnegie Mellon University in 1987.
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`The topic of my Ph.D. dissertation research was “Crystallization of Amorphous
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`Silicon Films and its Application in Bipolar and Thin Film Transistors.” I received
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`my Masters of Science (M.S.) degree in Electrical and Computer Engineering in
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`1984 from the State University of New York at Buffalo and my Bachelor of
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`Science (B.S.) degree in Physics in 1982 from the Aristotle University of
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`Thessaloniki in Greece.
`
`(3) Upon receiving my Ph.D. degree, I joined the faculty of Lehigh
`
`University in the Department of Electrical and Computer Engineering as an
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`Assistant Professor. I was promoted to the rank of Associate Professor with tenure
`
`in 1991 and to the rank of Professor in 1995. From 1987-1992, I served as
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`Associate Director of Lehigh's “Microelectronics Research Laboratory.”
`
`(4)
`
`In 1992, I founded and became Director of the “Display Research
`
`Laboratory,” which was the first academic laboratory in the United States
`
`dedicated to research and development of Thin Film Transistors (TFTs) for Active
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`Matrix Liquid Crystal Displays (AMLCDs) and Active Matrix Organic Light
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`Emitting Diode (AMOLEDs) displays. As Director of Lehigh's “Display Research
`
`Laboratory,” I have raised over $10 million through research contracts and grants
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`2
`
`
`
`to support the laboratory's research and development activities on thin film
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`transistors and their application to flat panel displays. These contracts and grants
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`were funded by the Defense Advanced Research Program Agency (DARPA), the
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`Army Research Laboratory (ARL), the National Science Foundation (NSF), the
`
`National Aeronautics and Space Administration (NASA), the State of
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`Pennsylvania, and a variety of industrial companies including IBM, Kodak, Sharp,
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`Northrop Grumman, and others.
`
`(5) As a faculty member, I supervised the research of eighteen Ph.D.
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`dissertations in the technical field of TFTs and, along with my graduate students,
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`published over 150 technical publications in scientific journals or conferences in
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`the field of thin film transistors and their applications in flat panel displays. In
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`addition to the aforementioned Ph.D. dissertations, I have also supervised a large
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`number of graduate student master’s theses and undergraduate research projects.1 I
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`have taught a number of different undergraduate and graduate level courses in the
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`Electrical and Computer Engineering department at the Lehigh University dealing
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`with the physics, technology, and the design of solid-state devices and circuits. I
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`have also introduced and regularly teach a course on “Semiconductor Material and
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`Device Characterization,” and I have also reorganized a course on “Introduction to
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`Design of Very Large Scale Integration (VLSI).”
`
`1 More information on this subject can be found on my research group web pages:
`www.ece.lehigh.edu/DRL
`
`3
`
`
`
`(6) As part of my research, I utilize much of the same equipment and
`
`many of the same microfabrication processes that are relevant to U.S. Patent No.
`
`6,404,480 (hereinafter referred to as the “‘480 patent”), including: Plasma-
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`Enhanced Chemical Vapor Deposition (PECVD) for intrinsic hydrogenated-
`
`amorphous silicon, silicon nitride and silicon dioxide films; sputter and e-beam
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`deposition tools for aluminum, indium-tin-oxide, tantalum and other metallic thin
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`films; photolithographic tools for spinning, exposure and developing photoresist
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`patterns; as well as plasma or wet etching tools for removing various thin film
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`materials from the substrate. Furthermore, I also utilize several tools for the
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`characterization of the materials and structures used in thin film transistors
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`including: optical microscopes, Scanning Electron Microscopy (SEM),
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`Transmission Electron Microscopy (TEM), and Atomic Force Microscopy (AFM).
`
`I also utilize a variety of electrical characterization techniques and instruments for
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`testing the electrical performance of completed TFT circuits and flat panel
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`displays.
`
`(7) As part of my research, I pioneered a technique for crystallizing
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`amorphous silicon. The technique I pioneered has been used in the manufacture of
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`small polysilicon TFT AMLCDs for over a dozen years, and, more recently,
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`polysilicon TFTs have also been used for AMOLED displays. In addition, many
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`industrial and academic laboratories have recently initiated R&D activities related
`
`4
`
`
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`to the fabrication of polysilicon thin film transistors on flexible metal foil
`
`substrates and their application to flexible displays. Such research flows from the
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`accomplishments of my research group in this technical field.
`
`(8) My industrial experience includes work at the XEROX Palo Alto
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`Research Laboratory and various consulting projects with flat panel display
`
`companies as well as companies producing equipment for the manufacture of flat
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`panel displays. All of these projects were related to the thin film transistors and
`
`their application to flat panel displays.
`
`(9)
`
`I am a member of several professional organizations including the
`
`Society for Information Display (SID), and the Electron Device Society of the
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`Institute of Electrical and Electronics Engineers (IEEE). I have also been the chair
`
`or co-chair at numerous national and international conferences/symposiums
`
`including several SID sponsored Workshops on Active Matrix Liquid Crystal
`
`Displays and a Materials Research Society Symposium on Flat Panel Displays. I
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`have co-authored two book chapters, one dealing with the “Polysilicon TFT
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`Technology” and another on application of “Polysilicon TFTs in AMOLED
`
`Displays.” I have served as a reviewer for technical papers submitted to several
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`scientific journals and have also served as a reviewer for several years for the
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`National Science Foundation Small Business Innovative Research (SBIR)
`
`program.
`
`5
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`
`
`(10) A copy of my latest curriculum vitae (C.V.) is attached as Appendix
`
`A and includes a list of my publications.
`
`II. My Status as an Independent Expert Witness
`
`(11)
`
`I have been retained in this matter by Chimei Innolux Corp.
`
`(“Petitioner”) to provide an analysis of the scope and content of the ‘480 patent
`
`relative to the state of the art at the time of the earliest application underlying the
`
`‘480 patent.
`
`(12)
`
`I am being compensated at the rate of $300 per hour for my work. My
`
`fee is not contingent on the outcome of any matter or on any of the technical
`
`positions I explain in this declaration. I have no financial interest in Petitioner.
`
`(13)
`
`I have been informed that Semiconductor Energy Laboratory Co., Ltd.
`
`(hereinafter referred to as “Patentee”) owns the ‘480 patent. I have no financial
`
`interest in the Patentee or the ‘480 patent nor have I ever had any contact with the
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`Patentee, or the inventors of the ‘480 patent, Yoshiharu Hirakata and Shunpei
`
`Yamazaki.
`
`III. Description of the Relevant Field and the Relevant Timeframe
`
`(14)
`
`I have carefully reviewed the ‘480 patent.
`
`(15) For convenience, all of the information that I considered in arriving at
`
`my opinions is listed in Appendix B.
`
`(16) Based on my review of these materials, I believe that the relevant field
`
`6
`
`
`
`for purposes of the ‘480 patent is semiconductor processes and device related to
`
`flat panel displays. I have been informed that the relevant timeframe is March 27,
`
`1997.
`
`(17) As described in Section I above, I have extensive experience in the
`
`relevant field. Based on my experience, I have a good understanding of the
`
`relevant field in the relevant timeframe.
`
`IV.
`
`The Person of Ordinary Skill in the Relevant Field in the Relevant
`Timeframe
`
`(18)
`
`I have been informed that “a person of ordinary skill in the relevant
`
`field” is a hypothetical person to whom an expert in the relevant field could assign
`
`a routine task with reasonable confidence that the task would be successfully
`
`carried out. I have been informed that the level of skill in the art is evidenced by
`
`the prior art references. The prior art discussed herein demonstrates that a person
`
`of ordinary skill in the art, at the time the ‘480 patent was filed, was aware of
`
`liquid crystal display structures, including techniques for providing connections
`
`therein, including various arrangements of conductive spacers for providing a
`
`connection between the opposing substrates.
`
`(19) Based on my experience, I have an understanding of the capabilities
`
`of a person of ordinary skill in the relevant filed. I have supervised and directed
`
`many such persons over the course of my career.
`
`7
`
`
`
`V.
`
`Background of the Technology
`
`(20)
`
`In LCDs, an image is divided into small elements called pixels. In a
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`color LCD display, each pixel is further divided into three sub-pixels, one for each
`
`of the three primary colors red, green, and blue. Each pixel (in a monochrome
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`display) or sub-pixel (in a color display) contains a TFT, a capacitor, and a pixel
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`electrode.
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`(21) The TFT serves as a switch that, when turned ON, allows an electrical
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`current to flow into and charge the capacitor to a specific voltage. When the TFT
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`switch is turned OFF, current cannot flow through it and thus, the voltage
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`established at the capacitor is maintained until the next frame period, at which time
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`the switch will be turned on again in order to update the voltage stored in the
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`capacitor.
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`(22) The voltage stored in the capacitor also appears to the pixel electrode.
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`This voltage sets an electric field across the liquid crystal material that is on-top of
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`the electrode; the higher the stored voltage the higher the electric field. The
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`magnitude of the electric field across the pixel electrode will determine the optical
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`properties of the LCD material and this, in turn, will determine the amount of light
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`that will pass through the pixel or sub-pixel.
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`(23) Pixels are provided by an array of discrete LCD semiconductor
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`devices that form the LCD display. Individual pixels are switched by way of the
`
`8
`
`
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`TFTs in accordance with scan and drive control circuitry. The number of pixels
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`depends upon the display format. For example, the VGA format contains 640x480
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`pixels in a monochrome display, and 640x480x3 in a color display. There are
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`many display formats ranging from the aforementioned VGA (640x480) format up
`
`to an HDTV format, which includes up to 1920x1080x3 pixels with over six
`
`million thin film transistors (TFTs).
`
`VI.
`
`The ‘480 Patent
`
`(24) The ‘480 patent (Ex. A) describes problems with prior art LCD
`
`structures with respect to the nonuniformity of spacing between the two opposing
`
`substrates. (Ex. A at col. 2, ln. 60 – col. 3, ln. 6). Figure 13 of the ‘480 patent
`
`depicts a prior art LCD structure, which includes a conductive spacer 26 between
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`the first substrate 11 and the second substrate 23 in a common contact portion.
`
`(25) Figure 6 of the ‘480 patent depicts the alleged point of novelty of the
`
`‘480 patent. As shown in Figure 6, the LCD structure is substantially similar to the
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`prior art LCD structure depicted in Figure 13. According to the alleged invention
`
`of the ‘480 patent, however, the conductive spacer 401 has been moved from an
`
`9
`
`
`
`opening in the dielectric layer (see location of figure element 26 in the prior art
`
`structure depicted in Figure 13) to a position on top of the remaining dielectric
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`layer (figure element 319 in Figure 6).
`
`(26) A side-by-side comparison between Figure 6 and prior art Figure 13
`
`of the ‘480 patent highlights that the difference is that the conductive spacer is held
`
`over the second interlayer insulating film 319 rather than in an opening therein (as
`
`annotated in red below).
`
`(27)
`
`Independent claims 1, 6, and 11, of the ‘480 patent recite the LCD
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`structure depicted in Figures 6 and 13. Regarding the placement of the conductive
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`spacers, independent claims 1, 6, and 11 require that “at least one of said
`
`conductive spacers is held over said second insulating film and in contact with
`
`10
`
`
`
`both said second conductive film and said third conductive film.” (Emphasis
`
`added). Thus, the independent claims require that the conductive spacer not be
`
`placed in an opening of the second insulating film, but rather, over said second
`
`insulating film.
`
`VII. Claim Interpretation
`
`(28)
`
`In proceedings before the USPTO, I understand that the claims of an
`
`unexpired patent are to be given their broadest reasonable interpretation in view of
`
`the specification from the perspective of one skilled in the art. I have been
`
`informed that the ‘480 patent has not expired. In comparing the claims of the ‘480
`
`patent to the known prior art, I have carefully considered the ‘480 patent, and the
`
`‘480 prosecution history based upon my experience and knowledge in the relevant
`
`field. I have not encountered any “coined” terms or terms that require
`
`consideration of a special or explicitly defined meaning. Instead, the claim terms
`
`of the ‘480 patent are used in their ordinary and customary sense as one skilled in
`
`the relevant field would understand them.
`
`VIII. Unpatentability Based on Prior Art in the Present Proceedings
`
`(29)
`
`I am informed that the ‘480 patent is a division of U.S. Patent
`
`Application No. 09/361,218, filed on July 27, 1999, which is a division of U.S.
`
`Patent Application No. 09/046,685, filed on March 24, 1998. Additionally, ‘480
`
`patent claims priority to a foreign patent, Japanese Patent Application No. JP 9-
`
`11
`
`
`
`094606, filed on March 27, 1997. I am further informed that this means that the
`
`‘480 patent is considered to have been filed on March 27, 1997 for purposes of
`
`determining whether a reference constitutes prior art. Thus, a reference will
`
`qualify as prior art if it disclosed or suggested the invention of the ‘480 patent prior
`
`to March 27, 1997.
`
`(30)
`
`I have been informed that a patent claim can be found unpatentable as
`
`obvious where the differences between the subject matter sought to be patented
`
`and the prior art are such that the subject matter as a whole would have been
`
`obvious at the time the invention was made to a person having ordinary skill in the
`
`relevant field. I understand that an obviousness analysis involves a consideration
`
`of (1) the scope and content of the prior art; (2) the differences between the
`
`claimed inventions and the prior art; (3) the level of ordinary skill in the pertinent
`
`art; and (4) secondary considerations of non-obviousness.
`
`IX.
`
`Patentee’s Admitted Prior Art (“APA”) in View of Japanese Patent
`Publication No. JP 5-2243333 to Moriyama (“Moriyama”) Invalidates
`Claims 1, 5, 6, 10, 11, and 15 of the ‘480 Patent
`
`(31)
`
`I have been asked to consider the admitted prior art (“APA”) together
`
`with Moriyama, and to compare these combined teachings to claims 1, 5, 6, 10, 11,
`
`and 15 of the ‘480 patent.
`
`(32) Figures 12-15 of the ‘480 patent (designated “Prior Art” by the
`
`Patentee) illustrate what I understand to be well established LCD structures that
`
`12
`
`
`
`were known to be in existence prior to March 27, 1997. For example, the very
`
`same standard LCD semiconductor device structures are found in the Moriyama
`
`reference (e.g., Figures 4-7). As such, I have been informed that to the extent
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`certain aspects depicted in Figures 12-15 are referenced in claims 1, 5, 6, 10, 11,
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`and 15 of the ‘480 patent, they are deemed to be “old” or “Admitted Prior Art.” I
`
`identify the first 10 elements (1.1-1.10) of independent claims 1, 6, and 11 as
`
`referencing such standard features depicted in Figures 12-15. I note that the first
`
`10 elements of claims 1, 6, and 11 are identical. The only element in claim 1 that
`
`is not necessarily found in these figures, or described in the accompanying
`
`descriptions of these figures in the ‘480 patent specification, is element 1.11
`
`(which is identical to claim 6 element 6.12 and claim 11 element 11.11), which
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`states “wherein at least one of said conductive spacers is held over said second
`
`interlayer insulating film and in contact with both said second conductive film and
`
`said third conductive film.” Independent claim 6 includes element 6.11, which
`
`states “wherein said conductive spacers are dispersed into a sealing material,”
`
`which is not necessarily found in Figures 12-15, or described in the accompanying
`
`descriptions of these figures in the ‘480 patent specification. In addition,
`
`independent claim 11 includes element 11.12, which states “wherein each of said
`
`openings occupies an area larger than an area occupied by each of said conductive
`
`spacers,” which is disclosed in the description of the prior art in the ‘480 patent.
`
`13
`
`
`
`(33) Although not explicitly identified in the description of the prior art in
`
`the ‘480 patent, a person of ordinary skill in the art would understand that the layer
`
`between the substrate 11 and the conductive layer 21 (highlighted in yellow, below
`
`in prior art Figure 13) would necessarily have to be an insulating film.
`
`This layer is required to electrically isolate the conductive structures in the
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`common contact portion from the TFTs. If this layer was not an insulator, the
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`common contact portion would be short circuited to the TFT. Furthermore, the
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`interlayer insulating film serves as the first isolation layer of the TFT structure that
`
`helps to isolate the source and drain electrodes from the gate electrode of the TFT
`
`17.
`
`(34) Moriyama is directed to an LCD device, the same field of endeavor as
`
`the ‘480 patent. Moriyama also describes a structure for providing a contact
`
`between the opposing LCD substrates, and does so in the same manner as
`
`described in ‘480 patent.
`
`(35) Moriyama describes a structure for providing a contact between the
`
`opposing substrates of a terminal of an LCD device. As shown in Figures 6 and
`
`14
`
`
`
`7(a) of Moriyama, the terminal includes an insulating layer 5 that has a number of
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`contact holes 2 formed in it. Moriyama at ¶ 6; Figures 6, 7(a).
`
`The electrical contact between the two opposing substrates 14, 20 is made through
`
`the metal particles 16. Moriyama at ¶ 7. As shown in Figure 7(a) above, the metal
`
`particles are held over the insulating layer 5, rather than in the contact holes 2.
`
`(36) Moriyama describes another embodiment of a structure for providing
`
`a contact between the opposing substrates of a terminal of an LCD device in
`
`Figures 4 and 5. As shown in Figures 4 and 5 of Moriyama, the contact area
`
`includes a number of contact holes 2 formed in it. Moriyama at ¶¶ 20-21; Figure 4.
`
`15
`
`
`
`Figure 5 shows a cross-sectional drawing along the section D-D’ in Figure 4.
`
`Moriyama at ¶ 20; Figures 4, 5. The electrical contact between the two opposing
`
`substrates is made through the metal particles 16. Moriyama at ¶ 21. As shown in
`
`Figure 5 above, the metal particles are held over the insulating layer (the layer
`
`between the underlying metal layer 1 and the transparent metal 4), rather than in
`
`the contact holes 2.
`
`(37)
`
`I see no discernable difference between the above described use of
`
`conductive spacers held over the insulating layer in Moriyama and claim elements
`
`1.11, 6.12, and 11.11, which state “wherein at least one of said conductive spacers
`
`is held over said second interlayer insulating film and in contact with both said
`
`second conductive film and said third conductive film.”
`
`(38) Moriyama further describes that the conductive spacers 16 may be
`
`dispersed in a sealing material, which it describes as “a thermal curable resin 22,”
`
`also shown in Figure 7(a). Moriyama at ¶ 7; Figure 7(a).
`
`One of ordinary skill in the art would recognize that the thermal curable resin 22 of
`
`Moriyama is a sealing material.
`
`16
`
`
`
`(39)
`
`I see no discernable difference between the above described
`
`dispersion of the metal particles 16 in a thermal resin 22 and claim element 6.11,
`
`which states “wherein said conductive spacers are dispersed into a sealing
`
`material.”
`
`(40) As shown in prior art Figure 13 above, the APA discloses that the
`
`contact holes in the second interlayer insulation layer occupy an area larger than an
`
`area occupied by the conductive spacers (26).
`
`(41) Figure 7(a) of Moriyama also depicts that the contact holes 2 occupy
`
`an area larger than an area occupied by the metal particles 16. Moriyama at Figure
`
`7(a).
`
`(42)
`
`I see no discernable difference between the above described relation
`
`of the larger area of the contact holes to the area occupied by the metal particles 16
`
`in Moriyama and claim element 11.12, which states “wherein each of said
`
`openings occupies an area larger than an area occupied by each of said conductive
`
`spacers.”
`
`(43) Dependent claims 5, 10, and 15 of the ‘480 patent depend from
`
`independent claims 1, 6, and 11, respectively. Claims 5, 10, and 15 of the ‘480
`
`patent include the identical language in that they state “wherein said active matrix
`
`display device is a liquid crystal display device.” Figures 12-15 of the ‘480 patent
`
`are described the specification as being directed to a “prior art active-matrix liquid
`
`17
`
`
`
`crystal display.” ‘480 patent at col. 1, ll. 48-50; Figures 12-15. Therefore, the
`
`APA discloses the feature claimed in claims 5, 10, and 15 of the ‘480 patent.
`
`(44) Having now explained my assessment of the scope and content of the
`
`APA and Moriyama, I find that the APA provides all the elements of claims 1, 5,
`
`6, 10, 11, and 15 of the ‘480 patent, with the exception of those described above;
`
`however, those features are clearly taught by Moriyama.
`
`(45)
`
`I understand the APA to be naturally combinable with the teachings of
`
`Moriyama as both are directed to the same field of endeavor and both include
`
`structures including conductive spacers for providing an electrical connection
`
`between the opposing substrates of an LCD device.
`
`(46) Combining the teachings of the APA with the placement of the
`
`conductive spacers disclosed in Moriyama would have been well recognized in the
`
`semiconductor art because providing the spacer on the conductive layer on the
`
`higher surface over the insulating layer will ensure a good electrical contact
`
`between the opposing substrates through the spacers.
`
`(47) Combining the teachings of the APA with the disclosure in Moriyama
`
`that the openings in the insulating layer have an area larger than the conductive
`
`spacers would have been well recognized in the semiconductor art because if the
`
`openings are smaller than the conductive spacers, the spacers may become trapped
`
`in the opening, thereby impeding the movement of the spacers as the substrates are
`
`18
`
`
`
`being joined. It was well known that if the opening is larger than the spacer as
`
`disclosed in Moriyama, the spacers would be allowed to simply fall into the
`
`opening, which would allow the spacers above the insulating layer to move freely.
`
`X.
`
`Patentee’s APA in view of Moriyama and U.S. Patent No. 4,600,273 to
`Ohno (“Ohno”) Invalidates Claims 2, 7, and 12 of the ‘480 Patent
`
`(48)
`
`I have been asked to consider the APA together with Moriyama and
`
`Ohno, and to compare these combined teachings to claims 2, 7, and 12 of the ‘480
`
`patent.
`
`(49) As set forth in Section IX above, the APA of the ‘480 patent in view
`
`of Moriyama invalidates independent claims 1, 6, and 11 of the ‘480 patent.
`
`Dependent claims 2, 7, and 12 of the ‘480 patent depend from independent claims
`
`1, 6, and 11, respectively. Claims 2, 7, and 12 of the ‘480 patent include the
`
`identical language in that they state “wherein each of said conductive spacers is a
`
`sphere coated with gold.” Although the APA and Moriyama disclose the
`
`conductive spacer as being a sphere, they do not specifically describe that the
`
`conductive spacer is a sphere coated with gold.
`
`(50) Ohno is directed to an LCD device, the same field of endeavor as the
`
`‘480 patent. Ohno also describes a structure for providing a contact between the
`
`opposing LCD substrates, and does so using spherical conductive spacers, which
`
`may be coated with gold, as described in the ‘480 patent.
`
`(51) Ohno discloses “providing a contact media which generally comprises
`
`19
`
`
`
`a non-conductive core material disposed between the upper and lower electrodes of
`
`the display panel. The core material is made conductive by electroless plating
`
`thereon of one or more conductive materials. … The non-conductive core particles,
`
`such as glass beads, glass fibers, or plastic balls, can be formed by injection-
`
`molding or by cooling after they are melted and passed through an orifice, having a
`
`fixed diameter.” Ohno at col. 2, ll. 6-18. “An electroless plating bath consists of a
`
`plating bath using at least one of the metals selected from the group consisting of
`
`gold, nickel, copper, silver, cobalt, and tin.” Ohno at col. 4, ll. 42-44.
`
`(52)
`
`I see no discernable difference between the above described use of a
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`gold coated conductive sphere as a spacer between the opposing substrates of an
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`LCD device in Ohno and claim elements 2.1, 7.1, and 12.1, which state “wherein
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`each of said conductive spacers is a sphere coated with gold.”
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`(53) Having now explained my assessment of the scope and content of the
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`APA, Moriyama, and Ohno, I find that the APA and Moriyama provides all the
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`elements of claims 2, 7, and 12 of the ‘480 patent, with the exception of that
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`described above; however, that feature is clearly taught by Ohno.
`
`(54)
`
`I understand the APA and Moriyama to be naturally combinable with
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`the teachings of Ohno as all are directed to the same field of endeavor and all
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`include structures which include a conductive spacer between the opposing
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`substrates of an LCD device. Ohno discloses the use of a spherical conductive
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`20
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`
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`spacer, which is coated with gold.
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`(55) Combining the APA and Moriyama with the gold coated spherical
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`spacers disclosed in Ohno would have been well recognized in the semiconductor
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`arts as providing conductive spacers of a high conductivity, i.e., low resistance, and
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`improved reliability.
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`XI.
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`Japanese Patent Publication No. JP 6-289415 to Kitawada (“Kitawada”)
`in View of Moriyama Invalidates Claims 1, 5, 6, 10, 11, and 15 of the
`‘480 Patent
`
`(56)
`
`I have been asked to consider Kitawada together with Moriyama, and
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`to compare these combined teachings to claims 1, 5, 6, 10, 11, and 15 of the ‘480
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`patent.
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`(57) The first 10 limitations of independent claims 1, 6, and 11 are all
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`identical.
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`(58) Claim elements 1.1, 6.1, and 11.1 state “[a]n active matrix display
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`device.” Kitawada is directed to “an active-matrix liquid crystal display device.”
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`Kitawada at ¶ 1. Kitawada is in the same field of endeavor as the ‘480 patent.
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`Kitawada also describes a structure for providing a contact between the opposing
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`LCD substrates, and does so in the same manner as described in ‘480 patent.
`
`(59)
`
`I see no discernable difference between the stated subject matter of
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`Kitawada and claim elements 1.1, 6.1, and 11.1.
`
`(60)
`
` Claim elements 1.2, 6.2, and 11.2 state “a first substrate.” Kitawada
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`21
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`
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`discloses a first substrate, namely, “device substrate 301.” Kitawada at ¶ 15;
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`Figure 3(c).
`
`(61)
`
`I see no discernable difference between the substrate of Kitawada and
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`the “first substrate” recited in claim elements 1.2, 6.2, and 11.2.
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`(62) Claim elements 1.3, 6.3, and 11.3 state “a first interlayer insulating
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`film provided over said first substrate.” Kitawada discloses a first interlayer
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`insulating film provided over said first substrate. In particular, as shown in Figure
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`3(c), a person of ordinary skill in the art would understand that the layer provided
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`over the substrate 301 would necessarily have to be a first interlayer insulating
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`film. This layer is required to electrically isolate the wiring 318 from, e.g., the
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`wiring 317.
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`Further, as shown in Figure 1(c), this same layer is identified as the “first inter-
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`layer insulating film 119 over device substrate 101.” Kitawada at ¶ 8; Figure 1(c).
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`22
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`
`
`(63)
`
`I see no discernable difference between the insulating film provided
`
`on the substrate of Kitawada and the “first interlayer insulating film provided over
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`said first substrate” recited in claim elements 1.3, 6.3, and 11.3.
`
`(64) Claim elements 1.4, 6.4, and 11.4 state “a first conductive film
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`provided on said first interlayer insulating film.” Kitawada discloses a first
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`conductive film provided on said first interlayer insulating film, namely, the wiring
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`318 is provided on the first insulating film. Kitawada at ¶ 18; Figure 3(c).
`
`(65)
`
`I see no discernable difference between the conductive film provided
`
`on the first insulating film of Kitawada and the “first conductive film provided on
`
`said first interlayer insulating film” recited in claim elements 1.4, 6.4, and 11.4.
`
`(66) Claim elements 1.5, 6.5, and 11.5 state “a second interlayer insulating
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`film provided on said first conductive film, said second interlayer insulating film
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`having at least two openings.” Kitawada discloses a second interlayer insulating
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`film provided on the first conductive film, where the second interlayer insulating
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`film has at least two openings. In particular, “transparent organic insulating film
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`319 over the driver circuit” is provided over the wiring 318 and pixel electrode
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`314, as shown in Figures 3(b) and 3(c). Kitawada at ¶ 16; Figures 3(b), 3(c). The
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`23
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`
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`openings in the second insulating layer are annotated in Figures 3(b) and 3(c)
`
`below.
`
`(67)
`
`I see no discernable difference between the second insulating film
`
`provided on the first conductive film of Kitawada and the “second interlayer
`
`insulating film provided on said first conductive film, said second interlayer
`
`insulating film having at least two openings” recited in claim elements 1.5, 6.5, and
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`11.5.
`
`(68) Claim elements 1.6, 6.6, and 11.6 state “a second conductive film
`
`provided on said second interlayer insulating film and in said openings.” Kitawada
`
`discloses a second conductive film provided on the second interlayer insulating
`
`film and in said openings. In particular, the “pixel electrode such as ITO 314 is
`
`formed over this transparent organic insulating film ….” Kitawada at ¶ 16; Figures
`
`3(b), 3(c). In addition, the electrode 305 and the pixel electrode 314 are provided
`
`on the second insulating film and in the openings thereof, as shown in Figures 3(b)
`
`24
`
`
`
`and 3(c) below. Kitawada at ¶ 18; Figures 3(b), 3(c).
`
`(69)
`
`I see no discernable difference between the second conductive film
`
`provided on the second insulating film and in the openings thereof of Kitawada and
`
`the “second conductive film provided on said second interlayer insulating film and
`
`in said openings” recited in claim elements 1.6, 6.6, and 11.6.
`
`(70) Claim elements 1.7, 6.7, and 11.7 state “a second substrate opposed
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`to said first substrate.” Kitawada discloses a second substrate opposed to said first
`
`substrate, namely, “[o]pposing substrate 302 is fastened to device substrate 301
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`….” Kitawada at ¶ 15; Figure 3(c).
`
`(71)
`
`I see no discernable difference between the second substrate opposed
`
`to the first substrate of Kitawada and the “second substrate opposed to said first
`
`substrate” recited in claim elements 1.7, 6.7, and 11.7.
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`25
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`
`
`(72) Claim elements 1.8, 6.8, and 11.8 state “a third conductive film
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`provided on said second substrate.” Kitawada discloses a third conductive film
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`provided on said second subs