[19]
`United States Patent
`5,960,191
`[11] Patent Number:
`Sample et al. Sep. 28, 1999 [45] Date of Patent:
`
`
`
`
`
`US005960191A
`
`[54]
`
`[75]
`
`EMULATION SYSTEM WITH TIME-
`MULTIPLEXED INTERCONNECT
`
`4,578,761
`4,583,169
`
`3/1986 Gray ........................................ 364/481
`4/1986 Cooledge ................................ 364/300
`
`Inventors: Stephen P. Sample, Saratoga; Mikhail
`Bershteyn, Campbell, both of Calif;
`Michael R. Butts, Portland, Oreg.;
`Jerry R. Bauer, Cupertino, Calif.
`
`Assignee: Quickturn Design Systems, Inc., San
`Jose, Calif.
`
`Appl. No.: 08/865,741
`
`Filed:
`
`May 30, 1997
`
`Int. Cl.6 ...................................................... G06F 9/455
`US. Cl.
`................................. 395/500.49; 395/500.44
`Field of Search ............................. 364/578; 395/500,
`395/376; 326/41
`
`References Cited
`
`U.S. PATENT DOCUMENTS
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`(List continued on next page.)
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`.......... G06F 1/04
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`9/1983
`Japan ........................... H03K 19/177
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`9/1983
`Japan ........................... H03K 19/177
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`Japan .
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`5.
`
`(List continued on next page.)
`
`Primary Examiner—Kevin J. Teska
`Assistant Examiner—Samuel Broda
`
`Attorney, Agent, or Firm—Lyon & Lyon LLP
`
`[57]
`
`ABSTRACT
`
`A hardware emulation system is disclosed which reduces
`hardware cost by time-multiplexing multiple design signals
`onto physical logic chip pins and printed circuit board. The
`reconfigurable logic system of the present invention com-
`prises a plurality of reprogrammable logic devices, and a
`plurality of reprogrammable interconnect devices. The logic
`devices and interconnect devices are interconnected together
`such that multiple design signals share common I/O pins and
`circuit board traces. A logic analyzer for a hardware emu-
`lation system is also disclosed. The logic circuits necessary
`for executing logic analyzer functions is programmed into
`the programmable resources in the logic chips of the emu-
`lation system.
`
`25 Claims, 30 Drawing Sheets
`
`/12
`
`MUX CHIP
`CROSSBAR
`C
`
`G
`
`D
`
`G
`
`22
`
`C
`
`D
`
`
`
`
`
`<25
`
`K24
`
`k24
`
`
`
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`..
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`.........
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`4,577,276
`3/1986 Dunlop et a1.
`.......................... 364/491
`
`
`
`
`.
`
`12
`
`
`
`AB
`
`
`
` ECROSSB/imE
`DEMUX‘BIE‘DEMUXF)“ I MUX
`MUX
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`
`
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`34 35
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`
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`MUX ||OEMU><t
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`B
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`0
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`:
`LOGIC CHIP
`LOGIC CHIP
`LOGIC CHIP
`GLOGIC CHIP
`
`1o)
`107
`10/
`1o]
`
`SYNOPSYS 1010
`
`1
`
`SYNOPSYS 1010
`
`

`

`5,960,191
`
`Page 2
`
`US. PATENT DOCUMENTS
`_
`.
`493877625
`5/1986 Marmoa JL 9 a1~ ~~~~~~~~~~~~~~~~~~~~ 364/578
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`6/1986 Burstein et al.
`........................ 364/491
`
`476007846
`7/1986 Burrows ~~~~~
`326/39
`
`4,612,618
`9/1986 Pryor 6t al~ -
`- 364/490
`
`476137940
`9/1986 Shenton 6t al~
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`4,621,339
`~~~~~~~~~~~~~~~~~~~~~~~~~ 364/490
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`
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`
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`~~~~~~~
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`
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`
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`
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`
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`
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`........................... 365/201
`
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`365/185.11
`313:: 2:131:1{21’1............................... 7;:17/33
`
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`......................... 364/578
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`:,;g§,é139g
`4,777,606
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`4,786,904
`
`
`
`364/900
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`.. 364/716
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`............................... 364/491
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`
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`4,849,928
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`
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`.....
`29/832
`
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`
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`
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`gfligéggg
`’
`’
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`‘ """""""""""""
`’
`’
`y
`9/1991 Hyduke """""""""""""""""" 395500
`570519938
`
`~ 364578
`590537980
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`
`2
`
`SYNOPSYS 1010
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`SYNOPSYS 1010
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`

`5,960,191
`Page 3
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`article
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`from
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`SYNOPSYS 1010
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`Page 4
`
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`
`SYNOPSYS 1010
`
`5
`
`SYNOPSYS 1010
`
`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 1 0f 30
`
`5,960,191
`
`ECROSSBAR
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`
`SYNOPSYS 1010
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`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 2 0f 30
`
`5,960,191
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`
`SYNOPSYS 1010
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`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 3 0f 30
`
`5,960,191
`
`OUTPUT
`PIN
`
`DIVIDER '
`48
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`
`SYNOPSYS 1010
`
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`
`SYNOPSYS 1010
`
`

`

`US. Patent
`
`Sep. 28, 1999
`
`Sheet 4 0f 30
`
`5,960,191
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`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 5 0f 30
`
`5,960,191
`
`EXTERNAL
`SIGNAL
`
`LOGIC CHIP
`
`
`
`10
`
`SYNOPSYS 1010
`
`10
`
`SYNOPSYS 1010
`
`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 6 0f 30
`
`5,960,191
`
`QGNAL
`
`134
`
` EXTERNAL
`
`MUX CHIP
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`MUXCLK
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`
`11
`
`SYNOPSYS 1010
`
`11
`
`SYNOPSYS 1010
`
`

`

`US. Patent
`
`Sep. 28, 1999
`
`Sheet 7 0f 30
`
`5,960,191
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`

`

`US. Patent
`
`Sep. 28, 1999
`
`Sheet 8 0f 30
`
`5,960,191
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`

`

`US. Patent
`
`Sep. 28, 1999
`
`Sheet 9 0f 30
`
`5,960,191
`
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`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 10 0f 30
`
`5,960,191
`
`BACKPLANE
`1804 PINS
`
`TURBO
`1868 PINS
`
`EVENT BUS
`
`CLOCK IN
`
`15
`
`SYNOPSYS 1010
`
`15
`
`SYNOPSYS 1010
`
`

`

`US. Patent
`
`Sep. 28, 1999
`
`Sheet 11 0f 30
`
`5,960,191
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`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 12 0f 30
`
`5,960,191
`
`
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`F/G.
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`/4.
`
`REPEATER
`
`EXTERNAL
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`
`540
`
`17
`
`SYNOPSYS 1010
`
`17
`
`SYNOPSYS 1010
`
`

`

`US. Patent
`
`Sep. 28, 1999
`
`Sheet 13 0f 30
`
`5,960,191
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`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 14 0f 30
`
`5,960,191
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`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 15 0130
`
`5,960,191
`
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`

`US. Patent
`
`Sep. 28, 1999
`
`Sheet 16 0f 30
`
`5,960,191
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`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 17 0f 30
`
`5,960,191
`
`LOGIC OR l/O BOARD
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`CONTROL BOARD
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`

`

`US. Patent
`
`Sep. 28, 1999
`
`Sheet 18 0f 30
`
`5,960,191
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`

`US. Patent
`
`Sep. 28, 1999
`
`Sheet 19 0f 30
`
`5,960,191
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`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 20 0f 30
`
`5,960,191
`
`H6. 200.
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`
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`
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`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 21 0f 30
`
`5,960,191
`
`A
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`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 22 0f 30
`
`5,960,191
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`
`27
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`SYNOPSYS 1010
`
`27
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`
`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 23 0f 30
`
`5,960,191
`
`HG. 22.
`
`IMPORT
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`

`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 24 0130
`
`5,960,191
`
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`SYNOPSYS 1010
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`

`US. Patent
`
`Sep.28, 1999
`
`Sheet 25 0f 30
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`5,960,191
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`HG. 23.
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`SYNOPSYS 1010
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`

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`US. Patent
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`Sep.28, 1999
`
`Sheet 26 0f 30
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`5,960,191
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`MS
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`31
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`US. Patent
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`Sep.28, 1999
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`Sheet 27 0f 30
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`SYNOPSYS 1010
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`US. Patent
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`Sep.28, 1999
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`Sheet 28 0f 30
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` PARTIAL 4:1 TDM GROUP (00/01 ONLY)
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`SYNOPSYS 1010
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`US. Patent
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`Sep.28, 1999
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`Sheet 29 0f 30
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`r1300
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`US. Patent
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`Sep. 28, 1999
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`Sheet 30 0f 30
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`5,960,191
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`5,960,191
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`1
`EMULATION SYSTEM WITH TIME-
`MULTIPLEXED INTERCONNECT
`
`1. FIELD OF THE INVENTION
`
`The present invention relates in general to apparatus for
`verifying electronic circuit designs and more specifically to
`hardware emulation systems in which multiple design sig-
`nals are carried on a single physical wire between program-
`mable logic chips.
`2. BACKGROUND OF THE INVENTION
`
`Hardware emulation systems are devices designed for
`verifying electronic circuit designs prior to fabrication as
`chips or printed circuit boards. These systems are typically
`built from programmable logic chips (logic chips) and
`programmable interconnect chips (interconnect chips). The
`term “chip” as used herein refers to integrated circuits.
`Examples of logic chips include reprogrammable logic
`circuits such as field-programmable gate arrays (“FPGAs”),
`which include both off-the-shelf products and custom prod-
`ucts. Examples of interconnect chips include reprogram-
`mable FPGAs, multiplexer chips, crosspoint switch chips,
`and the like. Interconnect chips can be either off-the-shelf
`products or custom designed.
`Prior art emulation systems have generally been designed
`so that each signal in an electronic circuit design to be
`emulated is mapped to one or more physical metal lines
`(“wires”) within a logic chip. Signals which must go
`between logic chips are mapped to one or more physical pins
`on a logic chip and one or more physical traces on printed
`circuit boards which contain the logic and interconnect
`chips.
`The one-to-one mapping of design signals to physical pi