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`‘ or designing systems-on-a-chip, your team undoubtedly uses the latest tools for high-level
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`Hardware description languages (HDLs) enable you to evaluate designs at behavioral
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`manufacturable gate-level design descriptions. Using these tools, your team’s design
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`Yet managing the complexity of chip and system verification with gate-level simulations
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`Logic emulation is the proven technology to manage the complexity of chip designs and.
`system verification. lt enables designers to exercise chips in a real operating environment
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`Today, you cantconquer high-level verification problems with a new emulation solution.aQ;
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`Quickturn’s emulation technology creates a highly observable and reprogrammable “virtual
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`Directly reads Verilog or VHDL designs in RTL or mixed RTL and
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`Together, the HDL_and Quest. emulation software components provide a unique approach to efficiently
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`Flexible memory emulation
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`
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`Reliable, in-circuit connections
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`Pinpoint system level problems months earlier
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`The HDL—'ICE’s integrated PowerDebug environment helps you quickly and easily locate errors, probe circuit intemals, and
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`Tight integration between the HDL Hierarchy Browser, source code windows, and waveform windows give you the
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`windows showing HDL structure and contents into forms in the Quest emulation software.
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`Accelerate vector debugging tests
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`To verify your emulation implementation, Vector Debug mode lets you run a virtually unlimited number of vectors at
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`Interactive Readbackm capability streamlines debugging by letting you take snap—shots of internal register state and sig-
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`cycle—by—cycle data, unrestricted by the number of available channels in the logic analyzer, and without affecting the usable
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`emulation gate "capacity, available I/O resources, system configuration, or timing.
`
`Verify correct emulation mapping
`
`For regression testing, the System Realizer also provides a Functional Test mode, which runs up to 128K ofvectors at
`
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`
`Zoom into design problems fast
`
`Once the emulated design is plugged into a target system environment, Quicl<turn’s embedded logic analyzer
`lets you zoom into design problems and quickly pinpoint necessary changes. The 1152 channel, 128k deep Logic
`Analyzer has state machine based trigger and acquire capability (up to 8 states) and 8 event trigger support.
`
`6
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`_ SYNOPSYS 1008
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`7
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`SYNOPSYS 1008
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`

`
`Features and Specifications
`
`Model
`
`Architecture
`
`HDL—ICE ASIC Emulation System
`
`Hierarchical multiplexing architecture
`
`Custom interconnect chip
`Xilinx 40 I 3 FPGA
`
`Capacity
`
`250,000 emulation gates*
`
`Memory Support
`
`Memory compiler for RAM
`
`(single or multi-port) and ROM
`
`Emulation Speed
`IIO connections
`
`4-8 MHZ typicaI**
`
`Up to 600 total I/O signals
`
`Software
`
`Design entry
`
`Target System
`484 for PGA
`
`330 for QFP
`
`Existing components
`
`Mixed RTL and gate—|eveI
`
`design import
`
`Maps RTL into emulation primitives
`
`HDL debugger
`Quest Emulation Software:
`
`Single-pass automatic compilation
`
`Correct-by—construction timing
`
`Incremental compilation
`
`Verilog, VHDL*** , EDIF, TDL,
`NDL formats
`
`Over 55 ASIC libraries available
`
`Debug
`
`Integrated logic analyzer.
`
`I I52 probes.
`
`l28K depth memory, I6 MHz operation,
`
`8 events, complex trigger and acquire,
`Interactive readback
`
`Bench top (8.5’' H x 4.5" D x 27.7" \/V)
`500 watts
`
`65 lbs
`
`_90 l- 220 VAC
`
`Form factor
`
`Power
`
`Weight
`Line in
`
`World Headquarters
`and Western Sales
`
`Quicktum Design Systems. Inc.
`440 Clyde Avenue
`Mountain View, CA 94043
`Phone 4|5-967-3300
`‘
`
`Eastern Sales
`
`Quiclctum Design Systems. Inc.
`Suite 340
`33 Boston Post Road
`
`Mariborough, MA 0I752
`Phone 508-480-0660
`
`Central Sales
`
`Quiclctum Design Systems, Inc.
`Suite 600
`I0l East Park Boulevard
`
`Plano, TX 75074
`Phone 2I4-5 I 6-3838
`
`European Headquarters
`Quiclctum Design Systems - GmbH
`Kronstadter Strasse 9
`
`8 I 677 Munich, Germany
`Phone 49 (89) 939-44I 0
`
`Japan
`Quicktum Design Systems, Inc.
`Madre Matsuda Bldg. 4F
`4-I3 Kioi-cho
`
`Chiyoda-ku. Tokyo I 02 Japan
`Phone 8 I '(3) 3237 68 I 0
`
`Quicktum, The Quicktum Logo, Quicktum Design
`Systems. Quest, PowerDebug, and HDL-ICE are trade- ' ‘
`marks of Quicktum Design Systems, Inc. All other trade-
`marks or registered trademarks are the property of their
`respective holdeis.
`
`* Actual emulation capacity is design style and memory dependent. For
`example. designs with low pin-to-net ratios and many small memories may
`achieve 250K gateslmodule. Typical design styles will achieve |50K
`
`gates/‘module or 500k transistors.
`
`"°"Actual performance is design dependent.
`
`*"°"AvaiIable first half of I995.
`
`p%nn QUICKTURN
`
`
`
`. SYNOPSYS 1008
`
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`
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