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`

`
`Our Reference: 02282.PO55
`
`Patent
`
`METHOD AND AEPARATUS FOR GATE-LEVEL SIMULATION OF SYNTHESIZED
`REGISTER TRANSFER LEVEL DES|GNS WITH SOURCE-LEVEL DEBUGGING
`inventors: Alain Raynaud and Luc M. Burgun
`A
`.
`.
`Respectfully submitted.
`.
`-
`LAKELY SOKOLOFF TAYLOR & ZAFMAN LLP
`Wzzaii.
`/0“...
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`B
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`E’ E
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`513;
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`‘U 1 U
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`a
`
`William D. Davis
`
`Reg. No. 38,428
`
`EM542801726US
`“Express
`Mail” mailing label number:
`ui
`31 1998
`Date of Deposit:
`
`I hereby certify thai_I am causing this paper or fee to be deposited with
`the Unite
`(1 States Postal Service "Express Mail Post Office to Addressee"
`service 0
`n the date indicated above and that this paper or fee has been
`addressed to the Assistant Commissioner for Patents, Washington, D. C.
`20231
`
`‘
`
`Michelle J. Turner
`
` l iJ
`
`'
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`
`
`*i'***
`Docket Due Date:
`Date Mailed:
`ed hereon:
`llU.S.Pl-t3lTd
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`SYNOPSYS 1002
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`

`
`UNITED STATES PATENT APPLICATION
`
`FOR
`
`METHOD AND APPARATUS FOR GATE—LEVEL SIMULATION OF
`
`SYNTHESIZED REGISTER TRANSFER LEVEL DESIGNS WITH SOURCE-
`LEVEL DEBUGGING
`
`:15:
`L22
`
`
`I.«....:'.L-""(rill
`
`INVE NTORS:
`
`ALAIN RAYNAUD
`LUC M. BURGUN
`
`Prepared by:
`
`BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN, LLP
`12400 WILSHIRE BOULEVARD
`SEVENTH FLOOR
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`(503) 684-6200
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`Attorney Docket No. O2282.P055
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`EM 542801726 US
`"Express Mail" mailing label number
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`July 31, 1993
`Date of Deposit
`
`I hereby certify that I am causing this paper or fee to be deposited with the United States Postal Service
`“Express Mail Post Office to Addressee" service on the date indicated above and that this paper or fee has
`been addressed to the Assistant Commissioner for Patents, Washington, D. C: 20231
`
`Michelle 4. Tgrngr
`(Typed or printed name of person mailing paper or fee)
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`( Jgnature of
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`mailing paper or fee)
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`7
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`ME
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`D AND APP
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`T
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`F R
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`-LEVEL SIM
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`TI N OF
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`Y
`ESIZED RE I
`R TRA SFER L
`EL DE IGN WI H
`UR E-
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`LEVEL DEBLJQQINQQ
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`.12”
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`FIELD F TH
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`NTTON
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`10
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`15
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`20
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`This invention relates to the fields of simulation and prototyping
`
`when designing integrated circuits.
`
`In particular, this invention is drawn to
`
`debugging synthesizable code at the register transfer level during gate-level
`simulation.
`
`BAQEGRQUND QF TI-IE !NyENTI§ 2N
`
`Integrated circuit designers have adopted the use of high—level
`
`hardware description languages due in part to the size and complexity of
`
`modern integrated circuits. One such description language is Very High
`
`Speed Integrated Circuit (VHSIC) Description Language, or VHDL. Further
`
`information regarding VHDL may be found in the IEEE Standard VHDL
`
`Language Reference Manual (IEEE 1076-1987, IEEE 1076-1993). Another such
`
`description language is Verilog. These high level description languages are
`
`typically generically referred to as hardware description languages (I-lDLs).
`
`Synthesis is the process of generating a gate—level netlist from the
`
`high—leVel description languages. Presently, synthesis tools recognize a subset
`
`of the high-level description language source code referred to as Register
`
`1
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`Transfer Level (RTL) source code. Further information regarding RTL source
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`code may be found in the IEEE 1076.6 /D1.10 Draft Standard for VHDL Register
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`Transfer Level Synthesis (1997).
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`The RTL source code can be synthesized into a gate-level netlist. The
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`gate-level netlist can be verified using gate-level simulation, The gate-level
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`simulation can be performed using a software gate-level simulator.
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`Alternatively, the gate-level simulation may be performed by converting the
`gate-level netlist into a format suitable for programming an emulator, a
`hardware accelerator, or a rapid-prototyping system so that the digital circuit
`/description can take an actual operating hardware form.
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`Debugging environments for high—level hardware description _
`languages frequently include a number of functionalities for analyzing and
`verifying the design when performing simulation. For example, a designer
`can typically navigate the design hierarchy, View the RTL source code, and set
`breakpoints on a statement of RTL source code to stop the simulation.
`Statements are usually identified by their line number in the RTL source
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`code. In addition, the debugging environment often supports viewing and
`tracing variables and signal values. The RTL simulation environment
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`typically offers such RTL debugging functionalities.
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`RTL simulation is typically performed by using software RTL
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`simulators which provide good flexibility. However, for complex designs, a
`very large number of test vectors may need to be applied in order to
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`adequately verify the design. This can take a considerable amount of time
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`using software RTL simulation as contrasted with hardware acceleration or
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`emulation starting from a gate-level netlist representation (i.e., ”gate—level
`hardware acceleration,” or "gate—1evel emulation”). Furthermore, it may be
`useful to perform in-situ Verification, which consists of validating the design
`under test by connecting the emulator or hardware accelerator to the target
`system environment (where the design is to be inserted after the design is
`completed)-
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`One disadvantage with gate—level simulation, however, is that most of
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`the high-level information from the RTL source code is lost. Without the
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`high-level information, many of the debugging functionalities are
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`unavailable.
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`For example, the designer typically cannot set a breakpoint from ‘the
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`source code during gate-level simulation. Although signals can be analyzed
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`during gate-level simulation, mapping signal values to particular source code
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`lines can be difficult, if not impossible.
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`If the source code is translated into a
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`combinatorial logic netlist, for example, the designer cannot ”step” through
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`' the source code to trace variable values. Instead, the designer is limited to
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`analyzing the input Vector and resulting output vector values. Although the
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`signals at the inputs and outputs of the various gates may be traced or
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`modified, these values are determined concurrently in a combinatorial
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`network and thus such analysis is not readily mappable to the RTL source
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`code.
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`A typical design flow will include creating a design at the RTL level,
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`then synthesizing it into a gate-level netlist, Although simulation of this
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`netlist can be performed at greater speeds using emulators or hardware
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`accelerators, the ability to debug the design at the gate level is severely limited
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`in comparison with software RTL simulation.
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`SQ flMARY QF THE INVENTIQN
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`Methods of instrurnenting synthesizable register transfer level (RTL)
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`source code to enable debugging support akin to high-level language
`programming environments for gate-level simulation are provided.
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`One method of facilitating gate-level simulation includes the step of
`generating cross-reference instrumentation data including instrumentation
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`logic indicative of the execution status of at least one synthesizable statement
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`within the RTL source code. A gate-level netlist is synthesized from the RTL
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`source code. Evaluation of the instrumentation logic during simulation of
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`the gate-level netlist enables RTL debugging by indicating the execution status
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`of the cross~referenced synthesizable statement in the RTL source code.
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`In one embodiment, the gate—leVel netlist is modified to provide
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`instrumentation signals implementing the instrumentation logic and
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`corresponding to synthesizable statements within the RTL source code.
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`In
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`various embodiments, this may be accomplished by modifying the RTL
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`source code or by generating the modified gate-level netlist during synthesis
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`as if the source code had been modified.
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`Alternatively, the gate-level netlist is not modified but the
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`instrumentation signals implementing the instrumentation logic are
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`contained in a cross-reference instrumentation database.
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`In either case, the instrumentation signals indicate the execution status of the
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`corresponding cross-referenced synthesizable statement. The
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`instrumentation signals can be used to facilitate source code analysis,
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`breakpoint debugging, and visual tracing of the source code execution path
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`during gate-level simulation.
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`For example, a breakpoint can be set at a selected statement of the
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`source code. A simulation breakpoint is set so that the simulation is halted at
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`a simulation cycle where the value of the instrumentation signals indicate
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`that the statement has become active .
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`With respect to visually tracing the source code during execution, the
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`instrumentation logic is evaluated during gate-level simulation to determine
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`a list of at least one active statement. The active statement is displayed as a
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`highlighted statement.
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`With respect to source code analysis, cross-reference instrumentation
`data including the instrumentation signals can be used to count the number
`of times a corresponding statement is executed in the source code. For
`example, an execution count of the cross-referenced synthesizable statement
`is incremented when evaluation of the corresponding instrumentation logic
`indicates that the cross-referenced synthesizable statement is active.
`Other features and advantages of the present invention will be
`apparent from the accompanying drawings and from the detailed description
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`that follows below.
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`The present invention is illustrated by way of example and not
`limitation in the figures of the accompanying drawings, in which like
`references indicate similar elements and in which:
`Figure 1 illustrates the process of synthesizing RTL source code into a1
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`gate-level design.
`Figure 2 illustrates one embodiment of a modified process for
`generating a gate-level design.
`Figure 3 illustrates one embodiment of a method for instrumenting
`level-sensitive RTL source code.
`Figure 4 illustrates VHDL source code.
`Figure 5 illustrates the gate-level design synthesized from the RTL
`source code of Figure 4.
`Figure 6 illustrates the VHDL source code of Figure 4 modified in
`accordance with the method of Figure 3.
`Figure 7 illustrates one embodiment of the gate-level logic synthesized
`from the modified RTL source code.
`Figure 8 illustrates sample Verilog source code before instrumentation.
`Figure 9 illustrates the Verilog source of Figure 8 instrumented in
`accordance with the method of Figure
`Figure 10 illustrates the gate—1evel logic synthesized from the
`instrumented Verilog source code of Figure 9.
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`Figure 11 illustrates ¥er-i-legsource code for a D flip-flop with
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`asynchronous reset.
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`Figure 12 illustrates one method of instrumenting event-sensitive RTL
`source code.
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`Figure 13 illustrates the source code of Figure 11 modified in
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`accordance with the instrumentation process of Figure 12.
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`Figure 14 illustrates the gate—level logic synthesized for the
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`instrumented source code of Figure 13.
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`Figure 15 illustrates Verilog source code for a D flip-flop with
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`asynchronous reset.
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`Figure 16 illustrates the Verilog source code of Figure 15 after
`instrumentation in accordance with the method of Figure 12.
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`Figure 17 illustrates a method of instrumenting process activation.
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`Figure 18 illustrates source code modified in accordance with the
`method of Figure 17.
`Figure 19 illustrates an instrumented ”case” statement.
`Figure 20 illustrates a process for decreasing the logic needed to
`instrument the source code,
`Figure 21 illustrates incorporating instrumentation within the
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`synthesis process.
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`Figure 22 illustrates a method of setting a breakpoint in RTL source
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`code for use during gate-level simulation.
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`DETAILED QESQRIPTIQN
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`Figure 1 illustrates a typical RTL source code synthesis process. HDL
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`code including synthesizable RTL source code (110) serves as input to a
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`synthesis process 120. In one embodiment, the RTL source code 110 is
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`synthesized in step 140 to produce a gate-level design 150. The gate-level
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`design can be used for gate—level simulation as illustrated in step 160.
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`Typically the gate-level design comprises a hierarchical or flattened
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`gate-level netlist representing the circuit to be simulated. The various signals
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`in a design are referred to as nets. A hierarchical netlist is made of a list of
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`blocks, whereas a flattened netlist comprises only one block. A block contains
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`components and a description of their interconnection using nets.
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`Components can be reduced to combinatorial or sequential logic gates, or they
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`may be hierarchical blocks of lower level.
`For example, the component may be a primitive gate denoting a single
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`combinatorial logic function (e.g., AND, NAND, NOR, OR, XOR, NXOR, etc.)
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`or a single storage element such as a flip-flop or latch for sequential logic.
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`One example of a set of primitive gates is found in the generic library GTECH
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`available from Synopsys, Inc. of Mountain View, California.
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`Alternatively the component may be an application specific integrated
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`circuit (ASIC) library cell which can be represented by a set of primitive gates.
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`One example of an ASIC library is the LCASOOK ASIC library developed by LSI
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`Logic, Inc., Milpitas, California.
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`A component may also be a programmable primitive that represents a
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`set of logic functions and storage. One example of a programmable primitive
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`is the configurable logic block (CLB) as described in The Programmable Gate
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`Array Handbook, Xilinx Inc., San Iose, 1993.
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`Another example of a component is a macro block denoting a complex
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`logic function such as memories, counters, shifters, adders, multipliers, etc.
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`Each of these can be further reduced to primitive gates forming combinatorial
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`or sequential logic.
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`Three major categories of tools are available to the designer to simulate
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`and test the design. Software RTL simulators (such as ModelSimTM from
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`Model Technology, Inc.) typically offer a high-level of abstraction for their
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`debugging environment, but have limited performance in terms of speed and
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`no in—situ capacity. Software gate—leve1 simulators (such as Quicl<SirnTM from
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`Mentor Graphics Corporation) typically offer limited level of abstraction and
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`speed as well as no in—situ capacity. Hardware gate—level simulators (such as
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`Cobalt” and System Realizer‘-‘M from Quickturn Inc., Avatar” from Ikos,
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`and fast-prototyping systems usually built from FPGAs) typically offer very
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`good performance i.n terms of speed and in—situ capacity, but a limited
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`debugging environment.
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`When testing the design described by the HDL source code a designer
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`may choose to simulate and validate the design at the RTL source code level
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`(i.e., RTL simulation). RTL simulation typically permits the designer to set
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`breakpoints in the source code, navigate the design hierarchy, View variables
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`and signals and trace the value of these variables and signals.
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`When testing complex designs, millions or billions of test vectors may
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`need to be applied in order to adequately test the design. Hardware
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`accelerators or emulators can be used with the gate-level design to test the
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`design at a much greater speed than what is typically possible through
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`software simulation (i.e. either software RTL simulation or software
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`gate-level simulation). Unfortunately, the gate-level design generated in step
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`150 typically includes none of the high-level information available in the
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`RTL source code 110. As a result, features available during RTL simulation
`such as setting breakpoints or analyzing the source code coverage are not
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`available during gate-level simulation.
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`Instrumentation is the process of preserving high—1evel information
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`through the synthesis process.
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`Instrumentation permits simulation of a gate-
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`level netlist at the level of abstraction of RTL simulation by preserving some
`of the information available at the source code level through the synthesis
`process.
`Figure 2 illustrates one embodiment of the instrumentation process in
`which instrumentation is integrated with the synthesis process. RTL source
`code 210 is provided to the synthesis process 220. The synthesis process 120 of
`Figure 1 has been modified to include an instrumentation step 234. After
`instrumentation the instrumented code is then synthesized in step 240 as the
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`original RTL source code was in step 140 of Figure 1.
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`In one embodiment, instrumentation results in generating a modified
`gate-level design to permit reconstitution of the flow of execution of the
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`original RTL source code during gate—leve1 simulation. Generally
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`instrumentation logic is created for a synthesizable statement in the RTL
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`source code either by modifying the RTL source code or by analyzing the RTL
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`source code during the synthesis process. The instrumentation logic provides
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`an output signal indicative of whether the corresponding synthesizable
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`statement is active. A gate-level design including the instrumentation
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`output signal is then synthesized. Referring to Figure 2, the resulting
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`gate~leve1 design 250 contains additional logic to create the additional
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`instrumentation output signals referenced in instrumentation data 238.
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`In an alternative embodiment, the RTL source code is analyzed to’
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`generate a cross-reference database as instrumentation data 238 without
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`modifying the gate-level design. The cross-reference database indicates the
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`combination of already existing signals in the form of instrumentation logic
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`that can be evaluated during simulation to determine whether a particular
`line of the RTL source code is active. The cross-reference database contains a
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`cross-reference between these instrumentation logic output signals and the
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`position of the corresponding statement in the source code.
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`The
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`instrumentation data 238 is likely to contain considerably more complex logic
`to evaluate during simulation when the approach of not modifying the
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`gate-level design (i.e., ”pure" cross-reference database) is taken.
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`The two approaches have tradeoffs. The gate-level design modification
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`technique does not require special knowledge of the target simulation
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`environment. Moreover, the gate—level design modification technique
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`significantly reduces or eliminates the complexity of the logic to be evaluated
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`during simulation to the extent that emulator or accelerator hardware
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`triggering circuitry can be used to take an action when the corresponding
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`statement is executed.
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`For example, the hardware triggering circuitry may be used to halt the
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`simulation at a particular statement or to count the number of times a
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`particular statement is executed. The resulting gate-level design used during
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`simulation, however, Will not be the design actually used for production thus
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`simulation may not verify accurately the behavior of the gate-level design
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`used for production. Furthermore, simulation of modified gate-level design
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`may require more physical resources in hardware than the original design
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`alone if gates have been added in order to implement the instrumentation
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`logic.
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`Alternatively, the pure cross—reference database technique typically
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`results in greater complexity of instrumentation logic to evaluate during
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`simulation, but does not otherwise affect the original gate-level design. The
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`greater complexity, however, may prevent the use of the hardware triggering
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`circuitry to halt the simulation or to track source code coverage. Thus the
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`pure cross-reference database technique may result in a significantly slower
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`simulation time. Furthermore, since the evaluation may be performed by
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`software, direct verification of the gate—level design in the target system
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`through in—situ verification may not be possible. The instrumentation data
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`including the logic added for instrumentation purposes can be eliminated
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`after testing, however, without disrupting the gate-level design.
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`In essence the gate-level design modification technique greatly
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`simplifies the analysis and the instrumentation logic required for
`cross—referencing by modifying the gate-level design to create unique signals
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`and therefore simpler logic to evaluate (