The availability of programmable logic devices based on static memory cells allows the implementation
`
`of ‘soft" hardware - that is. logic devices whose functions can be changed while they remain resident in
`
`system. A growing number of SRAM-based Field Programmable Gate Array (FPGA) users are taking
`
`advantage of this capability. In general, these applications of reconfigurable logic fall into three
`
`categories: System with built-in diagnostic or test logic. “adaptable” system designs, and systems with
`
`“multi-purpose" hardware
`
`Published in:
`
`ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
`
`Date of Conference: 19—23 Sep 1994
`
`Page(s):
`227 - 230
`
`Meetlng Date:
`19 Sep 1994-23 Sep 1994
`
`Print ISBN:
`0-7803-2020—4
`
`INSPEC Acceeslon Number:
`4998160
`
`Conference Location :
`Rochester. NY
`
`Dlgltal Object Identlfler:
`10.1109/ASIC.1994.404570
`
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`TAKING ADVANTAGE OF RECONFIGURABLE LOGIC
`Bradly K. Fawcett
`
`Xilinx Inc.
`2100 Logic Drive
`San Jose. CA, USA 95124
`
`-
`The availability of programmable
`Abstract
`logic devices based on static memory cells allows
`- that
`implementation of "soft" hardware
`the
`is,
`logic devices whose
`functions can be changed
`target system.
`while they remain resident
`in
`the
`growing
`number
`of
`SRAM-based Field
`A
`Programmable Gate Array (FPGA) users are taking
`advantage of
`this capability.
`In general,
`these
`applications of
`reconfigurable
`logic
`fall
`into
`three
`categories:
`systems with
`built-in
`diagnostic
`or
`test
`logic, "adaptable"
`system
`designs , and
`'I m u I t i -purpose I'
`systems with
`hardware.
`
`In trod uction
`
`Combining the density and flexibility of gate arrays
`with the ease-of-use and convenience of a user-
`programmable device, Field Programmable Gate Arrays
`(FF'GAs) have proven to be a cost-effective alternative to
`standard SSI/MSI devices or custom VLSI components in
`thousands of system designs. However, the capabilities of
`static-memory-based FPGAs extend well beyond the direct
`replacement of other types of logic devices. In SRAM-
`based FPGAs, the state of internal static memory cells
`determines the logic functions and interconnections within
`the FPGA device. By downloading different configuration
`programs into the memory cells, the device's functions can
`be changed at will while the FPGA is resident in the target
`system. These devices can be programmed and
`reprogrammed an unlimited number of times. Thus,
`systems with FPGAs can contain "soft hardware" - that is,
`hardware whose functions can be changed easily during
`normal system operation. Innovative designers are taking
`advantage of this unique "in-system reconfigurability" in a
`wide variety of applications. In general, these applications
`of reconfigurable logic fall into three categories: systems
`with built-in diagnostic or test logic, "adaptable" system
`designs, and systems with "multi-purpose" hardware.
`
`The Mechanics of Reconfirrurability
`
`these FPGAs, logic functions and interconnections are
`determined by configuration program data stored in internal
`static memory cells. In Xilinx devices, for example, a
`single-ended five transistor memory cell is used to
`minimize memory area. Rather than the traditional array
`structure, the memory cells are distributed throughout the
`device; each cell is placed as close as possible to the logic
`it controls, resulting in maximum layout efficiency. The
`benefits of an SRAM-based FPGA include high density,
`high performance, testability, manufacturability, and the
`flexibility inherent to a device that can be programmed
`while resident in the system.
`Since the devices are static memory-based, a
`configuration program must be loaded into each FPGA
`when the system is powered-up. Thus, the configuration
`program (or programs) must reside in the system extemal to
`the FPGAs (for example, in EPROMs or on a disk).
`Xilinx FPGA devices feature several available loading
`modes to accommodate various system requirements.
`Automatic modes use on-chip control logic to load the
`FPGA directly from an extemal memory device (typically
`an EPROM). With the peripheral loading modes,
`configuration programs are written to the FPGA under the
`control of an extemal processor or DMA device, just like
`any other peripheral device. Both 8-bit parallel and serial
`loading formats are available for both modes.
`Just as these devices are initially configured during
`system initialization, they can be re-configured at any time
`during system operation. For example, a reconfiguration of
`a Xilinx FPGA is triggered by a high-to-low transition on
`the dedicated PROGRAM input. All configuration
`memorycells are cleared and a complete configuration
`program is loaded each time the device is configured.
`Configuration loading time usually is not a performance
`issue, since it has no impact once the configuration
`memory has been programmed. Nonetheless, configura-
`
`Table 1: Configuration program size and time for selected FPGAs
`(serial peripheral mode, maximum configuration clock rate)
`__________......____-----.~-------...----------...------.-...--------.----------
`Program Size
`Configuration
`Configuration
`Time
`Clock Speed
`(Data Bits)
`
`Device
`
`FPGAs based on static memory (SRAM) technology are
`available from several manufacturers, including Xilinx,
`AT&T Microelectronics, Altera, Atmel, and Motorola. The
`architectural
`implementation varies among
`the
`manufacturers, but the basic concepts are the same. In
`
`XC3020
`XC3042
`XC3090
`XC4002A
`XC4006
`XC4013
`
`14.819
`30.824
`64.200
`37,784
`119,832
`247,960
`
`10 MHz
`10 MHz
`10 MHz
`8 MHz
`8 MHz
`8 MHz
`
`2 ms
`4 ms
`8 ms
`6 ms
`17 ms
`34 ms
`
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`tion times are short - typically just a few milliseconds.
`Table 1 shows configuration program sizes and times for a
`sampling of Xilinx FPGA devices. There is no limit to the
`number of times an SRAM-based FPGA can be
`programmed.
`The design-related benefits of SRAM-based
`programmable logic are somewhat obvious. The ability to
`reconfigure FPGAs resident
`in the target system
`significantly eases the debugging process, reducing overall
`development time and cost, and shortening the product's
`time-to-market. Temporary modifications to the logic,
`such as routing an internal node to an unused I/O pad, can
`be implemented for debugging purposes and then removed
`from the production design. Typically. small design
`changes can be implemented in a few minutes time, with
`the designer receiving almost immediate feedback on the
`effects of the design modifications.
`In essence, SRAM-
`based FPGAs provide a flexible means of 'breadboarding'
`logic designs, as well as a cost-effective means of
`implementing logic in the final product.
`However, the benefits of the reconfigurable nature of
`SRAM-based FPGAs can extend beyond the debugging
`stage and influence the nature of the final product itself.
`Systems can include multiple configuration programs for
`their FPGAs, allowing varying operations to be performed
`efficiently with a minimal amount of hardware.
`Reconfigurable logic has been used to implement system
`diagnostics, to create systems that are adaptable for different
`environments or operations, and to implement 'multi-
`purpose' hardware in a system. The result is smaller, more
`powerful. less expensive, and more reliable system designs.
`
`Rgonfi ggring for System Diagnostics
`
`Built-in diagnostic and test logic assists the designer
`during initial system debug, increases the confidence level
`of the system's users, and aids in field maintenance
`operations. However, using traditional logic technologies,
`the additional
`logic needed to implement diagnostic
`operations can significantly increase the system's size,
`complexity, and cost.
`the
`Reprogrammable SRAM-based FPGAs offer
`designer an economical means to implement test logic
`without adding to the hardware content of the system. The
`same FPGAs that implement the system's logic can be
`reconfigured while in the system to hold diagnostic logic to
`test that system. When the system is powered-up or placed
`in a test mode, its FPGAs are configured with logic
`functions dedicated to testing other circuitry in the system.
`For example, a configuration dedicated to implementing a
`boundary scan test of the board assembly could be loaded
`into the system's FPGAs [1].
`(Boundary scan test logic is
`built into the XC4000 family of FPGAs, but would need to
`be implemented as a separate configuration of an XC2000
`or XC3000 family device.) Once the testing is successfully
`completed, other configuration programs are loaded into the
`FPGAs to implement the actual logic of the particular end
`application intended for that system. The diagnostic test
`
`logic is essentially 'cost-free‘, except for the additional
`memory space required for the extra FPGA configuration
`programs. This strategy has been employed to include
`diagnostic logic in applications such as computer
`peripherals, telecommunication multiplexers, industrial
`controllers, medical equipment, and integrated circuit device
`testers [2 - 5].
`
`A
`
`m
`
`in
`
`Another common use of reconfigurable logic is the
`implementation of a single hardware design that can be
`adapted for varying tasks or environments.
`In such
`systems, any of a number of potential configuration
`programs can be downloaded into the system's FPGAs to
`alter the logic for particular applications or operations as
`needed. Hence, more functionality is implemented with
`fewer components, hardware design costs can be amortized
`over a greater number of systems, and design cycle times
`are greatly reduced.
`TDX Peripherals Inc. (Hauppauge, NY) took advantage
`of 'adaptable hardware“ in the design of a PC-compatible
`controller card in the TDX SO/GCR 9-track, 1/2-inch tape
`drive. Four different data densities commonly are used for
`9-track tapes, ranging from 800 to 6250 bits per inch (bpi).
`Each density level has a different data encoding scheme,
`with the complexity of the encoding algorithm increasing
`with higher density.
`TDX's former systems required a
`different controller card design for each. By employing
`seven FPGA devices, including four XC3000 series and
`three XC2000 series parts, a single PC card capable of
`handling several different densities and formats was
`developed. Customers can select the desired format from a
`menu on the PC's terminal:
`this selection triggers the
`downloading of the appropriate configuration programs and
`software device driver. All seven FPGAs are downloaded in
`parallel from the PC's disk under control of the processor,
`and constitute over 70% of the logic in the system.
`Initial
`shipments of the system supported the 1600 and 6250 bpi
`formats. The lesser-used 3200 and 800 bpi formats were
`added later through the development of new FPGA
`configuration programs, and previous customers' systems
`were updated via floppy disk.
`Such 'adaptable system' design has been particularly
`popular
`among
`test
`equipment manufacturers;
`reconfigurable FPGAs can be used to adapt the same
`hardware to perform varying types of tests. Dainippon
`Screen Manufacturing Co. (Kyoto, Japan) used SRAM—
`based FPGAs in a system that automates optical
`inspections of the metal pattern on printed circuit boards
`(Figure 1) [6]. Four XC2018 FPGAs are used, with each
`controlling the testing of one of four design rule checks:
`line width, clearance width, spurious copper size, and
`pinhole size. Image data from a CCD camera is loaded into
`the XC2018 devices, converted to a matrix format, and
`processed for defect correction. Defective block data is
`passed to the system's processor through a FIFO buffer.
`There are eleven levels of criteria for line and clearance
`
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`width, and five levels of criteria for pinhole and spurious
`copper size. For any given inspection run, the operator
`chooses the appropriate inspection criteria based on the
`customer's requirements;
`the system's processor then
`downloads the appropriate FPGA configuration programs
`corresponding to the operator's selections.
`Taking the concept of adaptable hardware to the extreme,
`several vendors, including Quickturn Design Systems,
`Zycad, and Aptix, offer ASIC emulation systems based on
`Xilinx FPGAs. In these systems, multiple FPGAs can be
`used to emulate logic designs comprising tens of thousands
`of gates. These systems allow designers to test, debug, and
`verify ASIC designs rapidly. Such an emulation system
`was used during the design of the Intel Pentium
`microprocessor, trimming months from the development
`cycle.
`
`Multi-Purpose Hardware
`
`Some innovative designers have built systems where
`reconfiguration of the programmable logic is a normal part
`of the system's operation. This implies that the system has
`some "mutually-time-exclusive'' functions that can be
`swapped into and out of the FPGAs as needed. For
`example, at any given time, a tape recorder can read or
`write, but never both simultaneously. Consequently, an
`FPGA within a digital tape recorder could be configured to
`perform one set of functions when writing data (such as data
`encoding and e m r code generation), and then reprogrammed
`to perform another set of functions when reading data (such
`as data decoding and error detection and correction) [7].
`These types of "multi-purpose" hardware applications of
`SRAM-based FPGAs are especially cost-effective; at least
`
`twice the hardware would be required to implement the same
`functionality with traditional logic devices.
`For example, reconfigurable SRAM-based FPGAs were
`key to the design of a pivoting monitor from Radius Inc.
`(San Jose, CA), that can be used in either portrait or
`landscape orientation [8]. The monitor actually has six
`potential operating modes: 1, 2, and 4 bitdpixel for the
`various shades of gray in portrait mode, and 1, 2, and 4
`bits/pixel in landscape mode. The interface control
`circuitry, including pixel address translation, for any one
`mode fits in a single XC2018 FPGA. Thus, six
`potential configuration programs are available for the
`FPGA. A position sensitive switch senses when the
`monitor is rotated and generates an interrupt to the system
`software, which in turns triggers the automatic downloading
`of the appropriate FPGA configuration data. Similar
`schemes have been employed in applications ranging from
`missile guidance systems to printer controllers to
`microprocessor-based board testers [5,9,10].
`The long-term implications of "soft hardware" are
`staggering; reconfigurable FPGA technology already is
`shaping the future of computing. Several research
`laboratories have used Xilinx FPGAs to implement multi-
`purpose, high-speed coprocessors for accelerating operations
`in computer systems. These "reconfigurable computing
`engines" can provide performance exceeding supercomputers
`in some applications. For example, the SPLASH system,
`a linear logic array based on Xilinx FPGAs and designed by
`the Supercomputing Research Center, operates as a co-
`processor in a Sun workstation (Figure 2) [11,12].
`SPLASH'S first application was to implement a systolic
`algorithm for one-dimensional pattern matching during
`DNA rescarch, whcrc it outperformed a Cray-2 by a factor
`of 325 and ;I custom-built nMOS devicc by a factor of 45.
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`Figure. 2: The SPLASH coprocessor board featurcs a linear array of FPGA and SRAM devices
`Through FPGA configuration, the SPLASH coprocessor
`during system operation. New system architectures that
`has also been used for other applications, such as text
`take advantage of reconfigurable logic will continue to
`emerge as FPGA performance and density levels continue to
`searches and image processing. FPGAs have been used to
`build similar "reconfigurable engines" with equally
`increase.
`impressive results at IBMs Almaden Research Center [13]
`and Digital Equipment's Paris Research Labs [ 141, among
`others. By providing the capability to dynamically alter a
`computer's hardware resources to address specific
`computational needs, reconfigurable FPGAs may someday
`bring the performance of supercomputers to desktop
`systems for specific applications.
`S ti mmary
`
`References
`
`.
`.
`1. New, B., "Boundary-Scan Emulator for XC3000". XAPP ADD^ cauons
`Handbook. Xilinx PN 0400810-01. OCI. 1992
`2. Fawcett, B.. "Taking Advantage of Reconfigurable Logic". Hgh
`Perform ance SvstemsP
`1989
`3. Smih, D., "User-Programmable Chips Take on a Broader Range of
`Applications". VLSI Svstems Desien. July 1988
`4. Reynolds, J., "Building Tomorrow's Disk Controller Today". Electron&
`Products. Dec. 15. 1987
`5. Hillen, K. and Fawcett. B., "Build Reconfigurable Peripheral
`Mar. 8, 1990
`Controllers". Electronic Desiet
`6. Kanai, T.. "FPGAs Aid PCB Inspection", ASIC & EDA, Jan. 1992
`7. Liehe. T.. "Two, Two, Two Chips in One", Electronic Eneineering
`b. Nov. 17,1986
`8. Tan-Nguyen. J.. Oyama. T. and Moss, N., "Pivoting Monitor Increases
`Rew 'ew. Fall 1990
`Versatility of Workstations". -v
`9. Kaiser, M.. "Flexible Programmable Logic Key to Tester Design".
`Proceedings of 1994 PLD Desim Conference. April, 1994
`10. Tallyn, K., "Reprogrammable Missile", M-D
`ac c
`Electronics. April. 1990
`11. Gokhale, M.. Holmes. W., Kopser, A., Lucas, S.. Minnich. R. and
`Sweely. D.. "Building and Using a Highly-Parallel Programmable Logic
`Array", Computer. Jan. 1991
`12. Amold, J.. Buell, D. and Davis, E., "Splash 2 . Proceedines of 4&
`h u a l ACM m s i u m on Parallel A-
`and Archite-
`1992
`13. Cox, C. and Blanz. W. E., "GANGLION - A Fast Hardware
`Implementation of a Connectionist Classifier", Proceedinm of the Custom
`u t e d CI 'rcuit Conf-
`1991
`14. Benin, P.. Doncin. D. and Vuillemin, J:, "Programmable Active
`Memories: a Performance Assessment". First Intemational ACWSIGD4
`Workshon on Field Proerammahle Gate Arravs. Feb. 1992
`
`Designer's are taking advantage of the reconfigurable
`nature of SRAM-based FPGAs in a wide variety of
`applications. However, these systems have a few
`characteristics in common. Each, obviously, has multiple
`FPGA configuration bitstreams available to the system in
`semiconductor or magnetic memory. Each has logic
`functions that do not need to exist simultaneously within
`the system. Each has a stimulus that tells the system when
`to change bitstreams, and enough 'intelligence' to select the
`correct bitstream at the appropriate time. The selection
`mechanism can be as simple as a switch. However, in
`most cases, a microprocessor or microcontroller controls
`the selection and downloading of FPGA bitstreams as part
`of its control operation.
`In summary, the advent of in-system programmable,
`SRAM-based FPGAs has freed the designer from the "hard"
`nature of traditional logic ICs. With these flexible devices,
`designers can build cost-effective diagnostic logic, create
`adaptable systems, and have logic dynamically reconfigured
`
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