IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`In re U.S. Patent No. 6,947,882
`
`Trial Number:
`
`Filed:
`
`Issued:
`
`Sept. 24, 1999
`
`Sept. 20, 2005
`
`Inventors: Frederic Reblewski
`Olivier Lepaps
`Jean Barbier
`
`Assignee: Mentor Graphics Corporation
`
`Title:
`
`REGIONALLY TIME MULTIPLEXED
`EMULATION SYSTEM
`
`Mail Stop Patent Board, PTAB
`United State Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 6,947,882
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 ET SEQ.
`
`OHSUSA:751803920.2
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`Inter Partes Review of U.S. Pat. 6,947,882
`
`TABLE OF CONTENTS
`
`TABLE OF CONTENTS ...........................................................................................ii
`EXHIBIT LIST ..........................................................................................................iv
`I.
`MANDATORY NOTICES ..............................................................................1
`A.
`Real Party-In-Interest ...............................................................................1
`
`B.
`
`C.
`
`Related Matters.........................................................................................1
`
`Lead And Back-Up Counsel ....................................................................1
`
`Service Information..................................................................................2
`D.
`PAYMENT OF FEES ......................................................................................2
`II.
`III. REQUIREMENTS FOR INTERPARTESREVIEW .................................3
`A.
`Grounds For Standing ..............................................................................3
`
`B.
`
`3.
`4.
`
`Identification Of Challenge......................................................................3
`Claims for which inter partes review is requested ........................3
`1.
`2.
`The specific art and statutory ground(s) on which the
`challenge is based...........................................................................3
`How the challenged claims are to be construed.............................5
`How the construed claims are unpatentable under the
`statutory grounds identified in paragraph (b)(2) of this
`section ............................................................................................5
`Supporting evidence relied upon to support the challenge............6
`5.
`SUMMARY OF THE ’882 PATENT .............................................................6
`A.
`Description Of The Alleged Invention.....................................................6
`
`IV.
`
`B.
`
`Summary Of The Prosecution History.....................................................7
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`Inter Partes Review of U.S. Pat. 6,947,882
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`TABLE OF CONTENTS (CONT’D)
`
`V.
`
`THERE IS A REASONABLE LIKELIHOOD THAT AT LEAST
`ONE CLAIM OF THE ’882 PATENT IS UNPATENTABLE ....................9
`A.
`Identification Of The References As Prior Art ........................................9
`
`B.
`
`Summary Of Invalidity Arguments........................................................10
`1.
`The ’191 patent invalidates claims 1-14 and 17-20 of the
`’882 patent....................................................................................10
`The ’760 patent invalidates claims 5-8 and 17-20 of the
`’882 patent....................................................................................13
`The Agarwal patent invalidates claims 5-8, 17, and 20 of
`the ’882 patent..............................................................................13
`VI. DETAILED EXPLANATION.......................................................................14
`A.
`’191 Patent Claim Chart.........................................................................14
`
`2.
`
`3.
`
`B.
`
`’760 Patent Claim Chart.........................................................................40
`
`Agarwal Claim Chart..............................................................................48
`C.
`VII. CONCLUSION ...............................................................................................56
`
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`Inter Partes Review of U.S. Pat. 6,947,882
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`EXHIBIT LIST
`
`SYNOPSYS 1001
`
`U.S. Pat. 6,947,882 (the “’882 patent”)
`
`SYNOPSYS 1002
`
`U.S. Pat. 5,960,191 (the “’191 patent”)
`
`SYNOPSYS 1003
`
`U.S. Pat. 5,475,830 (“Chen”)
`
`SYNOPSYS 1004
`
`U.S. Pat. 6,020,760 (the “’760 patent”)
`
`SYNOPSYS 1005
`
`U.S. Pat. 5,761,484 (“Agarwal”)
`
`SYNOPSYS 1006
`
`U.S. App. Ser. No. 09/404,920 dated Sept. 24, 1999
`
`SYNOPSYS 1007
`
`Office Action dated Nov. 8, 2002
`
`SYNOPSYS 1008
`
`Office Action Response dated Dec. 24, 2002
`
`SYNOPSYS 1009
`
`Office Action dated Feb. 10, 2003
`
`SYNOPSYS 1010
`
`RCE and Amendment dated July 10, 2003
`
`SYNOPSYS 1011
`
`Office Action dated Aug. 25, 2003
`
`SYNOPSYS 1012
`
`Response to Restriction Requirement dated Sept. 17,
`2003
`
`SYNOPSYS 1013
`
`Office Action dated Dec. 5, 2003
`
`SYNOPSYS 1014
`
`Office Action Response dated March 3, 2004
`
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`Inter Partes Review of U.S. Pat. 6,947,882
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`Petitioner Synopsys, Inc. (“Synopsys” or “Petitioner”) respectfully requests
`inter partes review for claims 1-14 and 17-20 of U.S. Patent No. 6,947,882 (the
`“’882 patent,” attached as Ex. 1001) in accordance with 35 U.S.C. §§ 311-319 and
`37 C.F.R. § 42.100 et seq.
`
`I. MANDATORY NOTICES
`
`to 37 C.F.R. § 42.8(a)(1), Synopsys provides the following
`Pursuant
`mandatory disclosures.
`
`A. Real Party-In-Interest
`
`Pursuant to 37 C.F.R. § 42.8(b)(1), Petitioner certifies that Synopsys, Inc. is
`the real party-in-interest.
`
`B. Related Matters
`
`to 37 C.F.R. § 42.8(b)(2), Petitioner identifies the following
`Pursuant
`judicial or administrative matters that would affect, or be affected by, a decision in
`this proceeding: Mentor Graphics Corp. v. EVE-USA, Inc. et al., No. 3-12-cv-
`01500 (D. Or. Aug. 17, 2012).
`
`C. Lead And Back-Up Counsel
`
`to 37 C.F.R. § 42.8(b)(3), Petitioner provides the following
`Pursuant
`designation of counsel:
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`Inter Partes Review of U.S. Pat. 6,947,882
`
`Lead Counsel
`
`William H. Wright
`wwright@orrick.com
`Registration No. 36,312
`CA Bar No. 161580
`ORRICK, HERRINGTON, &
`SUTCLIFFE LLP
`777 South Figueroa Street, Suite
`3200
`Los Angeles, California 90017
`Tel:213-629-2020
`Fax: 213-612-2499
`Customer No. 34313
`
`Backup Counsel
`Travis Jensen
`tjensen@orrick.com
`Registration No. 60,087
`CA Bar No. 259925
`
`ORRICK, HERRINGTON, &
`SUTCLIFFE LLP
`1000 Marsh Road
`Menlo Park, CA 94025-1015
`Tel: 650-614-7400
`Fax: 650-614-7401
`
`Customer No. 34313
`
`Pursuant to 37 C.F.R. § 42.10(b), a Power of Attorney accompanies this
`Petition.
`
`D. Service Information
`
`Pursuant to 37 C.F.R. § 42.8(b)(3), service information for lead and backup
`counsel is provided above.
`
`II. PAYMENT OF FEES
`
`The undersigned authorizes the Office to charge $27,200.00 to Deposit
`Account No. 15-0665 as the fee required by 37 C.F.R. § 42.15(a) for this Petition
`for inter partes Review. Review of 18 claims is requested, so no excess claims fee
`is required. The undersigned further authorizes payment for any additional fees
`that might be due in connection with this Petition to be charged to the above
`referenced Deposit Account.
`
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`Inter Partes Review of U.S. Pat. 6,947,882
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`III. REQUIREMENTS FOR INTERPARTESREVIEW
`
`As set forth below and pursuant to 37 C.F.R. § 42.104, each requirement for
`inter partes review of the ’882 patent is satisfied.
`
`A. Grounds For Standing
`
`Pursuant to 37 C.F.R. § 42.104(a), Petitioner certifies that the ’882 patent is
`available for inter partes review and that the Petitioner is not barred or estopped
`from requesting inter partes review challenging the claims of the ’882 patent on
`the grounds identified herein.
`
`B.
`
`Identification Of Challenge
`
`Pursuant to 37 C.F.R. § 42.104(b), the precise relief requested by Petitioner
`is that the Patent Trial and Appeal Board (“PTAB”) invalidate claims 1-14 and 17-
`20 of the ’882 patent.
`
`1. Claims for which interpartesreview is requested
`
`Petitioner requests inter partes review of claims 1-14 and 17-20 of the ’882
`patent.
`
`2. The specific art and statutory ground(s) on which the challenge
`is based
`
`Inter partes review of the ’882 patent is requested in view of the following
`references, each of which is prior art to the ’882 patent under 35 U.S.C. § 102(a),
`(b), and/or (e):
`
`(1) U.S. Pat. 5,960,191 issued to Stephen P. Sample et al.
`“’191 patent,” attached as Ex. 1002);
`
`(the
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`(2) U.S. Pat. 5,475,830 issued to Nang-Ping Chen et al. (“Chen,” attached
`as Ex. 1003);
`
`(3) U.S. Pat. 6,020,760 issued to Stephen P. Sample et al.
`“’760 patent,” attached as Ex. 1004); and
`
`(the
`
`(4) U.S. Pat. 5,761,484 issued to Anant Agarwal et al. (“Agarwal,”
`attached as Ex. 1005).
`
`The ’191 patent both anticipates (under 35 U.S.C. § 102) and renders
`obvious (under 35 U.S.C. § 103) claims 1-14 and 17-20 of the ’882 patent. The
`’760 patent both anticipates (under 35 U.S.C. § 102) and renders obvious (under 35
`U.S.C. § 103) claims 5-8 and 17-20 of the ’882 patent. The Agarwal patent both
`anticipates (under 35 U.S.C. § 102) and renders obvious (under 35 U.S.C. § 103)
`claims 5-8, 17, and 20 of the ’882 patent. The table below summarizes the specific
`art and statutory grounds on which the challenges are based.
`
`Claim
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`10.
`
`’191 Patent
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`’760 Patent
`
`Agarwal
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
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`Inter Partes Review of U.S. Pat. 6,947,882
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`Claim
`
`11.
`
`12.
`
`13.
`
`14.
`
`15.
`
`16.
`
`17.
`
`18.
`
`19.
`
`20.
`
`’191 Patent
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`’760 Patent
`
`Agarwal
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`102 and 103
`
`3. How the challenged claims are to be construed
`
`A claim subject to inter partes review receives the “broadest reasonable
`construction in light of the specification of the patent in which it appears.” 42
`C.F.R. § 42.100(b). Petitioner submits, for the purposes of this inter partes review
`only, that the claim terms take on their ordinary and customary meaning that the
`terms would have to one of ordinary skill in the art. Petitioner submits that none of
`the challenged claims contain a means-plus-function or
`step-plus-function
`limitation.
`
`4. How the construed claims are unpatentable under the statutory
`grounds identified in paragraph (b)(2) of this section
`
`An explanation of how construed claims 1-14 and 17-20 of the ’882 patent
`are unpatentable under the statutory grounds identified above,
`including the
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`Inter Partes Review of U.S. Pat. 6,947,882
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`identification of where each element of the claim is found in the prior art patents or
`printed publications, is provided in Section VI, below, in the form of claim charts.
`
`5. Supporting evidence relied upon to support the challenge
`
`The exhibit numbers of the supporting evidence relied upon to support the
`challenge and the relevance of the evidence to the challenge raised, including
`identifying specific portions of the evidence that support
`the challenge, are
`provided in Section VI, below, in the form of claim charts. An Exhibit List
`identifying the exhibits is also included.
`
`IV. SUMMARY OF THE ’882 PATENT
`
`The ’882 patent is titled “Regionally Time Multiplexed Emulation System”
`and names Frederic Reblewski, Oliver Lepaps, and Jean Barbier as inventors. The
`’882 patent issued on Sept. 20, 2005 from an application filed on Sept. 24, 1999.
`The ’882 patent includes twenty total claims. Independent claims 1 and 5, as
`well as the remaining claim dependencies are show in the claim tree below.
`
`1
`
`5
`
`2 3 4
`
`6
`
`8 9 10
`
`13 14
`
`17 18
`
`20
`
`7
`
`11 12
`
`15
`
`16
`
`19
`
`A. Description Of The Alleged Invention
`
`The ’882 patent is directed to a “regionally time multiplexed” system for
`emulating a circuit design. ’882 patent Abstract. The system includes a plurality
`of reconfigurable logic devices (e.g., field programmable gate array chips or
`FPGAs).
`’882 patent Abstract and Fig. 2. The FPGAs include reconfigurable
`“logic elements” and I/O pins. ’882 patent Abstract. Circuit board traces, routing
`chips, or other conventional wiring techniques are used to connect the FPGAs.
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`Inter Partes Review of U.S. Pat. 6,947,882
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`’882 patent 5:33-35; 6:61-64; and 10:35-38. The system uses “at least one user
`clock to clock the logic elements and at least one signal routing clock to time
`multiplex the routing of emulation signals between the [FPGAs], with the at least
`one signal routing clock being independent of the at least one user clock.” ’882
`patent Abstract.
`A second aspect of the ’882 patent deals with achieving simultaneous bi-
`directional data transfer over a single connection.
`’882 patent 2:62-63; Fig. 11;
`and 10:29-11:23.
`
`B. Summary Of The Prosecution History
`
`The ’882 patent was in prosecution for nearly seven years, including through
`the filing of two Requests for Continued Examination (“RCE”). In each of the four
`office actions issued during this period, the examiner rejected all of the claims that
`were pending at the time.
`As originally filed in 1999, the application that matured into the ’882 patent
`contained 22 claims. Ex. 1006 at 26-31. A first Office Action dated Nov. 8, 2002
`rejected claims 1-16 as anticipated by U.S. Patent No. 5,701,441 (“Trimberger”)
`and rejected claims 17-22 as anticipated by the ’191 patent. Ex. 1007.
`In a
`response dated Dec. 24, 2002, the applicant presented arguments to traverse the
`anticipation rejections. Ex. 1008. The applicant’s only argument directed to the
`’191 patent related to a “bidirectional data transfer connection …” limitation. Ex.
`1008 at page 6.
`In a second Office Action dated Feb. 10, 2003, the anticipation rejections
`were made final. Ex. 1009. In response, on July 10, 2003, the applicant filed an
`RCE accompanied by an amendment cancelling claims 1-9, adding claims 23-39
`(many of which were similar to the cancelled claims), and traversing the rejection
`of claims 10-22. See Ex. 1010.
`In particular, the applicant again traversed the
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`rejection of claims 17-22 based on the ’191 patent solely on the “bi-directional data
`transfer …” limitation. See Ex. 1010 at 11-12.
`In a third Office Action dated Aug. 25, 2003, the examiner issued a three-
`way restriction requirement. See Ex. 1011. The examiner stated that group II
`(consisting of claims 17-22) “is directed to bi-directional communication link
`using a single trace or wire which has separate utility such as that of a system for
`communicating between devices on chips or boards which is separate and distinct
`from Group I and Group III.” See Ex. 1011 at 2.
`In a response dated Sept. 17,
`2003, the applicant elected to pursue claims 13-16 and 23-38. See Ex. 1012.
`In a fourth Office Action dated Dec. 5, 2003, the examiner made anticipation
`rejections based on Trimberger,
`the ’191 patent, and Japanese reference 04-
`138569-1992 (“Okuda”). See Ex. 1013.
`In an apparent oversight, the examiner
`stated that the elected claims were anticipated by the ’191 patent but proceeded to
`analyze and reject only non-elected claims 17-22. Compare Ex. 1013 at 8-9 with
`the identical rejection of claims 17-22 in the Feb. 10, 2003 Office Action, Ex. 1009
`at 11-12.
`In an Office Action Response dated March 3, 2004, the applicant cancelled
`non-elected claims 1-12, 17-22, and 39 and traversed the rejections of the elected
`claims. See Ex. 1014. With respect to the rejections based on the ’191 patent, the
`applicant stated:
`
`“[T]he Office’s remarks relating to the rejection based on [the ’191
`patent] do not appear to relate in any respect
`to the content of
`independent claims 13 and 23 in this application. Rather,
`these
`remarks appear to relate to the content of non-elected claims 17-22.
`Accordingly, on its face, this rejection fails to carry the Office’s
`burden of establishing that claims 13-16 and 23-38 are anticipated by
`Sample.” Ex. 1014 at 11-12.
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`Inter Partes Review of U.S. Pat. 6,947,882
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`Elected claims 13-16 and 23-38 were subsequently allowed in a Notice of
`Allowability dated March 19, 2004. The applicant submitted a second RCE
`request, filed additional information disclosure statements, and the ’882 patent
`issued on Sept. 20, 2005.
`
`V. THERE IS A REASONABLE LIKELIHOOD THAT AT LEAST ONE
`CLAIM OF THE ’882 PATENT IS UNPATENTABLE
`
`A.
`
`Identification Of The References As Prior Art
`
`U.S. Pat. 5,960,191 titled “Emulation System With Time Multiplexed
`Interconnect” issued to Stephen P. Sample et al. (the “’191 patent,” Ex. 1002). The
`’191 patent issued on Sept. 28, 1999 from an application filed on May 30, 1997.
`The ’191 patent is prior art to the ’882 patent under at least 35 U.S.C. § 102(e).
`U.S. Pat. 5,475,830 titled “Structure And Method For Providing A
`Reconfigurable Emulation Circuit Without Hold Time Violations” issued to Nang-
`Ping Chen et al. (“Chen,” Ex. 1003). Chen issued on Dec. 12, 1995 from an
`application filed on Jan. 31, 1992. Chen is prior art to the ’882 patent under at
`least 35 U.S.C. § 102(a), (b), and (e).
`U.S. Pat. 6,020,760 titled “I/O Buffer Circuit With Pin Multiplexing” issued
`to Stephen P. Sample et al. (the “’760 patent,” Ex. 1004). The ’760 patent issued
`on Feb. 1, 2000 from an application filed on July 16, 1997. The ’760 patent is
`prior art to the ’882 patent under at least under 35 U.S.C. § 102(e).
`U.S. Pat. 5,761,484 titled “Virtual Interconnections For Reconfigurable
`Logic Systems” issued to Anant Agarwal et al. (“Agarwal,” Ex. 1005). Agarwal
`issued on June 2, 1998 from a PCT application filed on Apr. 1, 1994 which entered
`the U.S. national stage on Sept. 28, 1995. Agarwal is prior art to the ’882 patent
`under at least 35 U.S.C. § 102(a) and (b).
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`Inter Partes Review of U.S. Pat. 6,947,882
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`B. Summary Of Invalidity Arguments
`
`FPGA based circuit emulation systems have been known for decades.
`Indeed, the ’882 patent recognizes that “[e]mulation systems for emulating circuit
`designs are known in the art” and that such “systems are formed using
`conventional general purpose field programmable gate arrays (FPGAs) and general
`purpose routing chips.”
`’882 patent 1:12-16.
`Likewise,
`the ’882 patent
`acknowledges that “time multiplexing” multiple internal FPGA signals onto a
`single I/O pin for transfer to another FPGA chip was known in the art. ’882 patent
`1:33-48. The applicant’s primary criticism of prior art emulation systems was that
`the prior art systems purportedly did “not support
`time multiplexing of
`asynchronous signals.”
`’882 patent 1:52-53. As summarized below, the prior
`taught did teach this and all other elements of the challenged claims.
`
`1. The ’191 patent invalidates claims 1-14 and 17-20 of the ’882
`patent
`
`The ’191 patent anticipates claims 1-14 and 17-20 of the ’882 patent. To the
`extent not anticipated by the ’191 patent, each of claims 1-14 and 17-20 would
`have been obvious to a person of ordinary skill in the art in view of the ’191 patent.
`See, e.g., In re Yufa, Appeal No. 452 Fed. Appx. 998, 1000 (Fed. Cir. 2012)
`(affirming single reference obviousness rejections during reexamination). The
`Abstract of the ’191 patent reads as though written for the ’882 patent:
`
`A hardware emulation system is disclosed which reduces hardware
`cost by time-multiplexing multiple design signals onto physical logic
`chip pins and printed circuit board. The reconfigurable logic system
`of the present invention comprises a plurality of reprogrammable
`logic devices, and a plurality of reprogrammable interconnect devices.
`The logic devices and interconnect devices are interconnected
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`Inter Partes Review of U.S. Pat. 6,947,882
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`together such that multiple design signals share common I/O pins and
`circuit board traces.
`
`As detailed in section VI, the ’191 patent explicitly or inherently discloses every
`element of each challenged claim,
`including the alleged point of novelty—
`independent clocks. At a minimum, each challenged claim element would have
`been obvious to a person of ordinary skill in the art in view of the ’191 patent.
`Furthermore, the concept of asynchronous or independent clocks is disclosed in
`Chen.
`
`Given that the ’191 patent specifically incorporates Chen by reference (’191
`patent 2:27-31), Chen is part of the anticipatory disclosure of the ’191 patent. In
`addition, the incorporation by reference would have motivated a person of ordinary
`skill in the art to combine the references. Thus, the ’191 patent in combination
`with Chen obviate ’882 patent claims 1-14 and 17-20.
`The ’191 patent alone, and in combination with Chen, establish much more
`than “a reasonable likelihood” that the challenged claims are unpatentable. 35
`U.S.C. § 314(a). The fact that the ’191 patent served as the basis for rejection
`during prosecution (discussed supra section IV.B) should not preclude institution
`of an inter partes review because Petitioner is presenting the ’191 patent in a new
`light.
`
`Although no statute or case is directly on point for inter partes review,
`analogous statutory and case law is clear that so-called “old art” may serve as the
`basis for reexamination. Title 35 U.S.C. § 312(a), as amended on September 16,
`2011 by the America Invents Act, explicitly states that “[a] showing that there is a
`reasonable likelihood that the requester would prevail with respect to at least 1 of
`the claims challenged in the [inter partes reexamination] request is not precluded
`by the fact that a patent or printed publication was previously cited by or to the
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`Office or considered by the Office.” Similarly, under pre-September 16, 2011
`inter partes reexamination law, “old art” could establish a substantial new question
`See, e.g., MPEP § 2616 (“The substantial new question of
`of patentability.
`patentability [for inter partes reexamination] may be based on art previously
`considered by the Office if the reference is presented in a new light or a different
`way that
`escaped review during earlier
`examination.”); MPEP § 2642
`(“Determinations on whether a substantial new question of patentability exists in
`such an instance shall be based upon a fact-specific inquiry done on a case-by-case
`basis. For example, a substantial new question of patentability may be based
`solely on old art where the old art is being presented/viewed in a new light, or in a
`different way, as compared with its use in the earlier examination(s), in view of a
`material new argument or interpretation presented in the request.”).
`In the instant request, Petitioner is only relying on the ’191 patent to
`challenge claims which were not rejected over the ’191 patent during prosecution.
`Specifically, the examiner relied on the ’191 patent to reject original claims 17-22
`(see, e.g., Office Action dated Feb. 10, 2003, Ex. 1009 at 11-12). As noted by the
`examiner when he imposed the restriction requirement, claims 17-22 were “drawn
`to a system with bi-directional data transfer on a single wire between chips,” not
`clocking. See Ex. 1011 at 2. In fact, the term “clock” does not appear anywhere in
`original claims 17-22 (Ex. 1006 at 30-31) which the applicant subsequently
`cancelled (Ex. 1014 at 7). In contrast, various “clocking” limitations are central to
`each of the challenged claims. Accordingly, this Petition presents the ’191 patent
`in a new light.
`Moreover, Chen—which was not cited during prosecution—discusses
`clocking in detail including disclosing that “[a]ny pair of clock signals from
`different clock trees are assumed ‘asynchronous.’” Ex. 1003, Chen at 10:18-19. In
`summary, given the fact that the ’191 patent specifically incorporates Chen by
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`reference (’191 patent 2:27-31), a person of ordinary skill in the art would have
`motivation to combine the references. Thus, the ’191 patent is presented in a new
`light in view of Chen.
`
`2. The ’760 patent invalidates claims 5-8 and 17-20 of the ’882
`patent
`
`The ’760 patent anticipates claims 5-8 and 17-20 of the ’882 patent. To the
`extent not anticipated by the ’760 patent, each of claims 5-8 and 17-20 would have
`been obvious in view of the ’760 patent. The ’760 patent was not made of record
`during prosecution of the ’882 patent.
`The ’760 patent is generally directed to “implementing reconfigurable logic,
`such as a field programmable gate array (‘FPGA’)” with “flexible input/output
`buffer circuits” for “transfer[ing] data either bidirectionally or unidirectionally
`between an input/output pin and a FPGA core.” ’760 patent Abstract. The I/O
`circuitry “may be used to time-multiplex at least two signals onto an input pin, at
`least two signals onto an output pin, or both.” Id. “The circuitry provides two
`connections into the FPGA core which can be used to time-multiplex at least two
`independent inputs or outputs.” Id.
`As detailed in section VI, the ’760 patent explicitly or inherently discloses
`every element of ’882 patent claims 5-8 and 17-20, including the alleged point of
`novelty—independent clocks. At a minimum, these claims would have been
`obvious to a person of ordinary skill in the art in view of the ’760 patent.
`
`3. The Agarwal patent invalidates claims 5-8, 17, and 20 of the
`’882 patent
`
`Agarwal’s title is descriptive: “Virtual Interconnections for Reconfigurable
`Logic Systems.” The “virtual interconnections” disclosed in Agarwal “overcome
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`pin limitations by intelligently multiplexing each physical wire among multiple
`logical wires and pipelining these connections at
`the maximum clocking
`frequency.” Agarwal Abstract. Agarwal’s virtual interconnections are beneficial
`in “logic emulation systems employing Field Programmable Gate Arrays
`(FPGAs).” Id.
`Agarwal anticipates claims 5-8, 17, and 20 of the ’882 patent. To the extent
`not anticipated by Agarwal, the aforementioned claims are obvious in view of
`Agarwal. Agarwal is listed on the face of the ’882 patent but was not relied on as
`the basis for rejection during prosecution.
`As detailed in section VI, Agarwal explicitly or inherently discloses every
`element of ’882 patent claims 5-8, 17, and 20, including the alleged point of
`novelty—independent clocks. At a minimum, these claims would have been
`obvious to a person of ordinary skill in the art in view of Agarwal.
`
`VI. DETAILED EXPLANATION
`
`Pursuant to 37 C.F.R. § 42.104(b)(4), Petitioner provides in the following
`claim charts a detailed comparison of the claimed subject matter and the prior art
`specifying where each element of challenged claim is found in the prior art
`references. All emphasis is added unless otherwise indicated.
`
`A.
`
`’191 Patent Claim Chart
`
`Claim Language
`1. An emulation
`system
`comprising:
`
`’191 Patent (Ex. 1002)
`“A hardware emulation system is disclosed which reduces
`hardware cost by time-multiplexing multiple design signals
`onto physical logic chip pins and printed circuit board.” ’191
`patent Abstract.
`“The present invention relates in general to apparatus for
`verifying electronic circuit designs and more specifically to
`hardware emulation systems in which multiple design signals
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`Claim Language
`
`[a] a first plurality
`of reconfigurable
`logic devices;
`
`’191 Patent (Ex. 1002)
`are carried on a single physical wire between programmable
`logic chips.” ’191 patent 1:5-9.
`“The reconfigurable logic system of the present invention
`comprises a plurality of reprogrammable logic devices, and a
`plurality of reprogrammable interconnect devices.” ’191
`patent Abstract.
`“Examples of logic chips include reprogrammable logic
`circuits such as field-programmable gate arrays (‘FPGAs’),
`which include both off-the-shelf products and custom
`products.” ’191 patent 1:17-20.
`“In the presently preferred embodiment [Fig. 11], there
`are . . . thirty-six logic chips (FPGAs) 10 with two-hundred
`and seventy I/O pins each. The presently preferred
`embodiment utilizes FPGAs as logic chips 10 with the part
`number XC4036XL manufactured Xilinx Corporation[.]”
`’191 patent 14:31-36.
`
`[b] a second
`plurality of
`reconfigurable
`logic devices;
`[c] a third
`plurality of
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`See element 1[a].
`
`See element 1[a].
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`Claim Language
`reconfigurable
`logic devices;
`[d] a first time
`multiplexed
`interconnection
`coupled to and
`situated between
`the first plurality
`of reconfigurable
`logic devices and
`the second
`plurality of
`reconfigurable
`logic devices; and
`
`’191 Patent (Ex. 1002)
`
`“The reconfigurable logic system of the present invention
`comprises a plurality of reprogrammable logic devices, and a
`plurality of reprogrammable interconnect devices. The logic
`devices and interconnect devices are interconnected together
`such that multiple design signals share common I/O pins and
`circuit board traces.” ’191 patent Abstract.
`“The partial crossbar interconnect of FIG. 1 comprises a
`number of reprogrammable interconnect blocks 12, which in
`a preferred embodiment are multiplexer chips (Mux chips).
`The partial crossbar interconnect of FIG. 1 further comprises a
`number of reprogrammable configurable logic chips 10, which
`in a presently preferred embodiment are field-programmable
`gate arrays (FPGAs). Each Mux chip 12 has one or more
`connections to each logic chip 10.” ’191 patent 6:57-65.
`
`See element 1[d].
`
`[e] a second time
`multiplexed
`interconnection
`coupled to and
`situated between
`the second
`plurality of
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`Claim Language
`reconfigurable
`logic devices and
`the third plurality
`of reconfigurable
`logic devices,
`[f] wherein
`clocking of the
`second time
`multiplexed
`interconnection is
`independent of
`clocking of the
`first time
`multiplexed
`interconnection.
`
`2. The emulation
`system of claim 1,
`wherein each of
`the first plurality
`of reconfigurable
`logic devices,
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`’191 Patent (Ex. 1002)
`
`“A High Speed Asynchronous Clock Signal 144 is distributed
`to all chips in the system. Unlike the Mux Clock 44 described
`earlier with reference to FIG. 2, Asynchronous Clock Signal
`144 need not be synchronized between any two chips in the
`system or even between two pins on the same chip.
`Therefore, there is no need for a SYNC-Signal 48 as described
`earlier with reference to FIG. 2. Also, Asynchronous Clock
`Signal 144 may operate at any speed as long as the minimum
`pulse width produced on External Signal 144 will pass
`through the interconnect without undue degradation.” ’191
`patent 11:40-50.
`“On control board 600, a Mux chip 12 is used to select a
`combination of clocks from all of the different potential
`sources. The system may have up to thirty-two distinct clock
`sources. Any eight of these may be used on a pair of
`emulation boards 200. This allows different pairs of
`emulation boards 200 to have different clocks as might be
`required, for example, when more than one chip design was
`being emulated in a single hardware emulation system.
`Clocks are routed through programmable delay element 604
`and buffers 614 then through backplane 800 or 802 to
`emulation boards 200.” ’191 patent 19:54-66.
`“Any pair of clock signals from different clock trees are
`assumed ‘asynchronous.’” Chen (Ex. 1003) at 8:18-19; see
`also Chen at 5:38-47, 8:56-67, and 14:28-30.
`“Examples of logic chips include reprogrammable logic
`circuits such as field-programmable gate arrays (‘FPGAs’),
`which include both off-the-shelf products and custom
`products.” ’191 patent 1:17-20.
`“In the presently preferred embodiment [Fig. 11], there
`are . . . thirty-six logic chips (FPGAs) 10 with two-hundred
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`’191 Patent (Ex. 1002)
`and seventy I/O pins each. The presently preferred
`embodiment utilizes FPGAs as logic chips 10 with the part
`number XC4036XL manufactured Xilinx Corporation[.]”
`’191 patent 14:31-36.
`
`Claim Language
`each of the second
`plurality of
`reconfigurable
`logic devices, and
`each of the third
`plurality of
`reconfigurable
`logic devices is a
`field
`programmable
`gate array.
`
`3. The emulation
`system of claim 1,
`wherein the first
`time multiplexed
`interconnection
`includes a first set
`of input/output
`circuitry of a
`multi-clocked
`routing chip and
`the second time
`multiplexed
`interconnection
`includes a second
`set of input/output
`circuitry of the
`multi-clocked
`routing chip.
`
`“The invention also comprises a plurality of repro