‘
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`~'
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`"
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`MW
`PATENT (\2 ,0’} 1
`7
`
`Re Application Of:
`
`Frederic Reblewski et a1.
`
`Appln.No.: 09/404,920
`
`Filed: September 24, 1999
`
`For:
`
`.A REGIONALLY TIME MULTIPLEXED
`EMULATION SYSTEM
`
`Commissioner for Patents
`PO. Box 1450
`Alexandria, VA 223134450
`
`‘
`
`Sir:
`
`VVVVVVVVVV
`
`Group Art Unit: 2123
`
`Examiner: S. Makhdoom
`
`Confirmation No.2 8906
`
`Atty. Dkt. No. 003921 .00099
`
`RECEIVED
`
`J U L 1 5 2003
`Technology Center 2100
`
`AMENDMENT ACCOMPANYING REQUEST FOR
`CONTINUED EXAMINATION AND PETITION FOR
`TWO-MONTH EXTENSION OF TIME
`
`This Amendment is responsive to the Final Office Action mailed February 10, 2003 in the
`
`above-identified patent application, and it accompanies a Request for Continued Examination and a
`
`Petition for Extension of Time for two months.
`
`In response to the Final Office Action, please amend the instant application as described
`
`below:
`
`Amendments to the Specification begin on page 2 of this Paper.
`
`Amendments to the Claims are reflected in the Listing ofClaims, which begins on page 4 of
`
`this Paper.
`
`No changes to the drawings are made in this Paper.
`
`Remarks begin on page 10 of this Paper.
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`1i I
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`
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`2
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`I EQRZGMZ 00000055 190733
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`09404920
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`Frederic Reblewski et al. —- US. Application No.‘ 09/404,920
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`AMENDMENTS TO THE SPECIFICATION
`
`
`
`Pleaseamendthespecific/msdescribedbelow:
`(A) ”Please amend the paragraph at page 15, lines 3-8 as follows:
`
`
`--In an alternate embodiment ofthe present invention, signals are routed directly from
`
`I/O pins 510 5_1§ of FPGA 501 to/from I/O pins 533 of FPGA 503 without being
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`\
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`routed through RC 502. I/O circuitry 515 and 536 are both clocked by one ofeither
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`signal routing clock 509 or signal routing clock 510. Thus, even though a routing
`
`chip is not used in this alternate embodiment, the signal routing between FPGAs is
`
`still clocked by a signal independent of the user clock signal(s).--.
`
`(B) ‘/Please amend the paragraph at page 22, linesw as follows:
`
`,
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`--Chips 1102 and 1104 can simultaneously transfer signals to each other via
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`connection 1108. Chips 1102 and 1104 each include I/O circuitry, including a driver
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`and a detection logic as illustrated. An output signal 1121 to be output by chip 1102
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`is driven onto connection 1108 via driveri-l-z-L‘ m3. Concurrently, an output signal
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`1132 to be output by chip 1104 is driven onto connection 1108 via driver 1133.
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`3“
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`After the signals are driven onto connection 1108, detection logics 1125 and 1135
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`each sample the voltage level of connection 1108. Based on the sampled voltage
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`I
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`level ofconnection 1108, as well as possiblytheoutput signal 1132, detectionlogic
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`1135 provides an input signal 1131 to the internal circuitry of chip 1104 which is
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`representative of output signal 1121 driven by chip 1102. Similarly, based on the
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`sampled voltage level ofconnection 1108, as well as possibly the output signal 1 121,
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`Frederic Reblewski et al. — US. Application No."09/404,920
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`9/
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`£\ 1102 which is representative ofoutput signal 1132 drivenby chip 1104.--.
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`detection logic 1125 provides an input signal 1122 to the internal circuitry of chip
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`Fredergieblewski et al. — US. Application N$§/404,920
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`LISTING OF CLAIMS
`
`This Listing of Claims will replace all prior versions and Listings of Claims in the
`
`application:
`
`Claims 1-9 (Canceled without prejudice or disclaimer by this Amendment).
`
`
`10.
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`Original) A multi-clocked routing chip for use in an emulation system,
`
`the
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`multi-clocked r uting chip comprising:
`
`a reconfi
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`ble static routing circuit;
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`a first set of in ut/output circuitry coupled to provide inputs to and receive outputs from the
`
`reconfigurable static rout1 g circuit, wherein the first set ofinput/output circuitry is clocked by a first
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`clock signal; and
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`a second set of input/cu
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`t circuitry coupled to provide inputs to and receive outputs from
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`the reconfigurable static routing circ 't, wherein the second set ofinput/output circuitry is clocked by
`
`a second clock signal different than the rst clock signal.
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`11.
`
`(Original) The multi-routing
`
`ip of claim 10, wherein the first and second sets of
`
`input!output circuitry each includes a plurality o one-to-n demultiplexers and a plurality ofn-to-one
`
`multiplexers, where n is an integer greater than 1.
`
`12.
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`(Original) The multi-routing chip of c im 10, further comprising a third set of
`
`input/output circuitry coupled to provide inputs to and rece ve outputs from the reconfigurable static
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`routing circuit, wherein the third set of input/output circui
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`is clocked by a third clock signal
`
`different than the first and second clock signals.
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`13. (Original) An emulation system comprising:
`
`a first plurality of reconfigurable logic devices;
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`a second plurality of reconfigurable logic devices;
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`Fredergeblewski et a]. — US. Application No. 09/404,920
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`a third plurality of reconfigurable logic devices;
`
`
`a first time multiplexed interconnection coupled to and situated between the first plurality of
`
`
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`a S 0nd time multiplexed interconnection coupled to and situated between the second
`
`
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`plurality of re nfigurable logic devices and the third plurality of reconfigurable logic devices,
`
`‘
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`wherein clocking f the second time multiplexed interconnection is independent of clocking of the
`
`first time multiplexe interconnection.
`
`14.
`
`(Original)
`
`
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`e emulation system of claim 13, wherein each of the first plurality of
`
`reconfigurable logic device each ofthe second plurality ofreconfigurable logic devices, and each of
`
`the third plurality of reconfigu ble logic devices is a field programmable gate array (FPGA).
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`15.
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`(Original) The em ation system of claim 13, wherein the first time multiplexed
`
`interconnection includes a first set 0 input/output circuitry of a multi-clocked routing chip and the
`
`second time multiplexed interconnectio includes a second set of input/output circuitry ofthe multi-
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`clocked routing chip.
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`16.
`
`
`(Original) The emulation syst
`of claim 13, wherein the first time multiplexed V
`
`
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`interconnection includes a first plurality of mul '
`
`lexers and demultiplexers, and the second time
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`multiplexed interconnection includes a second pl
`
`17. (Original) A system comprising:
`
`a first chip;
`
`a second chip; and
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`lity of multiplexers and demultiplexers.
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`
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`a bi-directional data transfer connection, situated betw en the first chip and the second chip,
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`providing simultaneous bi-directional data transfer between the
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`rst and second chips via a single
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`wire or trace.
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`18. (Original) The system of claim 17, wherein the first chip includes a detection logic for
`
`ining a signal value asserted by the second chip based at least in part on a voltage level ofthe
`
`
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`dete
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`bi-dircc 'onal data transfer connection.
`
`19. Original) The system of claim 18, wherein the detection logic is also for determining
`
`the signal value
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`serted by the second chip based at least in part on a signal value asserted by the
`
`first chip.
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`
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`20. (Original)
`
`
`
`first chip comprises a first
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`configurable logic’device ofa plurality ofreconfigurable logic devices.
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`21.
`
`(Original) The system of claim 20, wherein the second chip comprises a first
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`interconnect device of a plur
`
`ity of interconnect devices interconnecting the plurality of '
`
`reconfigurable logic devices.
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`
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`22.
`
`(Original) The system 0 claim 20, wherein the second chip comprises a second
`
`reconfigurable logic device of the pluralit of reconfigurable logic devices.
`
`23. (Newly Added) An emulator f0 emulating a circuit design, comprising:
`
`a first reconfigurable logic device tha includes a first plurality of reconfigurable logic
`
`elements and first input/output circuitry;
`
`
`
`a second reconfigurable logic device that incl
`
`(163 a second plurality ofreconfigurable logic
`
`elements and second input/output circuitry;
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`
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`a first clock signal for clocking the first plurality o reconfigurable logic elements;
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`a second clock signal for clocking the second plurali
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`
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`freconfigurable logic elements; and
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`at least one signal routing clock signal for clocking the first input/output circuitry and the
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`second input/output circuitry, wherein the signal routing clock si
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`signal and the second clock signal.
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`is independent ofthe first clock
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`4. (Newly Added) An emulator according to claim 23, wherein the first reconfigurable
`
`logic devic is a field programmable gate array.
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`25.
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`
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`wly Added) An emulator according to claim 24, wherein the second reconfigurable
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`logic device is a eld programmable gate array.
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`26. (Newl
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`dded) An emulator according to claim 23, wherein the first clock signal and
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`
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`the second clock sign
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`are the same clock signal.
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`27.
`
`(Newly Add ) An emulator according to claim 23, wherein said at least one signal
`
`routing clock signal include a first signal routing clock signal for clocking the first input/output
`
`circuitry and a second signal to ting clock signal for clocking the second input/output circuitry,
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`wherein the first signal routing cloc signal is different from the second signal routing clock signal.
`
`28. (Newly Added) An emul or according to claim 23, further comprising:
`
`at least one interconnect device int connecting the first reconfigurable logic device and the
`
`second reconfigurable logic device, wherein aid interconnect device includes a first input/output
`
`portion and a second input/output portion, wh ein the first input/output circuitry and the first
`
`,
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`input/output portion are clocked by a first signal
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`uting clock signal, and wherein the second
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`
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`"5
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`input/output circuitry and the second input/output po 'on are clocked by a second signal routing
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`clock signal.
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`
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`29.
`
`(Newly Added) An emulator according to c
`
`'m 28, wherein said at least one
`
`interconnect device includes a plurality of multiplexers for time
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`ultiplexing data transfers to and
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`from another interconnect device.
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`
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`30. (Newly Added) An emulator according to claim 28, wher 'n signals are transferred out
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`interconnect device.
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`Frederic Reblewski et al. -— US. Application No. 09/404,920
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`1. (Newly Added) An emulator according to claim 23, further comprising:
`
`' d reconfigurable logic device clocked at least in part by a third clock signal that is
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`different from e first clock signal and the second clock signal.
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`32. (New Added) An emulator according to claim 23, further comprising:
`
`a first interco
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`ect device interconnecting the first reconfigurable logic device and the second
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`reconfigurable logic dev e; and
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`a bi-directional data
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`sfer connection situated between the first reconfigurable logic device
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`and the first interconnect devi
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`, wherein the bi-directional data transfer connection provides
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`
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`simultaneous bi-directional data tr
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`fer between the first reconfigurable logic device and the first
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`,
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`interconnect device via a single wire 0 trace.
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`33. (Newly Added) An emulator ccording to claim 32, wherein the first reconfigurable
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`logic device includes detection logic for dete
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`'ning a signal value asserted by the first interconnect
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`
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`device based at least in part on a voltage level 0
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`
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`e bi-directional data transfer connection.
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`34.
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`(Newly Added) An emulator accordi g to claim 33, wherein the detection logic
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`determines the signal value asserted by the first interco
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`ect device further based at least in part on a
`
`signal value asserted by the first reconfigurable logic devi
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`
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`35. (Newly Added) An emulator according to claim 3, further comprising:
`
`a first set of input/output pins connected to the first inp t/output circuitry for transferring
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`signals to and from the first reconfigurable logic device; and
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`
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`a second set of input/output pins connected to the seco d input/output circuitry for
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`transferring signals to and from the second reconfigurable logic device
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`Frederic Beblewski et al. - US. Application No. 09/404,920
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`36. (Newly Added) An emulator according to claim 23, wherein signals can be transferred
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`into an
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`ut ofthe first reconfigurable logic device asynchronously to changing of signals internal to
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`the first recon
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`able logic device.
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`
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`37. (Newly
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`ded) An emulator according to claim 36, wherein signals can be transferred
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`into and out ofthe second re nfigurable logic device asynchronously to changing ofsignals internal
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`.
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`to the second reconfigurable logic
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`
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`38. (Newly Added) An emulator
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`cording to claim 23, wherein the first reconfigurable
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`
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`logic device is a first field programmable gate
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`ay located on a first chip and the second
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`reconfigurable logic device is a second field programma
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`gate array located on a second chip
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`
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`separate from the first chip.
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`
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`39. (Newly Added) The multi-clocked routing chip of claim 10,
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`erein signals can be
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`transferred out of the reconfigurable static routing circuit asynchronously to input
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`signals to the
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`reconfigurable static routing circuit.
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`Fredergeblewski et al. - US. Application N39/404,920
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`REMARKS
`
`Applicants respectfully request entry ofthis Amendment and continuing prosecution of this
`
`application, as amended.
`
`I.
`
`GENERAL REMARKS REGARDING THE CONTENT OF THIS
`
`AMENDMENT
`
`Upon entry of this Amendment, claims 10-39 will be pending in this application. Original
`
`claims 1-9 are canceled without prejudice or disclaimer by this Amendment, and new claims 23-38
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`replace claims 1-9. Original claims 10-22 remain in the application in their original form, and new
`
`claim 39 depends from claim 10.
`
`New claims 23-26, 28, 29, and 31-34 are based on original claims 1—9 and find support in '
`
`these original claims, but the new claims are of somewhat different format and scope. Support for
`
`new claim 27 can be found, for example, in original claim 3 and at page 10, lines 1-4 of Applicants’
`
`original specification. Support for new claims 30 and 39 can be found, for example, at page 14, lines
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`7-12 of Applicants’ original specification. Support for new claim 35 can be found, for example, at
`
`page 13, lines 1 1-18 and Fig. 5 ofApplicants’ original specification. Support for new claims 36 and
`
`37 can be found, for example, at page 9, lines 17-21 ofApplicants’ original specification. Support
`
`for new claim 38 can be found, for example, at page 12, lines 19-23 and in original claims 17, 20,
`
`and 22. Also, Applicants have made minor changes to the specification by this Amendment so that
`
`the reference numbers used in the specification will match those present in the drawings.
`
`Accordingly, no new matter is included in this Amendment.
`
`11.
`
`APPLICANTS’ CLAIMS PATENTABLY DISTINGUISH FROM THE CITED
`
`ART
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`For anticipation to exist, each and every element ofa claim must be shown in a single
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`reference, and the reference must show these elements arranged in the same manner as
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`Frederic Reblewski et al. — US. Application No. 09/404,920
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`recited in the claim. E The Manual ofPatent Examining Procedure § 2131. As will be
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`demonstrated below, the Sample and Trimberger patents relied upon by the Office fail to
`
`anticipate the invention recited in Applicants’ claims because these cited patents do not
`
`describe the structure defined in the claims.
`
`A.
`
`Applicants’ Claims 17-22 Patentably Distinguish From Sample
`
`Claims 17-22 are rejected under 35 U.S.C. § 102(e) as allegedly anticipated by Sample, et al.,
`
`US. Patent No. 5,960,191 (hereinafter “Sample”). Applicants respectfully traverse this rejection and
`
`request its reconsideration.
`
`Applicants’ independent claim 17 recites a system that includes: (a) a first chip; (b) a second
`
`chip; and (c) a bi-directional data transfer connection situated between the chips. Additionally, claim
`
`17 recites that the bi-directional data transfer connection “provid[es] simultaneous bi-directional data
`
`transfer between the first and second chips via a single wire or trace” [emphasis supplied].
`
`Applicants respectfully submit that nothing in Sample teaches or remotely suggests this claimed
`
`simultaneous bi-directional data transfer connection between two chips over a single wire or trace.
`
`In support of this rejection, the Office points to column 6, line 39 et seq., column 16, lines
`
`25-30, and column 6, lines 40-67 in Sample. While these portions of Sample generally describe use
`
`ofbi-directional signals and bi-directional pins, Applicants respectfully submit that these portions of
`
`Sample do not teach or suggest a bi—directional data transfer connection that provides simultaneous
`
`bi-directional data transfer between two chips via a single wire or trace, as recited in Applicants’
`
`claim 17. Accordingly, Sample clearly fails to anticipate the invention defined in Applicants’ claim
`
`17. Allowance of claim 17 and its associated dependent claims is earnestly solicited.
`
`As to claim 18, this claim additional recites that the first chip includes detection logic for
`
`determining a signal value asserted by the second chip based at least in part on a voltage level of the
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`bi-directional data transfer connection. The Office points to column 16, line 30 et seq. and Fig. 13 in
`
`Sample as allegedly supporting the rejection of this claim. This portion of Sample mentions that a
`
`power board 240 converts from a 48V DC main power supply to a 3.3 V supply necessary to power
`
`the logic board. Nothing in this disclosure ofvoltage reduction teaches or remotely suggests use of
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`detection logic and a voltage level of a bi-directional data transfer connection to determine a signal
`
`value asserted by a chip, as recited in Applicants’ claim 18. Accordingly, Applicants respectfully
`
`submit that Sample fails to anticipate the subject matter of claim 18.
`
`Sample also clearly fails to anticipate the subject matter ofApplicants’ claim 19. This claim
`
`depends from claim 18 and additionally recites that the detection logic determines the signal value .
`
`asserted by the second chip based, at least in part, on a signal value asserted by the first chip. The
`
`cited portion of Sample (column 23,
`
`line 5 et seq.) generally describes routing signals to
`
`programmable edge detectors. Applicants respectfillly submit that this general disclosure in Sample
`
`does not teach or even remotely suggest use ofdetection logic to determine the signal value asserted
`
`by a second chip based, at least in part, on a signal value asserted by a first chip, as recited in
`
`Applicants’ claim 19. Accordingly, Applicants respectfully submit that Sample fails to anticipate the
`
`subject matter of claim 19.
`
`In view of the foregoing, Applicants respectfully submit that claims 17-22 patentably
`
`distinguish from the cited Sample patent. Withdrawal ofthis rejection and allowance of claims 17-
`
`22 are earnestly solicited.
`
`B.
`
`Applicants’ Claims 10-16 and New Claims 23-39 Patentably Distinguish
`From Trimberger
`
`Claims 1-16 are rejected under 35 U.S.C. § 102(b) as allegedly anticipated by Trimberger,
`
`US. Patent No. 5,701,441 (hereinafier “Trimberger”).
`
`Insofar as this rejection may be applied
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`against claims 10-16 and 23-39, Applicants respectfully traverse the rejection and request its
`
`reconsideration.
`
`Applicants’ claim 10 recites a multi—clocked routing chip for use in an emulation system.
`
`The claimed multi-clocked routing chip includes: (a) a reconfigurable static routing circuit; (b) a first
`
`.
`
`set ofinput/output circuitry coupled to provide inputs to and receive outputs from the reconfigurable
`
`static routing circuit, wherein the first set of input/output circuitry is clocked by a first clock signal;
`
`and (c) a second set of input/output circuitry coupled to provide inputs to and receive outputs from
`
`the reconfigurable static routing circuit, wherein the second set ofinput/output circuitry is clocked by
`
`a second clock signal different than the first clock signal. Applicants respectfully submit that
`
`Trimberger does not teach or suggest this claimed multi-clocked routing chip arrangement.
`
`The Office points to column 24, Section 8.2a of Trimberger as allegedly teaching the
`
`clocking aspects recited in Applicants’ claim 10. This portion ofTrimberger relates to clocking ofa
`
`flip-flop 2700 that forms part of a user’s design and receives a clock signal from clock gating
`
`circuitry 2701. While generally discussing multiple clocks in a user circuit design, this portion of
`
`Trimberger has little in common with the invention recited in Applicants’ claim 10. For example,
`
`nothing in this portion of Trimberger and/or the other portions of Trimberger cited by the Office
`
`teach or suggest a multi—clocked routing chip that includes two sets ofinput/output circuitry that are
`
`clocked by two different clock signals as recited in Applicants’ claim 10.
`
`With respect to claim 1 1, this claim further recites that the input/output circuitry in the multi-
`
`clocked routing chip includes multiplexers and demultiplexers. In rejecting this claim, the Office
`
`points to Fig. 52 and column 35 in Trimberger. This portion of Trimberger generally relates to a
`
`multi-clock sequencer 5200 that receives external clock signals and outputs internal micro cycle
`
`clocks that determine the appropriate micro-cycle in which to be active. Nothing in this portion of
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`Fredergeblewski et al. —- US. Application No. 09/404,920
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`Trimberger teaches or remotely suggests the multi-clocked routing chip including multiplexers and
`
`demultiplexers configured in the manner recited in Applicants’ claim 11.
`
`Applicants’ claim 13 recites an emulation system that includes: (a) a first plurality of
`
`reconfigurable logic devices; (b) a second plurality of reconfigurable logic devices; (c) a third
`plurality ofreconfigurable logic devices; ((1) a first time multiplexed interconnection coupled to and
`
`situated between the first and second plurality ofreconfigurable logic devices; and (e) a second time
`
`multiplexed interconnection coupled to and situated between the second and third plurality of
`
`reconfigurable logic devices. Claim 13 further recites that the clocking of the second time
`
`multiplexed interconnection is independent ofclocking ofthe first time multiplexed interconnection.
`
`The Office relies on Fig. 58 and Fig. 55 of Trimberger as allegedly showing the time
`
`multiplexed interconnection and clocking features of Applicants’ claim 13. As described in
`
`Trimberger, the circuit of Fig. 58 is used to eliminate or bypass some of the buffers normally
`
`associated with multiplexers 5601A and 5602A. Applicants respectfully submit that, when
`
`considered in context, the combination of Figs. 55 and 58 clearly does not result in an emulation
`
`system including the independent time multiplexed interconnection arrangement recited in claim 13.
`
`Applicants further submit that new claims 23-38 patentably distinguish from the teachings of
`
`Trimberger. Claim 23 recites an emulator for emulating a circuit design that includes: (a) a first
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`reconfigurable logic device that includes a first plurality of reconfigurable logic elements and first
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`input/output circuitry; (b) a second reconfigurable logic device that includes a second plurality of
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`reconfigurable logic elements and second input/output circuitry; (c) a first clock signal for clocking
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`the first plurality ofreconfigurable logic elements; ((1) a second clock signal for clocking the second
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`plurality ofreconfigurable logic elements; and (e) at least one signal routing clock signal for clocking
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`Frederic keblewski et al. - US. Application No. 09/404,920
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`the first input/output circuitry and the second input/output circuitry. Moreover, claim 23 recites that
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`the signal routing clock signal is independent of the first clock signal and the second clock signal.
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`In rejecting previous claim 1, the Office relied on column 25, line 30 et seq. ofTrimberger as
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`allegedly disclosing independent clocking features similar to those recited in claim 23. This portion
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`of Trimberger relates to a sequencer that sequences through microcycles. Applicants respectfully
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`submit that nothing in this portion ofTrimberger teaches or suggests the reconfigurable logic device,
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`clocking signal, and independent signal routing clock signal features and structures in the manner
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`recited in claim 23.
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`With respect to claims 24 and 25, Applicants further submit that nothing in Trimberger
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`teaches or suggests the arrangement of claim 23 wherein the first and/or second reconfigurable logic
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`devices are field programmable gate arrays.
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`Regarding claim 27, Applicants respectfully submit that Trimberger does not teach or suggest
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`use of two different signal routing clock signals in the arrangement of claim 23. Furthermore,
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`Applicants submit that nothing in Trimberger teaches or suggests the inclusion of an interconnect
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`device between the two reconfigurable logic elements wherein two portions of the interconnect
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`device are clocked by different signal routing clock signals as recited in claim 28.
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`With respect to claims 32-34, Applicants respectfully submit that nothing in Trimberger
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`teaches or suggests a bi-directional data transfer connection situated between a reconfigurable logic
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`device and an interconnect device, wherein the bi-directional data transfer connection provides
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`simultaneous bi-directional data transfer via a single wire or trace as recited in these claims.
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`Additionally, nothing in Trimberger teaches or suggests the additional detection logic features recited
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`in claims 33 and 34.
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`I
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`,
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`Frederickeblewski et a]. — US. Application No. 09/404,920
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`Applicants further submit that Trimberger does not teach or suggest the asynchronous signal
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`transfer aspects in structures as recited in claims 30, 36, 37, and 39.
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`In View of the foregoing, Applicants respectfully submit that claims 10-16 and 23-39
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`patentably distinguish from Trimberger. Withdrawal ofthis rejection and allowance ofthese claims
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`are earnestly solicited.
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`III.
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`CONCLUSION
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`If any additional fees are required, such as fees under 37 CPR. §§ 1.16 or 1.17, or if an
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`extension oftime is necessary that is not accounted for in the papers filed with this Amendment, the
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`Commissioner is authorized to debit our Deposit Account No. 19-0733 for any necessary fees,
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`including any necessary extension fees. Any overpayment also can be credited to Deposit Account
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`No. 19-0733.
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`All rejections having been addressed, Applicants respectfully submit that the instant
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`application is in condition for immediate allowance and respectfully solicit prompt notification ofthe
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`same.
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`Respectfillly Submitted,
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` William F. Rauchhol
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`Registration No. 34,7 1
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`BANNER & WITCOFF, LTD.
`1001 G Street, NW, 11th Floor
`Washington, DC. 20001
`(202) 824-3000 (Telephone)
`(202) 824-3001 (Facsimile)
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`Dated: July 10, 2003
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