Filed on behalf of Intellectual Ventures Management
`By:
`Lori A. Gordon
`Robert Green Sterne
`
`Sterne, Kessler, Goldstein & Fox PLLC
`
`1100 New York Avenue, NW
`Washington, D.C.
`Tel: (202) 371-2600
`Fax: (202) 371-2540
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE TI-IE PATENT TRIAL
`
`AND APPEAL BOARD
`
`PETITION FOR INTER PAR TES REVIEW
`
`OF U.S. PATENT NG. 7,994,609
`
`

`
`Inter partes review of United States Patent No. 7,994,609 to Quinn, titled
`
`“Shielding for Integrated Capacitors” (hereinafter “the ‘609 Patent”) is hereby
`
`requested. The ‘609 Patent is provided as IVM 1001. The petition for inter partes
`
`review is brought on behalf of Intellectual Ventures Management, LLC
`
`(“Intellectual Ventures Management”).
`
`I.
`
`Grounds for Standing (37 C.F.R. § 42.104(a))
`
`It is certified by the undersigned and the Petitioner, Intellectual Ventures
`
`Management, that the ‘609 Patent is available for inter partes review. The ‘609
`
`Patent was issued on August 9, 2011 more than nine months prior to the filing date
`
`of the present petition and is not currently involved in a post grant review
`
`proceeding.
`
`It is certified by the Petitioner, Intellectual Ventures Management, that the
`
`Petitioner is not estopped from requesting an inter partes review challenging
`
`claims 1-19 of the ‘609 Patent on the grounds identified herein.
`
`II.
`
`Identification of Cleallenge (37 C.F.R. § 42.104(b))
`
`A.
`
`Claim Construction
`
`The terms in claims 1-19 are to be given their broadest reasonable
`
`interpretation, as understood by one of ordinary skill in the art and consistent with
`
`the disclosure.
`
`

`
`B.
`
`Background
`
`The ‘609 Patent relates to shielding for integrated capacitors. The ‘609
`
`Patent was filed on November 21, 2008 as Application No. 12/276,289 (“the ‘289
`
`application” or “the ‘609 application”). The ‘289 Application was filed with two
`
`independent claims —prosecution claim 1 and prosecution claim 19.
`
`IVM 1003.
`
`During prosecution, the Examiner rejected prosecution claim 1 as being anticipated
`
`by U.S. Patent No. 7,259,956 to Fong, et al.
`
`IVM 1004.
`
`In response, the Patent
`
`Owner amended original prosecution claim 1
`
`to incorporate the limitations of
`
`allowable dependent claim 5, thus acquiescing that limitations in prosecution claim
`
`1 were known in the art.1 IVM 1005. In the same response, dependent prosecution
`
`claim 6 was amended to include the limitations of prosecution claims 1 and 5. The
`
`subject matter of allegedly patentable dependent claims 5 and 6 is directed to the
`
`addition of a reference shield to a capacitor structure. As will be demonstrated
`
`herein, adding a reference shield to a capacitor structure was well known in the art
`
`prior to the filing date of the ‘609 patent.
`
`Amended prosecution claim 1 issued as independent claim 1 and amended
`
`prosecution claim 6 issued as independent claim 13.
`
`Issued independent claims 1
`
`and 13 share identical limitations ([A]—[C]).
`
`Independent claim 13 includes an
`
`additional limitation [D] related to the structure of the reference shield.
`
`1 The limitations from prosecution claim 1 correspond to limitations [A] and [B] in issued
`claims 1 and 13 and prosecution claim 5 corresponds to limitation [C].
`
`-2-
`
`

`
`Claim 1
`
`Claim 13
`
`[P] A capacitor in an integrated circuit
`("IC") comprising:
`
`A capacitor in an integrated circuit
`("IC") comprising:
`
`[A]
`
`a core capacitor portion having a
`first plurality of conductive elements
`electrically connected to and forming
`a first part of a first node of the
`capacitor
`formed
`in
`a
`first
`conductive layer of the IC and a
`second
`plurality
`of
`conductive
`elements electrically connected to
`and forming a first part of a second
`node of the capacitor formed in the
`first
`conductive
`layer,
`the
`first
`plurality of conductive
`elements
`alternating with the second plurality
`of conductive elements in the first
`
`third
`a
`and
`layer,
`conductive
`elements
`conductive
`plurality of
`electrically connected to and forming
`a second part of the first node
`formed in a second conductive layer
`adjacent to the first conductive layer,
`at
`least portions of some of the
`second
`plurality
`of
`conductive
`elements overlying and vertically
`coupling to at least portions of some
`of the third plurality of conductive
`elements;
`
`a core capacitor portion having a
`first plurality of conductive elements
`electrically connected to and forming
`a first part of a first node of the
`capacitor
`formed
`in
`a
`first
`conductive layer of the IC and a
`second
`plurality
`of
`conductive
`elements electrically connected to
`and forming a first part of a second
`node of the capacitor formed in the
`first
`conductive
`layer,
`the
`first
`plurality of conductive
`elements
`alternating with the second plurality
`of conductive elements in the first
`
`third
`a
`and
`layer,
`conductive
`elements
`plurality of conductive
`electrically connected to and forming
`a second part of the first node
`formed in a second conductive layer
`adjacent to the first conductive layer,
`at
`least portions of some of the
`second
`plurality
`of
`conductive
`elements overlying and vertically
`coupling to at least portions of some
`of the third plurality of conductive
`elements;
`
`' [B]
`
`a shield capacitor portion having
`fourth plurality of conductive
`a
`elements formed in at least the first
`
`a shield capacitor portion having
`fourth plurality of conductive
`a
`elements formed in at least the first
`
`the
`conductive layer of the IC,
`second conductive layer of the IC, a
`third conductive layer of the IC, and
`a fourth conductive layer of the IC,
`the first conductive layer and the
`second conductive layer each being
`
`the
`IC,
`the
`conductive layer of
`second conductive layer of the 1C, a
`E third conductive layer of the IC, and
`a fourth conductive layer of the IC,
`the first conductive layer and the
`second conductive layer each being
`
`

`
`between the third conductive layer
`and the fourth conductive layer, the
`shield
`capacitor
`portion
`being
`electrically connected to and forming
`a second part of the second node of
`the capacitor and surrounding the
`first plurality of conductive elements
`and the third plurality of conductive
`elements; and
`
`between the third conductive layer
`and the fourth conductive layer, the
`shield
`capacitor
`portion
`being
`electrically connected to and forming
`a second part of the second node of
`the capacitor and surrounding the
`first plurality of conductive elements
`and the third plurality of conductive
`elements; and
`
`[C]
`
`a reference shield electrically
`connected to a reference node of the
`
`shield electrically I
`a reference
`connected to a reference node of the
`
`IC other than the second node of the
`
`IC other than the second node of the
`
`capacitor
`shield
`the
`capacitor,
`portion being disposed between the
`reference
`shield
`and
`the
`core
`
`capacitor
`shield
`the
`capacitor,
`portion being disposed between the
`reference
`shield
`and
`the
`core
`
`capacitor portion.
`
`capacitor portion
`
`[D] T
`
`wherein the reference shield includes
`a substrate portion of a substrate of
`the IC, a first conductive curtain
`extending from the substrate portion,
`and a second conductive curtain
`
`extendingfrom the substrate portion.
`
`The following annotated figures
`
`from the ‘609 patent
`
`illustrate the
`
`relationship between the limitations recited in independent claims 1 and 13.
`
`
`
`'
`‘214
`" 9‘ i 5')‘ t:onclucti"e layer
`
`

`
`515* Ph1Ta]it'>'
`0f 5‘1€mE1115
`
`second plurality
`of elements
`
`
`
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`gra
`
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`32
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`83
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`J
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`Tl
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`2'51
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`.
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`is
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`l
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`‘
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`or
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`
`7
`
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`N9 K
`22‘
`
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`FIG. 23
`
`‘
`
`224
`
`C.
`
`Citation of Prior Art
`
`As set forth herein and supported by the Declaration of Mr. Morgan Johnson
`
`(IVM 1002), claims 1-19 are rendered obvious by the following prior art references
`
`alone or in the combinations specified in the grounds of rejection below:
`
`c U.S. Patent No. 6,737,698 to Paul, et al, titled “Shielded Capacitor
`
`Structure” issued on May 18, 2004, over 4 years prior to the filing
`
`date of the ‘609 Patent (hereinafter “Paul”).
`
`IVM 1006. Thus, Paul
`
`qualifies as prior art under at least 35 U.S.C. § l02(b).
`
`- U.S. Patent No. 7,439,570 to Anthony,
`
`titled “Metal-Insulator-
`
`Metal-Capacitors,” issued on October 21, 2008, prior to the filing date
`
`of the ‘609 Patent.
`
`IVM 1007. Thus, Anthony qualifies as prior art
`
`under at least 35 U.S.C. § 102(a).
`
`s U.S. Patent No. 7,286,071 to Hsueh, et al,
`
`titled “System for
`
`Displaying Im_ages,” issued on October 23, 2007, more than one year
`
`-5-
`
`

`
`prior to the filing date of the ‘609 Patent.
`
`IVM 1008. Thus, Hsueh
`
`qualifies as prior art under at least 35 U.S.C. § 102(b).
`
`6 U.S. Patent No. 6,903,918 to Brennan,
`
`titled “Shielded Planar
`
`Capacitor,” issued on June 7, 2005, more than three years prior to the
`
`filing date of the ‘609 Patent. IVM 1009. Thus, Brennan qualifies as
`
`prior art under at least 35 U.S.C. § 102(b).
`
`as U.S. Patent No. 7,238,981 to Marotta, titled “Metal-Ploy Integrated
`
`Capacitor Structure,” issued on July 3, 2008, prior to the filing date of
`
`the ‘609 Patent. IVM 1011. Thus, Marotta qualifies as préor art under
`
`at least 35 U.S.C. § lO2(a).
`
`a U.S. Patent Application Publication No. 2008/0125857 to Bi, titled
`
`“Multi-Finger Capacitor” published on June 5, 2008, prior to the filing
`
`date of the ‘609 Patent.
`
`IVM 1010. Thus, Bi also qualifies as prior
`
`art under at least 35 U.S.C. § lO2(a).
`
`D.
`
`Ground 1: Paul, et al Renders Claims 1, 3, 5, 6, and 10-12 of the
`‘609 Patent Cbvious Under 35 U.S.C. § 1
`
`1.
`
`Paul Renders Independent Claim 1 Obvious
`
`a)
`
`Paul Discloses a Capacitor in an Integrated Circuit ( 1[P] )
`
`Paul discloses a capacitor in an “integrated circuit.” IVM 1006, Abstract.
`
`(“In a capacitor formed in an integrated circuit, one or more shields are disposed
`
`

`
`around layers of conductive strips to shield the capacitor. The shields confine the
`
`electric fields between the limits of the shie1ds.”)(emphasis added).
`
`b)
`
`Faul Discloses a Core Capacitor Portion ( l[A] )
`
`The disclosure of Paul “relates to shielded capacitor structures in integrated
`
`circuits.” IVM 1006, 126-7. As explained by Paul, a “shielded capacitor structure
`
`of the present
`
`invention can take on many configurations in addition to the
`
`example SEOWI1 in FIG. 4.” IVM 1006, 3:60-63.
`
`In addition to the configurations
`
`explicitly disclosed by Paul, “Various combinations of the configurations are also
`
`possible.” IVM 1006, 3:66-67.
`
`FIG. A.1 of the Johnson Declaration annotates FIG. 8 of Paul to illustrate
`
`how the capacitor elements of Paul map to the limitations of claim l[A]. As
`
`illustrated in FIG. 8, a row of conductive strips is formed in METAL 3 layer of
`
`capacitor 800. IVM 1002, 1130. The row of conductive strips formed in METAL 3
`
`layer has a set of conductive strips 804 connected to a first node of the capacitor
`
`(node B) and a set of conductive strips 806 connected to a second node of the
`
`capacitor (node A). IVM 1002, ‘i30.
`
`

`
`\ core
`
`c.a:pacitor
`
`portion
`
`
`
`second plurality‘
`Of elements
`
`first plllffilllfj-’
`of elements
`
`._._._!
`
`I i i
`
`"
`
`
`
`‘IE (
`
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`
`i
`
`
`
`"73- 3
`1/a’i"0t"3ted)
`
`third plurality
`of elements
`
`FIG. A.1 of the Johnson Declaration
`
`The METAL 3 layer of Paul is equivalent to the ‘first conductive layer of
`
`the IC” recited in independent claim 1. The set of conductive strips 806 in
`
`METAL 3 layer is equivalent
`
`to the “first plurality of conductive elements
`
`electrically connected to and forming a first part of a first node of the capacitor
`
`formed in a first conductive layer of the IC” recited in independent claim 1. The
`
`set of conductive strips 804 in METAL 3 layer is equivalent to the “second
`
`plurality of conductive elements electrically connected to and forming a first part
`
`of a second node of the capacitor formed in the first conductive layer” recited in
`
`independent claim 1. As illustrated in FIG. 8 of Paul, the conductive strips 804
`
`and 806 alternate. IVM 1002, ‘I30. Thus, Paul further discloses “the first plurality
`
`ofconductive elements alternating with the second plurality ofconductive elements
`
`in the first conductive layer” recited in independent claims 1 and 13.
`
`

`
`The METAL 2 layer of FIG. 8 includes a second row of conductive strips.
`
`IVM 1006, FIG. 8. The second row includes a set of conductive strips 806
`
`connected to node B.
`
`IVM 1002, ‘I31. One or more of the conductive strips 804
`
`in METAL 3 layer connected to node A overlay and vertically couple to
`
`conductive strips in the set of conductive strips connected to node B in l\/ETAL 2
`
`layer.
`
`IVM 1002,
`
`‘.131. Thus, Paul discloses “a third plurality of conductive
`
`elements electrically connected to and forming a second part of the first node
`
`formed in a second conductive layer adjacent to the first conductive layer, at least
`
`portions of some of the second plurality of conductive elements overlying and
`
`vertically coupling to at least portions of some of the third plurality of conductive
`
`elements” recited in independent claim 1.
`
`c)
`
`Paul Discloses a Shield Capacitor Portion.
`
`( 1[B] )
`
`Paul discloses a capacitor shield portion that “confine[s] the electric fields
`
`from node A to node B
`
`within the limits of the [top and bottom] shields 408 and
`
`410.” IVM 1006, 3:34-36. The capacitor 800 depicted in FIG. 8 of Paul has a side
`
`shield 812 in addition to the top shield 808 and the bottom shield 810. IVM 1006,
`
`4:26-28.
`
`In Paul, “a side shield could be formed on both sides of the capacitor
`
`800.” IVM 1006, 4:33-35. FIG. 8 of Paul has been edited as Sl’10W’é’l in FIG. A.2 of
`
`the Johnson Declaration (reproduced below) to illustrate the modification of
`
`capacitor 800 to include a side shield on both sides of the capacitor.
`
`

`
`ma.‘
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`
`FIG. 8 (edited)
`
`FIG. A.2 of the Johnson Declaration
`
`“The side shield 812 is formed by conductive strips 804 formed on the
`
`METAL l, 2, and 3 layers and connected to node A.” IVM 1006, 4:28-30. The
`
`top shield and bottom shield of Paul may also be comprised of conductive strips.
`
`IVM I006, 4:20-25. The side shield portion of Paul therefore includes a plurality
`
`of conductive elements in each of the lst layer, 2101 layer, 3rd layer, and 4th layer.
`
`Paul further discloses that the top shield (e.g., top shield 808 of FIG. 8) and bottom
`
`shield (e.g., bottom shield 810 of FIG. 8) may be connected to the same node such
`
`as node A.
`
`IVM 1006, 4:56-64. FIG. A.3 of the Johnson Declaration further
`
`modifies FIG. 8 to illustrate bottom shield 810 coupled to node A.
`
`-10-
`
`

`
`shield capacitor
`/ portion
`, . . . . . -..H
`ii
`- _ ‘gm core capacitor
`
`I-76.8
`
`
`
`fourth plurality
`of elements
`
`(edited and annotated)
`
`FIG. A.3 of the Johnson Declaration
`
`Paul discloses “a shield capacitor portion having a fourth plurality of
`
`conductive elements formed in at least the first conductive layer of the [C the
`
`second conductive layer of the [C a third conductive layer of the IC, and a fourth
`
`conductive layer ofthe IC. As illustrated in FIG. 8 of Paul, Paul also discloses “the
`
`first conductive layer and the second conductive layer each being between the
`
`7
`third conductive layer and the fourth conductive layer.’ As discussed above, the
`
`top shield and bottom shield of Paul could be connected to node A. Téerefore,
`
`Paul also discloses “shield capacitor portion being electrically connected to and
`
`forming a second part of the second node of the capacitor.” The shield portion of
`
`Paul surrounds “the first plurality of conductive elements and the third plurality of
`
`conductive elements.”
`
`-11-
`
`

`
`d)
`
`Paul Discloses a Reference Shield. ( 1[C] )
`
`In FIG. 13, Paul discloses an embodiment of a capacitor 1300 “where the top
`
`and bottom shields 1308 and 1310 are connected to a third node, shown in this
`
`example as a reference Voltage (e.g., ground) rather than to nodes A or B.” IVM
`
`1006, 4:61-64. Paul further discloses that “one or more shields are disposed
`
`around layers of conductive strips to shield the capacitor.” IVM 1006, Abstract.
`
`FIG. A.4 of the Johnson Declaration edits FIG. 13 of Paul to depict the core
`
`capacitor portion and shield capacitor portion of FIG. A.3 combined with the
`
`reference shield depicted in FIG. 13 of Paul. Specifically, the capacitor core has
`
`been replaced with a capacitor having a top shield, a bottom shield, and side
`
`shields on both sides of the capacitor.
`
`reference shield
`
`shield capacitor
`portion\
`$5‘.
`
`: _
`
`_
`
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`
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`
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`
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`
`IG, 13 (edited and annotated)
`
`FiG. A.4 of the Johnson Declaration
`
`-12-
`
`

`
`As discussed above, the reference shield 1308 of Paul is “connected to a
`
`third node, shown in this example as a reference voltage (e.g., ground) rather than
`
`to nodes A or B.” IVM 1006, 4:62-64. Thus, Paul discloses “a reference shield
`
`electrically connected to a reference node of the IC other than the second node of
`
`the capacitor” as recited in independent claim 1. FIG. A.4 above illustrates that
`
`the shield capacitor portion is between the reference shield 1308 and the core
`
`capacitor portion. Paul therefore also discloses “the shield capacitor portion being
`
`disposed between the reference shield and the core capacitor portion” recited in
`
`independent claim 1.
`
`e)
`
`Conclusiore
`
`The various configurations of Paul disclose each and every limitation of
`
`claim 1.
`
`IVM 1002,
`
`‘T|36.
`
`Paul does not explicitly disclose each limitation
`
`integrated into a single capacitor
`
`structure. As explained above, “various
`
`combinations of configurations [in Paul] are also possible.” IVM 1006, 3:64-67.
`
`A person of ordinary skill in the art could combine the configurations of Paul as
`
`suggested by Paul according to known methods to yield predictable results.
`
`IVM
`
`1002, ‘[136. A chip designer of ordinary skill desiring the benefits of a capacitive
`
`element immediately coupled to one or more active elements on the die would, in
`
`the normal course of layout, have tended toward a symmetrical configuration as
`
`illustrated in FIG. A.3 of the Johnson Declaration.
`
`IVM 1002, ‘J37. The manifold
`
`-13-
`
`

`
`benefits of physical structures that are symmetrical relate to chip fabrication
`
`masking, additive and subtractive processes as well as electrical performance.
`
`IVM 1002, 113 7. When die area allows, passive components such as capacitors and
`
`conductive elements such as interconnects can be advantageously drawn with
`
`symmetrical areas and volumes so as to achieve relatively constant ratios of
`
`conductors to dielectrics.
`
`IVM 1002, 1137. This approach minimizes electrical
`
`discontinuities associated with sudden changes in conductor (net) cross section
`
`and/or fluctuations in dielectric-to-conductor spacing.
`
`IVM 1002, ‘.137. Attention
`
`to this level of detail can,
`
`in certain chip fabrication sequences, reduce the
`
`probability of process
`
`induced defects and potentially increase conductor
`
`bandwidth. IVM 1002, ‘I37. For these reasons, Paul renders claim 1 obvious.
`
`2.
`
`Paul Renders Dependent Claim 3 Obvious Under 35 US. C. § 103.
`
`Claim 3 limits claim 1 by requiring that the shield capacitor portion of claim
`
`1 includes “a first node shield plate formed in the third conductive layer” and “a
`
`second node shield plate formed in the fourth conductive layer.”
`
`The
`
`configurations of Paul when combined disclose this limitation of claim 3.
`
`As disclosed above, Paul discloses a shield capacitor portion that “confine[s]
`
`the electric fields from node A to node B
`
`within the limits of the [top and
`
`bottom] shields 408 and 410.” IVM 1006, 3:34-36.
`
`The “first shield 4082 [is]
`
`2 The first shield is labeled 808 in edited and annotated FIG. 13.
`
`-14-
`
`

`
`formed in the METAL 4 layer above the conductive strips,” and the “second shield
`
`4103 is formed in the METAL 1 layer below the conductive strips.” IVM 1006,
`
`3:25-31. “The shield 408 is formed by a solid conductive plate” and “shield 410 is
`
`formed by a solid conductive plate.” IVM 1006, 3:26-30. As would be appreciated
`
`by a person of ordinary skill in the art, the upper shield 808 is a “first node shield
`
`plate” and the bottom shield 810 is a “second node shield plate.” IVM 1002, ‘J39.
`
`Although the bottom shield is depicted as not extending beneath the side shield
`
`(curtain), a person of ordinary skill in the art would appreciate that the bottom
`
`shield could be extended. IVM 1002, “|39. The METAL 4 and METAL 1 layers of
`
`Paul are equivalent to the “third conductive layer” and the “fourth conductive
`
`layer,” respectively.
`
`Claim 3 further requires that the shield capacitor portion includes “a first
`
`conductive curtain extending from the first node shield plate to the second node
`
`shield plate” and “a second conductive curtain extendingfrom the first node shield
`
`plate to the second node shield plate.” The ‘609 patent provides a description of a
`
`conductive curtain as “conductive filaments formed in successive metal
`
`layers
`
`connected with conductive vias to form essentially a conductive sheet extending
`
`perpendicular to and from the plane of illustration.”
`
`IVM 1001, 1023-7. The
`
`configurations of Paul when combined disclose such a conductive curtain.
`
`3 The second shield is depicted as element 810 in FIG. 8.
`
`-15-
`
`

`
`Paul discloses that “a side shield could be formed on both sides of the
`
`capacitor.” IVM 1006, 4:33-35. The side shield of “is formed by conductive strips
`
`804 formed on the METAL l, 2, and 3 layers and connected to node A.” IVM
`
`1006, 4:28-30. “[T]he conductive strips 804 of the side shield 812 are connected to
`
`each other, and to the top shield 808, by vias 814.” IVM 1006, 4:30-32. FIG. B of
`
`the Johnson Declaration (reproduced below) annotates the capacitor of FIG. A.4 to
`
`illustrate how the limitations of claim 3 map to the capacitor of FIG. A.4.
`
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`2“ ‘Ede Shidd Plate He, 13 (edited and annotated)
`
`Figure B of the Johnson Declaration
`
`A person of ordinary skill in the art would have combined the configurations
`
`as suggested by Paul to obtain the capacitor of claim 3.
`
`IVM 1002,
`
`‘Q41.
`
`In
`
`addition to the enhanced isolation provided by FIG. B, the chip fabrication and
`
`electrical performance advantages of increased symmetry are further motivation
`
`-16-
`
`

`
`for the combination.
`
`IVM 1002, ‘J41. Thus, Paul suggests and thus renders
`
`obvious the limitations of claim 3 “wherein the shield capacitor portion includes a
`
`first node shield plate formed in the third conductive layer and a second node
`
`shield plate formed in the fourth conductive layer and further comprising a first
`
`conductive curtain extending from the first node shield plate to the second node
`
`shield plate and a second conductive curtain extending from the first node shield
`
`plate to the second node shield plate.”
`
`3.
`
`Paul Renders Dependent Claim 5 Obvious Under 35 U.S.C. §103.
`
`Claim 5 limits claim 1 by requiring that the reference node connected to the
`
`reference shield
`
`is a VDD node.” As explained by Paul,
`
`in a capacitor
`
`6‘
`
`configuration, “the top and bottom shields 1308 and 1310 are connected to a third
`
`node, shown in this example as a reference voltage (e.g., ground) rather than to
`
`nodes A or B.” IVM 1006, 4:61-64. Although Paul does not explicitly disclose
`
`VDD as an exemplary reference Voltage, it would have been a routine and obvious
`
`design choice to use VDD as the reference node.
`
`IVM 1002,
`
`‘,[43. The chip
`
`designer, depending on surrounding adjacent available structures, voltages and
`
`circuit requirements, simply would be motivated, in an ordinary and inevitable
`
`way, to see VDD as one of the available layout and/or electrical tools or variables
`
`available to effectively implement the target circuit.
`
`IVM 1002, 1l43. “If a person
`
`of ordinary skill in the art can implement a predictable variation, § 103 likely bars
`
`-17-
`
`

`
`its patentability.” KSR, 550 U.S. at 417. Because a person of ordinary skill in the
`
`art would appreciate that any voltage could be used as the reference node, the
`
`choice of VDD as the reference node would have been obvious to a person of
`
`ordinary skill in the art. Thus, Paul renders claim 5 obvious.
`
`4.
`
`Paul Renders Dependent Claim 6 Obvious Under 35 US. C. §103.
`
`Claim 6 limits claim 1 by requiring that the reference node is “an analog
`
`ground node.” Paul discloses that the “top and bottom shields 1308 and 1310 are
`
`connected to a third node, shown in this example as reference voltage (e.g.,
`
`ground) rather than to nodes A or B.” (IVM 1006, 4:61-64) Accordingly, Paul
`
`discloses the limitation “wherein the reference node is an analog ground node.”
`
`5.
`
`Paul Renders Dependent Claim 10 Obvious Under 35 US. C. §103.
`
`As set forth in the claim chart below, Paul discloses the limitations of claim
`
`10. FIG. A.4 of the Johnson Declaration has been annotated to illustrate how
`
`elements of claim 10 map to the capacitor configuration of Paul.
`
`Claim 10
`
`U.S. Patent No. 6,737,698 to Paul, et al
`
`[P] The capacitor of claim 1,
`
`“The capacitor 400 is built using four layers of
`[A] Wllemlll tl1_e lllst Pllllallty
`metal, designated as METAL 1, METAL 2,
`of C0T1flUCl1Ve elements
`Compl1595 3 lllst Plllrallty METAL 3, and METAL 4... A second row of '
`Of C0l1ClUCtlVe Stllps
`conductive strips is formed in the METAL 3
`extending along 3 lllst
`layer. The second row of conductive strips
`dllectlolla
`also has first and second sets of conductive
`
`strips 404 and 406 connected to nodes A and
`B of the capacitor.” (IVM 1006, 3:11-22)
`
`As discussed above, METAL 3 is equivalent
`
`-13-
`
`

`
`to the first conductive layer and first
`conductive strips 406/806 in METAL 3 are
`equivalent to the first plurality of conductive
`strips.
`
`FIG. 1 of Paul illustrates that in this
`
`configuration the first plurality of conductive
`strips extend along a first direction.
`
`
`
`na. 1(Pr!or Art)
`
`[B]
`
`the second plurality of
`conductive elements
`
`comprises a second
`plurality of conductive
`strips extending along the
`first direction, and
`
`“The capacitor 400 is built using four layers of
`metal, designated as METAL 1, METAL 2,
`METAL 3, and METAL 4... A second row of
`conductive strips is formed in the METAL 3
`layer. The second row of conductive strips
`also has first and second sets of conductive
`
`strips 404 and 406 connected to nodes A and
`B of the capacitor.” (IVM 1006, 3:11-22)
`
`As discussed above, METAL 3 is equivalent
`to the first conductive layer and second
`conductive strips 404/804 in METAL 3 are
`equivalent to the second plurality of
`conductive strips.
`
`As illustrated in FIG. 1 above (and annotated
`FIG. A.4), the second plurality of conductive
`strips extend along the same direction as the
`first plurality.
`
`[C]
`
`the third plurality of
`conductive elements
`
`comprises a third plurality
`of conductive strips
`extending along the first
`direction.
`
`“The capacitor 400 is built using four layers of
`metal, designated as METAL 1, METAL 2,
`METAL 3, and METAL 4. Formed in the
`2 layer is a first row of conductive
`strips. A first set of conductive strips 404 is
`connected to node A of the capacitor.” (IVM
`
`-19-
`
`

`
`1006, 3:11-15)
`
`As discussed above, METAL 2 is equivalent
`to the second conductive layer and first
`conductive strips 406/806 in METAL 2 are
`equivalent to the third plurality of conductive
`strips.
`
`As illustrated in FIG. 1 above (and annotated
`FIG. A.4), the third plurality of conductive
`strips extend along the same direction as the
`first plurality.
`
`l5‘ph1ralit}* of elements
`= 13: plurality of
`conductive strips
`
`2“ pluralit}-' of elements
`= 2“ plmrality of
`condu«:t'tve strips
`
`reference
`shield
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`‘ >73
`
`{edited and annotated)
`
`Figure A.4 of the Johnson Declaration (Annotated)
`
`For the reasons above, Paul renders claim 10 obvious.
`
`-20-
`
`

`
`6.
`
`Paul Renders Dependent Claim 11 Obvious Under 35 U.S. C. §103.
`
`As set forth in the claim chart below, Paul discloses the limitations of claim
`
`11. FIG. A.4 of the Johnson Declaration (above) has been annotated to illustrate
`
`how elements of claim 11 map to the capacitor configuration of Paul.
`
`E
`
`Claim 11
`
`U.S. Patent No. 6,737,698 to Paul, et al
`
`[P] The capacitor of claim 10
`
`[A]
`
`iiurthel’ eempfising 3
`fourth plurallty of
`e0T1duet1Ve Strlps
`eleetrieally eendeeted T0
`and fermmg 3 third Part Of
`the Seeend nede extending
`along the first direction
`an_d altemaimg Wlth the
`thud phirahty _°f _
`Conductwe Smp,S In the
`Second conductwe layer‘
`
`“The capacitor 400 is built using four layers
`of metal, designated as METAL 1, METAL
`2, METAL 3, and METAL 4. Formed in the
`METAL 2 layer is a first row of conductive
`strips. A first set of conductive strips 404 is
`connected to node A of the capacitor.” (IVM
`1006, 3 :1 1-15)
`As discussed above, METAL 2 is equivalent
`to the second conductive layer and second
`-. conductive strips 404/804 in METAL 2 are
`equivalent to the fourth plurality of
`conductive strips. Node A of Paul is
`equivalent to the second node. Therefore,
`second conductive strips 404/804 in METAL
`2 form a third part of the second node.
`
`As illustrated in FIG. 1 above (and annotated
`FIG. A.4 above), the fourth plurality of
`conductive strips alternate with the third
`plurality of conductive strips and extend
`along the same direction as the first plurality.
`
`Accordingly, Paul renders claim 11 obvious.
`
`7.
`
`Paul Renders Dependent Claim 12 Obvious Under 35 US. C. §103.
`
`Claim 12 limits claim 1 by adding “a second reference shield connected to a
`
`second reference node of the [C
`
`the reference shield being disposed between the
`
`-21-
`
`

`
`second reference shield and the shield capacitor portion.”
`
`Paul discloses the use of both a capacitor shield and a reference shield. Paul
`
`explains that the “shields of the present invention may take on numerous forms in
`
`addition to the examples described above.”
`
`IVM 1006, 4:56-57. For example,
`
`Paul discloses that “one or more shields are disposed around layers of conductive
`
`strips to shield the capacitor.” IVM 1006, Abstract. Based on these disclosures in
`
`Paul, a person of ordinary skill
`
`in the art could combine the capacitor
`
`configurations disclosed by Paul to add a second reference shield above the first
`
`reference shield, as illustrated in FIG. C of the Johnson Declaration (reproduced
`
`below). IVM 1002, T145. There are certain circuit designs where fluctuation in the
`
`capacitive values caused by relatively small discontinuities in the shielding of the
`
`integrated capacitor would degrade the performance of the circuit either
`
`continuously or intermittently depending on voltage fluctuation, noise source
`
`strength, frequency and its periodicity. IVM 1002, ‘J45. In these cases, a person of
`
`ordinary skill in the art of chip design would be motivated to, in the normal course
`
`of layout and in certain more demanding cases use a full 3D field solver to
`
`simulate the local structures which could indicate the need to invoke the “third
`
`node” approach manifested in FIG. C. IVM 1002, ‘E45.
`
`-22-
`
`

`
`12.25
`
`
`fl reference shield
`
`second
`
`reference
`shield
`
`3 A 5'
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`FIG. $3 (edited and annotated
`
`Figure C of the Johnson Declaration
`
`E. Ground 2: Paul in View of Anthony Renders Claims 2, I3, and 14-17
`of the ‘609 Patent Obvious.
`
`1.
`
`Paul and Anthony Renders Claim 2 Obvious Under 35 US. C. §103.
`
`Claim 2 further limits claim 1 by requiring “wherein the third conductive
`
`layer is a metal layer of the IC and the fourth conductive layer is a poly layer of
`
`the [C the shield capacitor portion including a first node shieldplateformed in the
`
`metal layerfrom a plurality ofmetal stripes and a second node shieldplateformed
`
`in the poly layer.”
`
`The METAL 4 layer of Paul is equivalent to the recited third conductive
`
`layer of claim 1. The top shield of Paul (element 808) is formed in METAL 4.
`
`-23-
`
`

`
`Thus, Paul discloses that the third conductive layer is a metal layer ofthe IC.
`
`Paul further explains that the top shield may be comprised of conductive
`
`strips 704.
`
`IVM 1006, 4:20-23 (“FIG. 7 shows an example of a capacitor 700