US007439570B2
`
`(12) United States Patent
`Anthony
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,439,570 B2
`Oct. 21, 2008
`
`(54) METAL-INSULATOR-METAL CAPACITORS
`
`(75)
`
`Inventor: Michael P. Anthony, Andover, MA (US)
`
`6,265,764 B1
`6,266,226 B1 *
`5553191 B1
`6,737,698 B1
`
`7/2001 Kinsman
`7/2001 Hayashi .................... .. 361/303
`5/2003 Casey Gt 31-
`5/2004 Paul et al.
`
`(73) Assignee: Kenet, Inc., Woburn, MA (US)
`( * ) Notice:
`Subject. to any disclaimer, the term ofthis
`Patent 15 extended er aeleetee under 35
`U~S~C~ 1540’) by 0 days
`
`,
`
`,
`
`20057/b012425’3§%
`2006/0061935 A1
`2006/0197133 A1
`
`Eamauehllet 31'
`ones e a .
`et a1.
`3/2006 Schultz et al.
`9/2006 Jung etal.
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`(21) App1.N0.: 11/309,300
`.
`Flledi
`
`J11I1- 1, 2007
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`(22)
`
`JP
`wo
`
`FOREIGN PATENT DOCUMENTS
`2005 108874
`4/2005
`wo 96/27907
`9/1996
`
`(65)
`
`Prior Publication Data
`
`* Cited by examiner
`
`US 2007/0278551 A1
`
`Dec. 6, 2007
`
`Related U.S. Application Data
`
`,
`.
`Primary Examinar—DaVid Vu
`(74) Attorney, Agent, or Firm—Hamilton, Brook, Smith &
`ReYI101dS, P-C~
`
`(60) Provisional application No. 60/810,257, filed on Jun.
`2, 2006.
`
`(57)
`
`ABSTRACT
`
`(51)
`
`Int. Cl.
`(2006.01)
`H01L 27/108
`(52) U.S. C1.
`..................................... .. 257/309; 438/239
`(58) Field of Classification Search ............... .. 438/239,
`438/393; 257/300, 308, 309, 532,535, 659,
`257/1321.008, E27048
`See application file for Complete Search history.
`_
`References Clted
`U.S. PATENT DOCUMENTS
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`(56)
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`An interdigitated Metal-Insulator-Metal (MIM) capacitor
`provides self-shielding and accurate capacitance ratios with
`small capacitance values. The MIM capacitor includes two
`terrninals that extend to a plurality of interdigitated fingers
`separated by an Insulator. Metal plates eeeupy layers above
`and below the fingers and connect to fingers of.one.terminal.
`As a result, the .MlM capacitor provides self-shielding to one
`terminal.Additional shielding may be employed by a series of
`additional shielding layers that are isolated from the capaci-
`tor. The self-shielding and additional shielding may also be
`implemented at an array of MIM capacitors.
`
`6,066,537 A
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`Oct. 21, 2008
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`
`1
`METAL-INSULATOR-METAL CAPACITORS
`
`2
`SUMMARY OF THE INVENTION
`
`US 7,439,570 B2
`
`RELATED APPLICATION
`
`This application claims the benefit of U.S. Provisional
`Patent Application No. 60/810,257, filed Jun. 2, 2006, the
`entire teachings of which are incorporated herein by refer-
`ence.
`
`BACKGROUND OF THE INVENTION
`
`Metal-insulator-metal (MIM) capacitors are widely used in
`hybrid and monolithic electronic circuits. Such capacitors
`can be vertical, with horizontal metal plates; lateral, with
`vertical plates; or mixed, employing capacitance between
`both vertically-separated and horizontally-separated plates.
`In some applications, special insulator layers are provided for
`optimized capacitor performance. In others, existing dielec-
`trics are used, such as the inter-metal dielectrics which sepa-
`rate metal interconnections. The capacitors discussed below
`employ inter-metal dielectrics of this type, and are of mixed
`orientation.
`
`Interdigitated MIM capacitor structures similar to the
`capacitor 100 depicted in FIG. 1A have been used extensively
`in both semiconductor and hybrid processes. They provide
`reasonably well-controlled capacitance, with acceptable
`parasitic elements (resistance, inductance) for many applica-
`tions, while employing only process elements already present
`for other reasons: metal for interconnects and dielectrics for
`
`substrate and/or insulation. Capacitors of this type are often
`described as being composed of a number of ‘fingers.’ In the
`capacitor 100 illustrated in FIG. 1A, capacitor terminal 1 is
`connected to four fingers, and capacitor terminal 2 is con-
`nected to three fingers. A cross-section of the capacitor of
`FIG. 1A along line A-A‘ is shown in FIG. 1B, with fingers
`connected to each of the two terminals identified as 1 and 2
`
`respectively. Capacitance between terminals 1 and 2 in this
`structure is primarily horizontal, with fringing-field compo-
`nents extending into the vertical dimension.
`Terminal 2 ofthe capacitor 100 has capacitance to terminal
`1 along both sides of each of its three fingers, along the length
`labeled ‘L.’ In addition, finger-ends such as 3, 4, and 5 con-
`tribute some capacitance. If this capacitor design is general-
`ized to more or fewer fingers, while maintaining one more
`finger for terminal 1 than for terminal 2, we can write for the
`total capacitance between terminals 1 and 2:
`C:NFLC0+NFC3+2C4+(Np—1)C5
`
`(Equation 1)
`
`where NF is the number ofterminal-2 fingers; CO is the capaci-
`tance per unit length per finger; C3 is the capacitance per
`terminal-2 finger-end like 3; C4 is the capacitance per outside
`corner like 4; and C5 is the capacitance per terminal-1 finger-
`end like 5. In the example illustrated in FIG. 1, NF:3.
`The first term in Equation 1 (NFLCO) is proportional to
`both the number of fingers NF and the length L, both ofwhich
`are convenient design parameters. The remaining terms
`embody the finger-end effects enumerated, and are less sub-
`ject to control of the designer, but rather depend more on
`process details. Equation 1 can be simplified by re-combining
`the second through fourth terms:
`C:NFLC0+NFC1+C2
`
`(Equation 2)
`
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`A. Recognition of Problems with the Prior Art
`One desirable property of capacitors in circuit design is
`matching between nominally-identical capacitors. If capaci-
`tors with well-matched values can be reliably fabricated, then
`many circuits which depend on capacitance ratios can be
`constructed using arrays of ‘unit’ matched capacitors.
`Capacitors like that in FIG. 1A are suited to this type of
`matching, in that both the capacitance-per-unit-length CO and
`the end-effects are generally quite repeatable within a given
`process batch. If the length L is much greater than the finger
`spacing, then the first term in Equation 2 dominates total
`capacitance, making C reasonably stable batch-to-batch as
`well.
`
`In many applications it is desirable to maximize the capaci-
`tance per unit area provided by MIM capacitors. In processes
`with more than one metal layer, the additional layers can be
`used to provide additional capacitance in various ways, gen-
`erally involving interdigitated structures like that of FIG. 1A,
`stacked one over another. Such multi-layer MIM capacitors
`can retain many of the matching properties just discussed.
`B. Summary of Preferred Embodiments of Invention
`The present invention relates to an interdigitated Metal-
`Insulator-Metal capacitor. In some embodiments, the inter-
`digitated capacitor comprises an odd number greater than two
`of parallel metal fingers formed in a single metal layer and
`separated by a dielectric. The odd-numbered fingers may be
`connected to a first electrical terminal ofthe capacitor, and the
`even-numbered fingers may be connected to a second elec-
`trical
`terminal of the capacitor. Continuous metal plates
`extend at least as far as the outermost fingers, occupying
`metal layers above and below the layer containing the fingers,
`and separated from the fingers by layers of dielectric, with the
`plates connected to the outermost fingers. As a result, the first
`terminal shields the second terminal at all sides, thereby
`providing self-shielding to the capacitor.
`In further embodiments, additional shielding may be pro-
`vided by layers above and below the capacitor. The shielding
`layers may be electrically isolated from the terminals and
`connected by a series of metal layers and vias encompassing
`the capacitor. The capacitor terminals may be configured in a
`number of ways to provide predictable capacitances.
`In still further embodiments, an array of capacitors may
`include a plurality of self-shielded MIM capacitors sharing a
`common terminal.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The foregoing will be apparent from the following more
`particular description of example embodiments of the inven-
`tion, as illustrated in the accompanying drawings in which
`like reference characters refer to the same parts throughout
`the different views. The drawings are not necessarily to scale,
`emphasis instead being placed upon illustrating embodi-
`ments of the present invention.
`FIG. 1A is a block diagram of a prior art interdigitated
`MIM capacitor.
`FIG. 1B is a cross-section diagram ofthe prior art capacitor
`of FIG. 1A.
`
`FIG. 2A is a block diagram of a self-shielded interdigitated
`MIM capacitor according to an embodiment of the present
`invention.
`
`where CO is again the capacitance per finger per unit length;
`Cl is a capacitance per finger, independent of finger length;
`and C2 is a fixed ‘offset’ capacitance, independent of both NF
`and L. (C2 may be either positive or negative.)
`
`FIG. 2B is a cross-section diagram of the capacitor of FIG.
`2A.
`
`65
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`FIG. 3A is a block diagram of a self-shielded capacitor
`with additional shielding layers.
`
`

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`US 7,439,570 B2
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`3
`FIG. 3B is a cross-section of the capacitor of FIG. 3A.
`FIG. 4 is a cross-section of a capacitor with increased
`spacing to the additional shielding layers.
`FIG. 5 is a block diagram of a capacitor with extended
`fingers.
`FIG. 6 is a block diagram of a capacitor with extended
`fingers.
`FIG. 7A is a block diagram of a capacitor array with com-
`mon inner-terrninal fingers.
`FIG. 7B is a cross-section ofa capacitor in the array of FIG.
`7A.
`
`FIG. 7C is an electrical schematic diagram ofthe capacitor
`array of FIG. 7A.
`FIG. 8A is a block diagram of an array terminating capaci-
`tor with terminated fingers at one end of a capacitor array.
`FIG. 8B is a block diagram of an array terminating capaci-
`tor with extended fingers at one end of a capacitor array.
`FIG. 9A is a block diagram of an array terminating capaci-
`tor with extended fingers at one end of a capacitor array, the
`extended fingers coupled to a common terminal.
`FIG. 9B is a block diagram of an array terminating capaci-
`tor at one end ofa capacitor array, the capacitor having fingers
`coupled to a common terminal.
`FIG. 9C is a block diagram of an array terminating capaci-
`tor at one end ofa capacitor array, the capacitor having fingers
`connected via a secondary finger extending perpendicular to
`the fingers.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`A description of preferred embodiments of the invention
`follows.
`
`It is increasingly desirable to minimize the power con-
`sumption of electronic circuits. One means ofreducing power
`consumption is to reduce the size of capacitors used in the
`circuits, thus representing signals with smaller charge quan-
`tities. In this case it is desirable to produce capacitors with
`very small values, while retaining good matching and well-
`controlled ratios. While the unit-capacitor matching method
`discussed above is well-suited to large capacitor values, it is
`less effective when the desired unit capacitor requires a small
`number of fingers and L approaching the process’ s minimum
`dimensions. In this case the end effects become more signifi-
`cant, resulting in poor matching,
`less-predictable capaci-
`tance, and greater overall capacitance variation batch-to-
`batch. MIM capacitor designs which provide very small
`capacitance values with good matching, well-controlled
`ratios, and small batch-to-batch variability would therefore
`be desirable.
`
`In many circuit designs it is desirable to minimize the
`so-called “parasitic” capacitance between capacitor termi-
`nals and other circuit nodes. Parasitic capacitance to circuit
`common (“groun ”) can cause increased circuit noise and
`reduced circuit speed. Parasitic capacitance to other circuit
`nodes can give rise to errors due to noise and un-intended
`signal coupling. It would therefore be desirable to provide a
`MIM capacitor design with minimized capacitance to ground
`and with shielding from other circuit nodes.
`Embodiments of the present
`invention provide MIM
`capacitors with each of the desirable properties just enumer-
`ated. The first feature of this invention provides near-elimi-
`nation of parasitic capacitance and near-perfect shielding at
`one capacitor terminal.
`This embodiment is explained with the aid ofFIGS. 2A and
`2B. Consider first the interdigitated MIM capacitor 200
`depicted in FIG. 2A. Here, first terminal 21 extends to a
`plurality of fingers 27, the outermost of which are extended
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`and wrapped around the lower corners of second terminal 22;
`these extensions are identified as 25 and 26 in FIG. 2A.
`
`Further, two additional layers ofmetal are used to form plates
`23 and 24, covering the hatched area in FIG. 2A. The cross-
`section along B-B‘ in FIG. 2B shows these two new metal
`plates 23, 24 more clearly. They are electrically connected to
`terminal 21 by vias, such as vias 29, either inside or outside
`the area shown.
`The effect of these new features is that terminal 21 sur-
`
`rounds terminal 22, including fingers 28, almost completely
`in both horizontal and vertical directions. Plates 23 and 24
`
`provide shielding in the vertical direction, and the outer fin-
`gers and other elements of terminal 21 provide horizontal
`shielding. Thus terminal 22 is provided with nearly-complete
`shielding from both ground and other circuit nodes: terminal
`22 has capacitance almost entirely to terminal 21, and almost
`no capacitance to any other circuit node. Only the external
`terminal 22 connection (extending downward beyond the
`main rectangular capacitor area in FIG. 2A) is un-shielded.
`This shielding of one capacitor plate (22) by the other (21) is
`here termed ‘self-shielding.’ In many applications, only one
`capacitorplate needs to have good shielding and low parasitic
`capacitance: the self-shielding design of FIGS. 2A and 2B
`satisfies these requirements.
`For a given area, the capacitor 200 of FIGS. 2A and 2B
`provides slightly higher capacitance than the capacitor 100 of
`FIGS. 1A and 1B, due to the added vertical-field contribution
`of plates 23 and 24 as well as the extended terminal-1 seg-
`ments 25 and 26. However, the dependence of capacitance on
`design parameters NF and L, as expressed in Equation 2,
`remains valid. The three capacitance coefiicients C0, C1 and
`C2 have different values due to the revised geometry.
`For applications in which capacitor terminal 21 must also
`be shielded, two additional metal layers can be used, as shown
`in FIGS. 3A and 3B, to provide the needed shielding. In FIG.
`3A, the entirety of FIG. 2A is repeated as capacitor 30. Ter-
`minals 31 and 32, corresponding to 21 and 22, and plates 33
`and 34, corresponding to 23 and 24, are identified. Capacitor
`30 is surrounded by a shield ‘wall’ 37, and covered top and
`bottom by shield plates 35 and 36. A cross section along line
`C-C‘, as shown in FIG. 3B, shows the structure ofthe ‘wall’ 37
`and shield plates 35 and 36 relative to the capacitor 30. The
`vertical ‘wall’ 37 is constructed of metal lines 39 in the three
`
`metal layers used by capacitor 30, plus rows ofvias such as 38
`connecting these lines and the top and bottom plates 35 and
`36. This wall is penetrated by only one metal layer, carrying
`the connections to terminals 31 and 32 which are visible in
`FIG. 3A.
`
`As an alternative to the use of a metal layer as shown in
`FIG. 3B (which may be needed for interconnect purposes) the
`bottom shield plate 36 can be implemented with a poly-
`silicon or diffusion layer. The minimum number of metal
`layers required to implement the fully-shielded capacitor of
`FIGS. 3A and 3B is thus four.
`
`Walls 37 and plates 35 and 36 provide effective shielding of
`terminal 31 from external circuit nodes. As a side effect,
`however, they add parasitic capacitance from terminal 31, and
`also a slight parasitic capacitance from terminal 32, to the
`shield, which is usually at ground potential. In contrast, the
`shielding of terminal 22 in FIGS. 2A and 2B is provided by
`terminal 21 itself (self-shielding) and adds no parasitic
`capacitance to terminal 22. Thus the added shielding for
`terminal 31 represents a compromise.
`If additional metal layers, together with their inter-metal
`dielectric layers, are available, this added parasitic capaci-
`tance can be reduced. FIG. 4 shows a cross section (analogous
`to FIG. 3B) of such a structure. The use, mentioned above, of
`
`

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`US 7,439,570 B2
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`5
`a diffused layer for the bottom shield plate 46 is also illus-
`trated in FIG. 4. As many metal layers as are available may be
`used in this way to minimize parasitic capacitance.
`The self-shielded capacitors ofFIGS. 2, 3, and 4 all have an
`‘inner’ terminal (such as 22) and an ‘outer’ terminal (such as
`21). These capacitors are inherently asymmetrical: the inner
`terminal is fully shielded by the outer terminal and has neg-
`ligible parasitic capacitance; the outer terminal is either un-
`shielded or may have explicit added shielding, which adds
`parasitic capacitance. In many applications this asymmetry is
`tolerable, and the near-zero-parasitic capacitance and near-
`perfect shielding of the inner terminal is valuable.
`The other desirable property identified above was the pro-
`vision of small-value capacitors with accurate matching and
`precise ratios. The improved interdigitated MIM capacitors
`of this invention can provide these features, as will be shown
`below.
`
`Considering again Equation 2, the first term (NFLCO) pro-
`vides ideal ratio capability. Capacitance depends linearly on
`the number of fingers NF, a discrete parameter, and on the
`finger length L, a continuous one. Thus if the other terms in
`Equation 2 were negligible, arbitrary capacitance ratios could
`be precisely realized, with minimum capacitance limited only
`by the process design rules. If only the last (C2) term in
`Equation 2 were negligible, then capacitors with accurate
`integer ratios could be realized by varying NF while keeping
`L constant. This capability is valuable in many applications,
`such as A/D converters where integer capacitance ratios are
`commonly used.
`In practice, this second condition (C2 negligible) can be
`very nearly met for a set of MIM capacitor structures approxi-
`mating the self-shielded design of FIG. 2A. Examples are
`shown in FIGS. 5 and 6. Note that the additional shielding
`shown in FIGS. 3 and 4 is omitted from FIGS. 5 and 6 for
`
`reasons of clarity, although it can be added to these structures
`if the extra shielding is needed.
`FIG. 5 depicts a capacitor 500 similar to that of FIG. 2A,
`with NF:3. A cross-section along D-D‘ is identical with that
`shown in FIG. 2B. However, the wrap-around extensions of
`the outer terrninal-21 fingers (25 and 26 in FIG. 2A) are
`omitted from the capacitor 500 in this embodiment. The top
`and bottom plates 58 end co-incidentally with the ends of the
`terminal-51 fingers, as indicated by the hatched area. The
`three fingers, 53, 54, and 55, of terminal 52 are extended by a
`length LEXT beyond the ends of the terrninal-51 fingers. LEXT
`is chosen to be greater than the length LF, which represents
`the maximum significant fringing of electric field beyond the
`end of the terminal-51 fingers and top and bottom plates.
`In this capacitor 500, each finger has an ‘internal’ end like
`56 and an ‘external’ end like 57. The capacitance contributed
`by these finger-ends is nearly identical for each finger,
`because the geometry of each finger is identical and because
`the terminal-52 fingers extend beyond LF. Since, in the deri-
`vation of Equation 2, C2 arose from finger-end effects which
`were not equal for all fingers, it can be seen that C2 for the
`design of FIG. 5 is negligible. In other words, for this design
`the capacitance has the form:
`C:NFLC0+NFC1
`
`(Equation 3)
`
`This capacitance has the desirable property, described
`above, of being proportional to NF with no offset. Thus
`capacitors as shown in FIG. 5 can be used to realize accurate
`integer ratios of capacitance among multiple capacitors.
`This structure has less-complete self-shielding than that of
`FIG. 2, due to the terminal-52 finger extensions and the lack
`of terminal-51 wrap-around segments like 25 and 26 in FIG.
`2A. For values of L significantly greater than minimum metal
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`dimensions, however, these are relatively minor effects, and
`may in many applications be rendered innocuous by addi-
`tional shielding (like that shown in FIGS. 3 and 4) or careful
`placement of surrounding circuitry.
`FIG. 6 depicts another capacitor 600 with similar proper-
`ties. Again, the layout is similar to that of FIG. 2A, and the
`cross-section E-E‘ may be identical to that in FIG. 2B. The
`wrap-around extensions ofterminal-21 fingers in FIG. 2A are
`omitted in FIG. 6, and the top and bottom plates 69 end
`co-incidentally with the ends of the terminal-61 fingers. As
`with FIG. 5, terminal-62 fingers 62, 66, and 67 extend by
`EXT
`L
`beyond the terrninal-61 fingers, with LEX2>LF. In con-
`trast to FIG. 5, the connection between the fingers ofterminal
`62 is made at the top of this capacitor by metal line 65. Also
`fingers 63 and 64, the inner fingers of terminal 61, are con-
`nected by vias such as 68 to the top and bottom plates, which
`are in mm connected to terminal 61. Outer terminal-61 fin-
`
`in order to assure
`
`gers are likewise supplied with vias,
`matched capacitance per finger.
`Although the geometry of the outer fingers of terminal 62
`differs from that of the inner ones, the terminal-62 finger-end
`capacitances in FIG. 6 are nearly identical. Consequently, as
`with FIG. 5, the total capacitance between terminals 61 and
`62 obeys Equation 3 to a very good approximation, thus
`providing accurate capacitance proportionality to NF. This
`structure also has less-perfect self-shielding than that of FIG.
`2. As with the FIG. 5 capacitor, if L is significantly greater
`than minimum metal dimensions, then the shielding loss is
`minor, and may be rendered innocuous by similar means.
`As with the capacitor designs of FIGS. 2, 3, and 4, those of
`FIGS. 5 and 6 (and of FIGS. 7, 8, and 9 below) can be
`generalized to any number of fingers.
`In many applications, multiple capacitors with a common
`terminal are required. When some but not all of such capaci-
`tors must have good matching or accurate ratios, the concepts
`embodied in FIGS. 2 through 6 can be applied to satisfy these
`requirements while also providing self-shielding. FIGS. 7A
`through 7C show the essential concepts of a multiple-capaci-
`tor array exhibiting this combination of features. Certain
`details are explained below with the aid of FIGS. 8 and 9.
`FIG. 7A shows an array 700 offour capacitors in plan view:
`capacitors 75 and 76 are shown completely, while capacitors
`77 and 78 are partially shown. The array 700 can be extended
`with additional capacitors, as discussed below. Terminal 72 is
`common to all four capacitors 75-77. It is made up of three
`fingers 72A through 72C, which extend through all four
`capacitors and may continue as indicated. The connection
`between the three fingers constituting terminal 72 is not
`shown in this figure, but is discussed below. FIG. 7C shows a
`schematic circuit diagram of the structure of the array 700.
`Capacitor 75 is representative ofthis design. A section F-F‘
`through it is shown in FIG. 7B: it can be seen that this section
`may be identical to that of FIG. 2B. FIGS. 71A through 71D
`and top and bottom-plates 73A, 73B are connected to termi-
`nal 71 of this capacitor by vias 74, while fingers 72A through
`72C constitute terminal 72. Terminal 71 is the outer terminal,
`and terminal 72 is the inner terminal, which is surrounded by
`terminal 71 and consequently well-shielded and with very
`low parasitic capacitance, like terminal 21 of FIG. 2. The
`length of capacitor 75 along its fingers is L75, and it has NF:3
`fingers. Capacitor 76 is identical in section to capacitor 75; it
`also has NF:3, and has length L76.
`Capacitors 75 and 76 (and all other capacitors in this array
`700) are separated by a gap of length LG. The fingers of inner
`terminal 72 continue through these gaps, but all outer-termi-
`nal metal is interrupted. The electric field between inner and
`outer terminals fringes into the gaps, causing an increase ALF
`
`

`
`US 7,439,570 B2
`
`7
`in effective electrical length beyond the physical lengths L75,
`L76 etc. ALF is a characteristic ofthe process and of the finger
`width, finger spacing and gap length used in the capacitor
`layout. LG is optimally the minimum metal spacing permitted
`in the process used to fabricate the capacitors. With finger
`spacing and LG both equal to the minimum permitted by the
`process, ALF is approximately equal to LG, and is well
`matched between different capacitors in the same circuit and
`independent of L and NF.
`Fingers 71B, 71C, and 71D ofthe outer terminal of capaci-
`tor 75 are connected to terminal 71 by vias, as indicated. With
`an identical via added to finger 71A, the small capacitance
`added by the vias is the same for each finger. This added
`capacitance canbe regarded as a slight further increase ALVin
`effective electrical length of the fingers.
`The combined effects of field-fringing in the gaps and the
`vias can be expressed as:
`LEFF:L+ALF«-I-ALV
`
`(Equation 4)
`
`where LFFF is the effective electrical length of a capacitor of
`physical length L.
`It can be seen that, with the effective length accounted for,
`capacitors 75 and 76 do not have any end effects of the types
`discussed above. Each terminal-72 finger continues from
`capacitor to capacitor with no irregularities. With no end
`effects, the capacitance of each such capacitor is given by:
`C:NFLEFF-C0
`(Equation 5)
`
`Capacitors of this type can be designed for precise discrete
`capacitance ratios by selecting NF. Capacitance per finger is
`selected by choosing L. Because AL is quite consistent for a
`given fabrication process, reliable ratio accuracy can also be
`obtained by employing different L values. This parameter,
`being continuous rather than discrete, allows non-integer
`capacitance ratios.
`With AL on the order of the minimum metal spacing, this
`design can provide extremely small capacitor values with
`good matching and ratios. As an example, in a typical CMOS
`process of the 0.18-micrometer generation, ratio accuracy of
`1% can typically be obtained with capacitors as small as 5
`femto Farads (fF).
`With the capacitor-array design of FIG. 7, the gaps such as
`70 slightly reduce the completeness of self-shielding of ter-
`minal 72 by outer terminals 71, 79, etc. However, because
`metal thickness in typical processes is greater than LG, this
`effect is very minor. An added shield like those discussed in
`connection with FIGS. 3 and 4, or even a partial shield of
`similar design covering only the gaps, can eliminate coupling
`from external signals while adding only negligible parasitic
`capacitance to terminal 72.
`Thus the capacitor-array design of FIG. 7 provides both the
`matching and ratio accuracy and the self-shielding benefits
`sought. As mentioned above, this design can be generalized to
`include one, two, or more capacitors providing these benefits.
`Multiple capacitor arrays similar to FIG. 7 but with differing
`numbers of fingers can be employed to provide groups of
`capacitors with precise discrete ratios.
`Terminating an array of capacitors like that shown in FIG.
`7A requires a different design for the end units. Connecting
`the separate fingers of inner terminal 72 likewise requires a
`distinct design. These two special requirements dictate less-
`ideal characteristics for these unique capacitors, involving
`either finger-end effects which yield a capacitance obeying
`Equation 2 or 3 (rather than the more-ideal Equation 5), or
`reduced self-shielding completeness, or both effects. Never-
`theless, in many practical designs such less-ideal capacitors
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`can be combined with a set of very well-matched capacitors
`such as 75 and 76 to perform useful functions with negligible
`compromise.
`FIGS. 8A, 8B, and 9A-9C depict capacitors suitable for
`terminating a capacitor array like that of FIG. 7. As with the
`capacitors described above, the number of fingers shown is
`merely illustrative, and NF can range from 1 to any number
`required.
`FIGS. 8A and 8B show examples of capacitor designs
`which terminate an array like that of FIG. 7A without con-
`necting the inner-terminal fingers. FIG. 8A shows a termina-
`tion-capacitor design where terminal 84 extends to a number
`of fingers 85 that surround each of the fingers 72A-C of
`common terminal 72. This design provides complete self-
`shielding together with precise proportionality to NF (i.e., the
`capacitance obeys Equation 3). This capacitor is similar to the
`upper end of the capacitor in FIG. 2A.
`FIG. 8B shows a termination-capacitor design which sac-
`rifices some self-shielding effectiveness but allows for exter-
`nal connections to the inner-terminal fingers. The capacitor
`86 is similar to the lower end of the capacitor in FIG. 6, and
`also obeys Equation 3. The indicated vias 88 are necessary to
`connect the isolated outer-terminal fingers such as 81 and 82
`to outer terminal 83, as discussed in connection with FIG. 7A.
`These vias add a small capacitance between inner and outer
`fingers which is equal for each inner-terminal finger, thus
`maintaining C proportional to NF.
`FIGS. 9A, 9B, and 9C show designs which serve both to
`terminate a capacitor array, such as the array 700 of FIG. 7A,
`and to provide connections between the inner-terminal fin-
`gers. FIG. 9A shows a capacitor 94 similar to the lower end of
`the capacitor in FIG. 5, with the inner fingers extending
`beyond LF. Like that design, it obeys Equation 3, providing
`capacitance precisely proportional to NF. Si