w’l AND1%
`
` If?
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria1 Virginia 22313- 1450
`wwwnsptogov
`
`APPLICATION NO.
`
`
`
`
`
` F ING DATE
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`
`
`
`
`CONF {MATION NO.
`
`12/276,289
`
`11/21/2008
`
`Patrick]. Quinn
`
`X—3004 US
`
`3744
`
`24309
`
`7590
`
`10/27/2010
`
`XEINXJNC
`ATTN: LEGAL DEPARTMENT
`2100 LOGIC DR
`SAN JOSE, CA 95124
`
`FERNANDES, ERROL V
`
`2894
`
`MAIL DATE
`
`10/27/2010
`
`PAPER NUMBER
`
`DELIVERY MODE
`
`PAPER
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`PTOL—90A (Rev. 04/07)
`
`IVM 1004
`
`IPR ofU.S. Pat. No. 7,994,609
`
`

`

`
`
`Office Action Summary
`
`Application No.
`
`Applicant(s)
`
`12/276,289
`
`QUINN, PATRICK J.
`
`Examiner
`
`ERROL FERNANDES
`
`Art Unit
`
`2894 -
`
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE 3 MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION
`Extensions of time may be available under the provisions of 37 CFR 1.136(a).
`In no event however may a reply be timely filed
`after SIX (6) MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1)IXI Responsive to communication(s) filed on 14 September 2010.
`
`2a)I:I This action is FINAL.
`
`2b)IZI This action is non-final.
`
`3)I:I Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`
`closed in accordance with the practice under EX parte Quayle, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims
`
`4)IZI Claim(s) 1-15 and 19-23 is/are pending in the application.
`
`4a) Of the above Claim(s) 10,14 and 15 is/are withdrawn from consideration.
`
`5)I:I Claim(s) _ is/are allowed.
`
`6)IXI Claim(s) 1-4 11-13 19 and 20 is/are rejected.
`
`7)IZI Claim(s) 5-9 and 21-23 is/are objected to.
`
`8)I:I Claim(s) _ are subject to restriction and/or election requirement.
`
`Application Papers
`
`9)I:I The specification is objected to by the Examiner.
`
`
`10)I:I The drawing(s) filed on
`
`is/are: a)I:I accepted or b)I:I objected to by the Examiner.
`
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
`
`11)I:I The oath or declaration is objected to by the Examiner. Note the attached Office Action or form PTO-152.
`
`Priority under 35 U.S.C. § 119
`
`12)I:I Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)—(d) or (f).
`
`a)I:I All
`
`b)I:I Some * c)I:I None of:
`
`1.I:I Certified copies of the priority documents have been received.
`
`2.I:I Certified copies of the priority documents have been received in Application No.
`
`
`
`3.I:I Copies of the certified copies of the priority documents have been received in this National Stage
`
`application from the International Bureau (PCT Rule 17.2(a)).
`
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`4) D Interview Summary (PTO-413)
`1) E Notice of References Cited (PTO-892)
`Paper No(s)/Mai| Date. _
`2) D Notice of Draftsperson‘s Patent Drawing Review (PTO-948)
`5) I:I Notice of Informal Patent Application
`3) IZI Information Disclosure Statement(s) (PTO/SB/08)
`
`
`Paper No(s)/Mai| Date 05/07/2009'02/11/2010'02/24/2010'03/18/2010.
`6) D Other:
`U.S. Patent and Trademark Office
`
`PTOL-326 (Rev. 08-06)
`
`Office Action Summary
`
`Part of Paper No./Mai| Date 20100923
`
`

`

`Application/Control Number: 12/276,289
`
`Page 2
`
`Art Unit: 2894
`
`DETAILED ACTION
`
`Election/Restrictions
`
`Applicant's election with traverse of claims 1-9, 11-13, 17-20 in the reply filed on
`
`07/02/2010 is acknowledged. The traversal is on the ground(s) that “the examiner has not
`
`made a showing of the serious burden”. This is not found persuasive because subspecies A
`
`and B denoted in the restriction (i) require a different field of search (for example, searching
`
`different classes/subclasses or electronic resources, or employing different search queries) and
`
`(ii) the prior art applicable to subspecies A would not likely be applicable to subspecies B.
`
`The requirement is still deemed proper and is therefore made FINAL.
`
`Furthermore, the examiner has acknowledged the submitted preliminary amendment
`
`mailed to the office on 09/14/2010. As a result, the following office action has been prosecuted
`
`with regards to claims 1-9, 11-13 and 19-23.
`
`Claim Rejections - 35 USC § 102
`
`The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the
`
`basis for the rejections under this section made in this Office action:
`
`A person shall be entitled to a patent unless —
`
`(b) the invention was patented or described in a printed publication in this or a foreign country or in
`public use or on sale in this country, more than one year prior to the date of application for patent in
`the United States.
`
`Claim 1, 3, 4 and 11-13 are rejected under 35 U.S.C. 102(b) as being Fong et al. by US
`
`7,259,956 B2.
`
`Regarding claim 1, Fong discloses:
`
`a core capacitor portion having a first plurality of conductive elements (terminal A)
`
`electrically connected to (Via D) and forming a first part of a first node of the capacitor formed in
`
`a first conductive layer (Layer E) of the IC and a second plurality of conductive elements
`
`

`

`Application/Control Number: 12/276,289
`
`Page 3
`
`Art Unit: 2894
`
`(terminal B) electrically connected to (Via E) and forming a first part of a second node of the
`
`capacitor formed in the first conductive layer (Layer E), the first plurality of conductive elements
`
`alternating with the second plurality of conductive elements in the first conductive layer, and a
`
`third plurality of conductive elements (terminal A or B, chosen as A in this case) electrically
`
`connected to and forming a second part of the first node formed in a second conductive layer
`
`(Layer D) adjacent to the first conductive layer, at least portions of some of the second plurality
`
`of conductive elements overlying and vertically coupling to at least portions of some of the third
`
`plurality of conductive elements; and (refer to Figure set 2A—2C
`
`specifically Fig. 28)
`
`a shield capacitor portion having a fourth plurality of conductive elements formed in at
`
`least the first conductive layer of the IC (Layer E), the second conductive layer of the IC (Layer
`
`D), a third conductive layer of the IC (Layer Z), and a fourth conductive layer of the IC (Layer A),
`
`the first conductive layer and the second conductive layer each being between the third
`
`conductive layer and the fourth conductive layer (refer to Figure set 2A-2C
`
`specifically Fig.
`
`23),
`
`the shield capacitor portion being electrically connected to and forming a second part of
`
`the second node of the capacitor and surrounding the first plurality of conductive elements and
`
`the third plurality of conductive elements (refer to Figure set 2A-2C
`
`specifically Fig. 2B - col 5
`
`lines 36-42; shield top-most layer, bottom-most layer and side shield similar to that shown in Fig
`
`1D 192/194 formed in all intermediate layers
`
`such shields can be connected to one of the
`
`capacitors terminals [in this case terminal B can be chosen to be connected to form a second
`
`part of the second node]).
`
`Regarding claim 3, Fong discloses:
`
`wherein the shield capacitor portion includes a first node shield plate formed in the third
`
`conductive layer and a second node shield plate formed in the fourth conductive layer and
`
`

`

`Application/Control Number: 12/276,289
`
`Page 4
`
`Art Unit: 2894
`
`further comprising a first conductive curtain extending from the first node shield plate to the
`
`second node shield plate and a second conductive curtain extending from the first node shield
`
`plate to the second node shield plate (refer to Figure set 2A-2C
`
`specifically Fig. 2B - col 5
`
`lines 36-42; shield top-most layer, bottom-most layer and side shield similar to that shown in Fig
`
`1D 192/194 formed in all intermediate layers
`
`such shields can be connected to one of the
`
`capacitors terminals [in this case terminal B can be chosen to be connected to form a second
`
`part of the second node]).
`
`Regarding claim 4, Fong discloses:
`
`the first node is a top node of the switching capacitor and the second node is a bottom
`
`node of the capacitor (refer to claim 1). In regards to the claimed limitation which states
`
`“switching capacitor” the examiner does not give patentable weight since it has been held that a
`
`recitation with respect to the manner in which a claimed apparatus is intended to be employed,
`
`in the instant application as a switching capacitor, does not differentiate the clamed apparatus
`
`from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2
`
`USPQ F.2d 1647 (1987).
`
`Regarding claim 11, Fong discloses:
`
`wherein the first plurality of conductive elements comprises a first plurality of conductive
`
`strips extending along a first direction, the second plurality of conductive elements comprises a
`
`second plurality of conductive strips extending along the first direction (Layer E), and the third
`
`plurality of conductive elements comprises a third plurality of conductive strips extending along
`
`a second direction orthogonal to the first direction (Layer D) (refer to Figs 2B for Layer E and 2C
`
`for Layer D).
`
`Regarding claim 12, Fong discloses:
`
`

`

`Application/Control Number: 12/276,289
`
`Page 5
`
`Art Unit: 2894
`
`wherein each of the conductive elements in the third plurality of conductive elements is
`
`adjacent to a conductive element electrically connected to and forming a third part of the first
`
`node (Fig 2C, Layer D shown with optional connection using Via D layer to Layer E,
`
`in this case
`
`terminal A of Layer D would be connected to terminals A of Layer E).
`
`Regarding claim 13, Fong discloses:
`
`a fourth plurality of conductive elements (terminal A) formed in a fifth conductive layer
`
`(Layer C) of the IC disposed between the fourth conductive layer (Layer A) and the second
`
`conductive layer (Layer D) and electrically connected to (Via C) and forming a fourth part of the
`
`first node, the fourth plurality of conductive elements extending along the first direction, and
`
`a fifth plurality of conductive elements (terminal B) electrically connected to and forming
`
`a third part of the second node formed in the fifth conductive layer extending along the first
`
`direction alternating with the fourth plurality of conductive elements in the fifth conductive layer
`
`(refer to Fig 2B).
`
`Claim Rejections - 35 USC § 103
`
`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
`
`obviousness rejections set forth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described as set
`forth in section 102 of this title, if the differences between the subject matter sought to be patented and
`the prior art are such that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said subject matter pertains.
`Patentability shall not be negatived by the manner in which the invention was made.
`
`Claim 2 is rejected under 35 U.S.C. 103(a) as being unpatentable over Fong as in claim
`
`1 above, and in further view of Hajimiri US 6,690,570 B2
`
`Regarding claim 2, Fong discloses:
`
`wherein the third conductive layer is a metal layer of the IC and the fourth conductive
`
`layer is a metal layer of the IC, the shield capacitor portion including a first node shield plate
`
`

`

`Application/Control Number: 12/276,289
`
`Page 6
`
`Art Unit: 2894
`
`formed in the metal layer from a plurality of metal stripes and a second node shield plate formed
`
`in the metal layer (Fig 2A, 200 metal layer is depicted as forming all Via and Layers in Figs 28
`
`and 2C).
`
`Fong does not disclose:
`
`the fourth conductive layer is a poly layer
`
`Hajimiri discloses a patent from a similar field of endeavor in which:
`
`conductive strips can be either metal conducting strips or poly crystalline silicon strips.
`
`It would have been obvious to one of ordinary skill in the art at the time the invention was
`
`made to understand that the fourth conductive layer taught by Fong could be made of poly as
`
`taught by Hajimiri since both metal and poly have been shown by Hajimiri as suitable materials
`
`for inclusion as conductive strips of a stacked lC capacitor structure.
`
`Claims 19 and 20 are rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`Stribely et al. US 6,933,551 B1 in further view of Anthony US 7,439,570 B2
`
`Regarding claim 19, Stribley discloses:
`
`a first plate formed in a first conductive layer of the IC (Plate 1a);
`
`a second plate formed in a substrate of the IC (Diffused plate 10);
`
`a gate dielectric layer disposed between the first plate and the second plate (Dielectric
`
`10);
`
`Stribley does not disclose:
`
`a shield plate formed in a second conductive layer of the IC having a perimeter
`
`electrically connected the second plate so as to form an electrical shield around the first plate.
`
`Anthony discloses:
`
`

`

`Application/Control Number: 12/276,289
`
`Page 7
`
`Art Unit: 2894
`
`a shield plate (35 shield plate) formed in a second conductive layer of an IC having a
`
`perimeter electrically connected to second plate (46 diffused bottom shield plate) in a substrate
`
`(refer to Fig 4)
`
`It would have been obvious to one of ordinary skill in the art at the time the invention was
`
`made to form the shield plate taught by Anthony around the first plate taught by Stribley and
`
`connected to the substrate since it is shown that the substrate of Anthony provides a bottom
`
`plate for the shield while the substrate also has function as a bottom plate for the capacitor
`
`structure taught by Stribley. As a result, the capacitor of Stribely would benefit from the shielding
`
`structure taught by Anthony in that the capacitor would have close matching to adjacent
`
`capacitors, maintain good linearity, and retain high quality factors while also achieving high
`
`efficiency at higher device densities.
`
`Regarding claim 20, as in the combination of claim 19 above, Stribley discloses:
`
`the first conductive layer is a first poly layer (col 2 line 53; polysilicon), the substrate
`
`comprises silicon (col 2 line 40; silicon) and second plate is formed in an N-well (heavier doped
`
`region of substrate) of the substrate and
`
`Stribley/Anthony do not specifically disclose:
`
`the shield plate is formed in a second poly layer of the IC.
`
`Anthony does disclose that the bottom shield plate (36) can be implemented with a
`
`polysilicon layer as well. As a result of this dislcosure, it would have been obvious to one of
`
`ordinary skill in the art at the time the invention was made to understand that the top plate
`
`taught by Anthony could be formed using polysilicon since such a material is disclosed a
`
`suitable for the same purpose as the bottom plate.
`
`

`

`Application/Control Number: 12/276,289
`
`Page 8
`
`Art Unit: 2894
`
`Allowable Subject Matter
`
`Claims 5-9 and 21-23 are objected to as being dependent upon a rejected base claim,
`
`but would be allowable if rewritten in independent form including all of the limitations of the base
`
`claim and any intervening claims.
`
`Conclusion
`
`Any inquiry concerning this communication or earlier communications from the examiner
`
`should be directed to ERROL FERNANDES whose telephone number is (571)270-7433. The
`
`examiner can normally be reached on Monday - Friday 7:30-5:00 (alt Fri's off).
`
`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
`
`supervisor, Kimberly Nguyen can be reached on 571-272-2402. The fax phone number for the
`
`organization where this application or proceeding is assigned is 571-273-8300.
`
`Information regarding the status of an application may be obtained from the Patent
`
`Application Information Retrieval (PAIR) system. Status information for published applications
`
`may be obtained from either Private PAIR or Public PAIR. Status information for unpublished
`
`applications is available through Private PAIR only. For more information about the PAIR
`
`system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private
`
`PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you
`
`would like assistance from a USPTO Customer Service Representative or access to the
`
`automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
`
`/ERROL FERNANDES/
`Examiner, Art Unit 2894
`
`lKimberly D Nguyen/
`Supervisory Patent Examiner, Art Unit
`2894
`
`