US007994609B2
`
`(12) Ulllted States Patent
`Quinn
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,994,609 B2
`Aug. 9, 2011
`
`(54) SHIELDING FOR INTEGRATED
`CAPACITORS
`
`4,914,546 A
`4,937,649 A
`4,994,688 A
`
`4/1990 Alter
`6/1990 Shiba et al.
`2/1991 Horiguchi et al.
`
`(75)
`
`Inventor: Patrick J. Quinn, Dublin (IE)
`
`(Continued)
`
`(73) Assignee: Xilinx, Inc., San Jose, CA (US)
`
`DE
`
`FOREIGN PATENT DOCUMENTS
`25 48 563 A1
`5/1977
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 137 days.
`
`(Continued)
`
`OTHER PUBLICATIONS
`
`(zl) Appl- N05 12/2762289
`.
`Ffled:
`
`(22)
`(65)
`
`NOV‘ 21’ 2008
`Prior Publication Data
`US 2010/0127347 A1
`May 27, 2010
`
`(51)
`
`Int CL
`(2006.01)
`H01L 21/02
`(52) U.S. Cl.
`....................... .. 257/532, 257/499, 257/528
`(58) Field of Classification Search ................ .. 257/296,
`257/306, 307, 309, 532, 361/3061, 306.2
`See applleallen file fer eemplele Sealeh l1l5l01'Y~
`e erences
`1 e
`R f
`Ct d
`U.S. PATENT DOCUMENTS
`
`(56)
`
`1,899,176 A
`3,593,319 A
`4,156,249 A
`4,249,196 A
`4,409,608 A
`4,427,457 A
`4,470,096 A
`4,470,099 A
`4,571,543 A
`4,639,686 A
`4,700,457 A
`4,731,696 A
`4,827,323 A
`4,831,431 A
`4,878,151 A
`
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`
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`Heidelberg, Berlin Heidelberg, pp. 68-78.
`(C°mm“ed)
`
`Prirnary Examiner — Thanh V Pham
`Asszszanl Exammer — Errol Femandes
`(74) Attorney. Agent. or Firm — Scott Hewett; John J . King
`
`ABSTRACT
`(57)
`A capacitor in an integrated circuit (“IC”) includes a core
`capacitor portion having first conductive elements electri-
`cally connected to and forming a part of a first node of the
`capacitor formed in a first layer and second conductive ele-
`ments electrically connected to and forming a part of a second
`node of the capacitor formed in the first layer. The first and
`second conductive elements alternate in the first conductive
`
`layer. Third conductive elements electrically connected to
`and forming a part of the first node are formed in a second
`layer adjacent to the first layer. The capacitor also includes a
`shield capacitor portion having fourth conductive elements
`formed in at least first, second, third, and fourth layers. The
`shield capacitor portion is electrically connected to and forms
`a part of the second node of the capacitor and surrounds the
`first and third conductive elements.
`
`19 Claims, 9 Drawing Sheets
`
`222
`
`424 Substrate
`
`M1
`
`N+
`Substrate
`
`V99 Shield (N-well)
`
`IVM 1001
`
`IPR ofU.S. Pat. No. 7,994,609
`
`

`
`US 7,994,609 B2
`Page 2
`
`>>>>D>>>>>>D>>>>D>D>D>>D>D>D>D>
`
`*
`
`*
`
`5,005,103
`5,021,920
`5,077,225
`5,083,184
`5,089,878
`5,117,114
`5,119,169
`5,142,639
`5,155,658
`5,166,858
`5,172,299
`5,177,410
`5,189,594
`5,208,725
`5,275,974
`5,583,359
`5,712,813
`5,868,388
`5,939,766
`6,037,621
`6,064,108
`6,066,537
`6,297,524
`6,303,456
`6,303,457
`6,383,858
`6,385,033
`6,410,954
`6,417,556
`6,542,351
`6,570,210
`6,597,562
`6,625,006
`6,653,681
`6,661,079
`6,690,570
`6,737,698
`6,747,307
`6,765,778
`6,819,542
`6,822,312
`6,880,134
`6,882,015
`6,897,505
`6,903,918
`6,927,125
`6,933,551
`6,949,781
`6,963,122
`6,974,744
`7,009,832
`7,013,436
`7,027,287
`7,038,296
`7,050,290
`7,116,544
`7,154,734
`7,161,228
`7,170,178
`7,193,263
`7,195,971
`7,202,548
`7,259,956
`7,271,465
`7,274,085
`7,298,001
`7,348,624
`7,439,570
`7,485,914
`7,564,675
`7,663,233
`7,768,054
`2005/0077581
`2005/0135042
`2005/0161725
`
`*
`
`............... .. 361/306.2
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`
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`
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`10/2001
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`
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`polyiamonds”, Journal of Computational and Applied Mathematics,
`Amsterdam, NL, vol. 174, No. 2, Feb. 15, 2005, pp. 329-353.
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`problems” European Journal of Operational Research, Amsterdam,
`NL, vol. 83, No. 3, Jul. 10, 2007, pp. 950-960.
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`mial”, Journal of Physics A: Mathematical and Theoretical, vol. 40,
`No. 7, Feb. 16, 2007. pp. 1439-1446.
`U.S. Appl. No. 12/276,291, filed Nov. 21, 2008, Quinn, Patrick J.,
`Xilinx, Inc. 2100 Logic Drive, San Jose, California.
`U.S. Appl. No. 12/276,292, filed Nov. 21, 2008, Quinn, Patrick J.,
`Xilinx, Inc. 2100 Logic Drive, San Jose, California.
`U.S. Appl. No. 12/276,293, filed Nov. 21, 2008, Quinn, Patrick J.,
`Xilinx, Inc. 2100 Logic Drive, San Jose, California.
`U.S. Appl. No. 12/276,296, filed Nov. 21, 2008, Quinn, Patrick J.,
`Xilinx, Inc. 2100 Logic Drive, San Jose, California.
`U.S. Appl. No. 12/276,280, filed Nov. 21, 2008, Quinn, Patrick J.,
`Xilinx, Inc. 2100 Logic Drive, San Jose, California.
`Aparicio and Hajimiri, “Capacity Limits and Matching Properties of
`Integrated Capacitors”, IEEE J. Solid-State circuits, vol. 37, No. 3,
`pp. 384-393, Mar. 2002.
`Samavati, H. et al., “Fractal Capacitor”, IEEE Journal of Solid-State
`Circuit, vol. 33, No. 12 pp., 2035-2041, Dec. 1998.
`Chan et al., “Analysis of MMIC Structures Using an Efficient Itera-
`tive Approach”, IEEE Transactions on Microwave Theory and Tech-
`niques, vol. 36, No. 1, Jan. 1988, pp. 96-105.
`Imamura et al., “Bending-Comb capacitor with a Small Parasitic
`Inductance”, 2002 Symposium on VLSI Circuits Digest of Technical
`Papers, IEEE 2002, Jun. 13-15, 2002, pp. 22-25.
`Rajagopalan et al., “Optimization of Metal-Metal Comb-Capacitors
`for RF Applications”, Wireless Design & Development, Mar. 4, 2001,
`pp. 1-4.
`Sowlati et al., “High Density Capacitance Structures in Submicron
`CMOS for Low Power RF Applications”, International Symposium
`on Low Power Electronics and Design, 2001, Aug. 6-7, 2001, pp.
`243-246.
`Wakayama et al., “A 30-MHz Low-Jitter High-Linearity CMOS Volt-
`age-ControlledOscillator”, IEEE Journal of Solid-State Circuits, vol.
`sc-22, No. 6, Dec. 1987, pp. 1074-1081.
`
`* cited by examiner
`
`

`
`U.S. Patent
`
`Aug. 9, 2011
`
`Sheet 1 019
`
`US 7,994,609 B2
`
`FIG. 2A
`
`

`
`U.S. Patent
`
`Aug. 9, 2011
`
`Sheet 2 of9
`
`US 7,994,609 B2
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`Aug. 9, 2011
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`US 7,994,609 B2
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`US 7,994,609 B2
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`U.S. Patent
`
`Aug. 9, 2011
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`Sheet 7 of9
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`US 7,994,609 B2
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`
`U.S. Patent
`
`Aug. 9, 2011
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`Sheet 8 of9
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`US 7,994,609 B2
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`U.S. Patent
`
`Aug. 9, 2011
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`
`1
`SHIELDING FOR INTEGRATED
`CAPACITORS
`
`RELATED APPLICATIONS
`
`This patent application is being concurrently filed with
`commonly owned U.S. Patent Application entitled INTE-
`GRATED CAPACITOR WITH TARTAN CROSS SECTION
`
`by Patrick J. Quinn; and with commonly owned U.S. Patent
`Application entitled INTEGRATED CAPACITOR WITH
`INTERLINKED LATERAL FINS by Patrick J. Quinn; and
`with commonly owned U.S. Patent Application entitled
`INTEGRATED CAPACITOR WITH CABLED PLATES by
`Patrick J. Quinn; and with commonly owned U.S. Patent
`Application entitled INTEGRATED CAPACITOR WITH
`ARRAY OF CROSSES by Patrick J. Quinn; and with com-
`monly owned U.S. Patent Application entitled INTE-
`GRATED CAPACITOR WITH ALTERNATING LAYERED
`
`SEGMENTS by Jan L. de Jong et al., the disclosures ofwhich
`are each hereby incorporated by reference in their entireties
`for all purposes.
`
`FIELD OF THE INVENTION
`
`The present invention relates to capacitors formed in inte-
`grated circuits (“ICs”) commonly referred to as integrated
`capacitors.
`
`BACKGROUND
`
`Methods of fabricating ICs typically include a front-end
`sequence of processing, in which various electrical devices
`such as transistors are formed in a semiconductor substrate,
`and a back-end sequence of processing, generally including
`forming alternating layers ofdielectric material and patterned
`conductive material (typically metal) with conductive vias or
`other techniques being used to interconnect the metal layers
`to form a three-dimensional wiring structure that connects
`electrical devices to other electrical devices and to terminals
`of the IC.
`
`Capacitors are used in IC systems for a variety ofpurposes.
`In many instances, it is desirable to incorporate (integrate) a
`capacitor in the IC chip. A simple approach is to form two
`conductive plates with an intervening dielectric; however,
`this consumes a relatively large area for the capacitance
`obtained. One technique for increasing the capacitance of a
`given area is to use multiple conductive plates, each conduc-
`tive plate separated from the proximate plate(s) by dielectric.
`Further techniques use conducting strips, also called conduc-
`tive lines, conductive fingers, or conductive traces, that are
`alternately connected to the first and second capacitor termi-
`nals (nodes). Sidewall coupling between the conductive strips
`provides capacitance. Layers of conducting strips, either off-
`set or arranged in vertical congruency, can be added to further
`increase the capacitance of an integrated capacitor structure.
`One capacitor has a number of conductive strips in succes-
`sive layers connected to the first node alternating with an
`equal number of conductive strips connected to the second
`node of the integrated capacitor. The conductive strips are
`offset a half cell on successive layers, so that a conductive
`strip connected to the first node has conductive strips con-
`nected to the second node above and on both sides of it.
`
`Providing an equal number of conductive strips in a layer for
`each node balances the coupling of each node to the substrate,
`which is desirable in some applications, but undesirable in
`others, such as switching applications where it is desirable to
`have less coupling at one node. In order to reduce coupling to
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`US 7,994,609 B2
`
`2
`
`the substrate, a thick layer of silicon dioxide is used between
`the substrate and the first layer of conductive strips. This may
`be difiicult to integrate in a standard CMOS fabrication
`sequence and might require additional steps to be added to the
`standard process flow. The overlapping parallel conductive
`strips are connected at their ends using buss strips that con-
`sume additional surface area.
`
`Another approach to providing an integrated capacitor is to
`have conductive strips in a layer connected to alternate nodes
`ofthe capacitor with overlapping conductive strips connected
`to the same node. This forms essentially a curtain of conduc-
`tive strips and interconnecting vias connected to the first node
`of the capacitor with adjacent curtains of conductive strips
`and interconnecting vias connected to the second node. Over-
`lapping conductive strips connected to the same node avoids
`the lost surface area associated with buss strips; however,
`inter-layer capacitance is reduced because the upper strip is
`connected to the same node as the lower strip. This effect is
`somewhat obviated because, as critical dimensions shrink,
`inter-strip capacitance becomes more dominant than inter-
`layer capacitance. In other words, the dielectric layer separa-
`tion between successive metal layers becomes increasingly
`greater than the dielectric separation between conductive
`strips with decreasing critical dimension.
`Conventional integrated capacitors are often susceptible to
`electronic noise, which can affect the performance of the IC.
`In some applications, such as a filter capacitor application
`where one of the capacitor nodes (typically the bottom node)
`is connected to ground or to a power supply voltage, some
`degree of noise is often tolerable. However, in other applica-
`tions, such as when the capacitor is used in a signal path (i.e.,
`as a coupling capacitor or a switched capacitor), noise cou-
`pling can seriously degrade the performance of the circuit.
`Noise coupled onto a capacitor are particularly problematic
`when very low analog voltages are coupled through the
`capacitor, especially in a system on a chip, which often pro-
`duce more electrical noise than other types of ICs, such as a
`memory chip. Thus, integrated capacitors providing better
`noise immunity are desired for used low-noise applications
`on an IC.
`
`SUMMARY
`
`A capacitor in an integrated circuit (“IC”) includes a core
`capacitor portion having a first plurality of conductive ele-
`ments electrically connected to and forming part of a first
`node of the capacitor formed in a first conductive layer of the
`IC and a second plurality of conductive elements electrically
`connected to and forming part of a second node of the capaci-
`tor formed in the first conductive layer. The first plurality of
`conductive elements alternates with the second plurality of
`conductive elements in the first conductive layer. A third
`plurality ofconductive elements electrically connected to and
`forming part ofthe first node is formed in a second conductive
`layer adjacent to the first conductive layer, at least portions of
`some of the second plurality of conductive elements overly-
`ing and vertically coupling to at least portions of some of the
`third plurality of conductive elements. The capacitor also
`includes a shield capacitorportion having a fourth plurality of
`conductive elements formed in at least the first conductive
`
`layer of the IC, the second conductive layer of the IC, a third
`conductive layer ofthe IC, and a fourth conductive layer. The
`first and second conductive layers are between the third and
`fourth conductive layers. The shield capacitor portion is elec-
`
`

`
`US 7,994,609 B2
`
`3
`trically connected to and forms part ofthe second node of the
`capacitor and surrounds the first and third pluralities of con-
`ductive elements.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Accompanying drawing(s) show exemplary embodiment
`(s) in accordance with one or more aspects of the invention;
`however, the accompanying drawing(s) should not be taken to
`limit the invention to the embodiment(s) shown, but are for
`explanation and understanding only.
`FIG. 1 is a circuit diagram of a circuit using capacitors
`according to embodiments of the invention.
`FIG. 2A is an isometric view of a portion of a shielded
`integrated capacitor suitable for use in embodiments of the
`present invention.
`FIG. 2B is a side view of a integrated capacitor 220 in
`accordance with FIG. 2A.
`
`FIG. 2C is a side view ofthe integrated capacitor according
`to FIG. 2A with a ground shield according to an embodiment.
`FIG. 2D is a side view ofthe integrated capacitor according
`to FIG. 2A with an alternative ground shield according to
`another embodiment.
`
`FIG. 3A is a side view of an integrated capacitor with a
`bottom node shield according to an alternative embodiment.
`FIG. 3B is a partial cutaway plan view of the M5 and M4
`layers showing a portion of the ground plate and underlying
`bottom node shield plate of FIG. 3A.
`FIG. 4A is side view of an integrated capacitor with a
`bottom node shield according to yet another alternative
`embodiment.
`
`FIG. 4B is a cross section of a shielded integrated thin-
`dielectric capacitor in an IC according to another embodi-
`ment.
`
`FIG. 5 is a plan view of an FPGA incorporating an inte-
`grated capacitor according to an embodiment.
`
`DETAILED DESCRIPTION
`
`FIG. 1 is a circuit diagram of a circuit 100 using capacitors
`102, 104 according to embodiments of the invention. The top
`node 108 of capacitor 104 is switchable to be connected to or
`disconnected from a high-impedance input 114 of amplifier
`116. The bottom node 112 is connected to a switch. The top
`node 106 of the feedback capacitor 102 is also connected to
`the high-impedance input 114 of the amplifier 116 while the
`bottom node 110 is connected to output 118 of the amplifier
`116. The feedback capacitor 102 is switchably shorted by
`closing switch 119. The coupling capacitor 104 has a top node
`108 shielded by a bottom node shield 120 that essentially
`surrounds the top node 108 with conductive structures elec-
`trically connected to the bottom node and reduces parasitic
`capacitive coupling of the top node 108 to other nodes of the
`circuit 100. Connection to the top node 108 is made through
`a gap in the bottom node shield 120. Although the bottom
`node shield is shown as being contiguous, in some embodi-
`ments the bottom node shield is made up of several conduc-
`tive elements, such as metal filaments, metal vias, and poly-
`silicon or silicide plates or strips, to form a conductive cage
`around the top node, shielding the top node from electronic
`noise and from coupling to other nodes of the IC. In some
`embodiments, the bottom node shield contributes to the over-
`all capacitance of the integrated capacitor by coupling to the
`top node.
`The feedback capacitor 102 has a top node 110 shielded by
`a bottom node shield 122, and by an optional reference shield
`124. The reference shield 124 is connected to a relatively
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`stable reference voltage present in the IC, such as analog
`ground, digital ground, or VDD. The reference shield 124
`essentially surrounds the bottom node shield 120 and shields
`the bottom node from substantially coupling to more than one
`voltage reference (e.g., the bottom node couples to VDD or
`ground, but not both). In other embodiments, a reference
`shieldpartially surrounds a bottom node shield. The reference
`shield has a gap allowing electrical contact to be made to the
`bottom node, as described above.
`The terms “top” node and “bottom” node do not necessar-
`ily relate to the physical orientation ofthe nodes relative to the
`IC or other structure, but are used as terms of convenience. In
`some circuit applications, the top node of a capacitor indi-
`cates the node that is connected to a high-impedance or high-
`gain port of an amplifier or other device. In a system-on-chip
`(“SoC”),
`the accuracy on an analog-to-digital converter
`(“ADC”) is dependent on the ratio ofthe parasitic capacitance
`at the top node (Ctop) to all other nodes except the bottom
`node and the capacitance (Csig) that is the useful floating
`signal capacitance between both nodes. It is desirable to
`shield the top plate from ground currents or voltage supply
`fluctuations so that Ctop remains low. Using the bottom node
`to essentially surround the top node isolates the top node from
`coupling with other nodes in the circuit by essentially form-
`ing a portion of Faraday shell around the top node, and in
`some embodiments, distancing the top node from other con-
`ductive elements in the IC. It is understood by those of skill in
`the art that electrical connection to the top node is made
`through the bottom node shield, and therefore the bottom
`node shield does not completely surround the top node.
`In some embodiments, some sides of the top node are left
`unshielded. For example, an end of the top node that is physi-
`cally distant from other nodes might be left unshielded. In
`other embodiments, integrated capacitors are used as design
`cells, and adjacent integrated capacitors are connected in
`parallel to obtain a higher total capacitance. In some embodi-
`ments, the portions of the bottom node shield of adjacent
`commonly-connected integrated capacitors are omitted,
`allowing higher packing density.
`Complex ICs, such as programmable logic devices, often
`have several patterned metal layers separated by layers of
`dielectric material formed over a semiconductor substrate
`
`that are used for wiring connections and other functions com-
`monly called the “backend” of the IC. Some embodiments of
`the invention are adaptable to existing CMOS process
`sequences by using masks that form the desired patterns in the
`appropriate metal layers and vias through the inter-metal
`dielectric (“IMD”) layers or inter-layer dielectric (“ILD”) in
`the backend of the IC. The vias are formed using any of
`several known techniques, such as contact plug, damascene,
`or dual damascene techniques. Similarly,
`the conductive
`strips are formed using any of several known techniques, such
`as thin-film metal etch, thin-film metal lift-off, damascene,
`and dual damascene techniques. In some embodiments, one
`of the conductive layers is a polysilicon or silicide layer. In a
`further embodiment, a conductive well in the semiconductor
`substrate forms a portion of a capacitor plate or a shield.
`FIG. 2A is an isometric view of a portion 200 of an inte-
`grated capacitor according to an embodiment of the present
`invention. A bottom plate conductive matrix 202 includes a
`first bottom plate layer B made up of a first plurality of
`conductive strips 204, 206 and a second bottom plate layer B‘
`made up of a sheet of polysilicon or silicide, in what is
`commonly called a “poly” layer, all connected to the bottom
`node of the integrated capacitor. The bottom node in this
`embodiment is the capacitor node that is less susceptible to
`electronic noise than the top node when the capacitor is used
`
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`US 7,994,609 B2
`
`5
`in a particular circuit application. A top plate conductive
`matrix 212 is covered by the first bottom plate layer B and
`underlain by the second bottom plate layer B‘, which forms a
`partial Faraday shield around the top node.
`The first bottom plate layer is made up of strips, rather than
`a continuous sheet, because of design layout rules familiar to
`those of skill in the art of IC fabrication. Generally, each metal
`layer has minimum and maximum metal line widths and
`minimum separations. Polysilicon and silicide layers typi-
`cally have different design and process rules than patterned
`metal layers, which allows forming the bottom plate layer as
`a contiguous sheet of poly when the poly layer is used. Simi-
`larly, large conductive areas can be formed in the semicon-
`ductor substrate (e.g., an N-well or a P-well) to form a con-
`tinuous conductive sheet. In an alternative embodiment, the
`second bottom plate layer is formed in a conductive well of
`the substrate. The conductive well is separated from the poly
`layer by a relatively thin dielectric layer, providing good
`electrical performance even though the N-well is generally
`less conductive than a metal layer or poly layer. Using a
`conductive well to form part of a shield is further desirable
`because a moat can be formed around the portion of the
`substrate in which the N-well or P-well is formed, which
`further isolates the N- or P-well from stray currents. Use of a
`conductive well in a shield is also desirable because the well
`
`is surrounded in a fairly symmetrical fashion by metal, lead-
`ing to symmetrical current flow through the well portion of
`the shield.
`
`The conductive strips 204, 206 in the top plate layer B are
`electrically connected through vias (not shown, see, e.g., via
`214) to transverse (i.e., generally orthogonal) conductive
`strips (e.g., B4) in the lower layer so that interconnection
`between conductive strips 204, 206 in the metal layer of the
`first bottom plate layer B is not necessary. Alternatively, con-
`ductive cross members (cross-connects between strips in the
`metal layer) are optionally included in the first bottom plate
`layer to connect conductive strips in the layer, which
`improves shielding.
`Similarly, a top plate layer T is made up of a plurality of
`conductive strips 216, 218 connected to the top node of the
`integrated capacitor. The conductive strips in the top plate
`layer T are transverse to conductive strips T1, T2, T3, T4, T5
`above the top plate layer T and transverse to conductive strips
`T6, T7, T8, T9, T10 below the top plate layer, and conductive
`strips in the top plate layerT are electrically connected to each
`other through vias and transverse conductive strips above and
`below the top plate layer T. In some embodiments, the con-
`ductive strips (e.g. T1, B1) are made from a minimum-width
`metal line and are commonly referred to as “conductive fila-
`ments” or “metal filaments” and provide high line densities
`and high lateral capacitance. Lateral capacitance between
`conductive strips in the plate layers does not contribute to the
`specific capacitance of the integrated capacitor because the
`metal strips are connected to the same node, and conductive
`strips in the plate layers are often wider than minimum metal
`line width.
`
`The plate layers B, T, B‘ do not have alternating conductive
`strips, but rather all the conductive strips in these layers are
`connected to either the top node or the bottom node of the
`integrated capacitor. The configuration of a capacitor accord-
`ing to FIG. 2A provides bottom plates B, B‘ that shield the
`conductive elements of the top plate because they are embed-
`ded between the first and second bottom plate layers in the IC
`stack. Conductive curtains (see, FIG. 2B, ref. nums. 236, 238)
`on the right and left sides of the top plate conductive matrix
`are formed of vias and metal layers between the first bottom
`plate B and the second bottom plate B‘ and extend along a
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`third direction (e.g., the Z direction as illustrated in FIG. 2A)
`to form essentially a conductive plane (in the plane defined by
`the Y and Z axes). The bottom plate conductive matrix of the
`integrated capacitor loosely surrounds the top plate conduc-
`tive matrix of the integrated capacitor so that the top plate
`couples with the bottom plate on the top, bottom, right side,
`and left side. In a further embodiment, additional conductive
`curtains are optionally added in the plane defined by the X and
`Z axes to cover (shield) the ends of the top node conductive
`elements in these planes.
`FIG. 2B is a side view of a integrated capacitor 220 in
`accordance with FIG. 2A. The side view is taken along the
`direction of the arrow A in FIG. 2A. The integrated capacitor
`has a core capacitorportion 201 and a shield capacitorportion
`203. The shield capacitor portion 203 is basically a bottom
`node shield that has a first shield layer B formed in the fifth
`metal layer MS of a backend stack 222 of an IC that includes
`metal layers M1, M2, M3, M4, M5 and intervening dielectric
`layers that have vias (e.g., via 251) extending through the
`dielectric layers to connect metal layers. The dielectric layers
`are not shown with hatching for clarity of illustration, as they
`are well understood by those of skill in the art of IC process-
`ing.
`Integrated capacitors according to alternative embodi-
`ments include additional metal layers. The integrated capaci-
`tor includes an optional reference shield, which in this
`embodiment is a reference shield connected to VDD. The
`reference shield includes a shield plate 224 made up of a
`conductive well (Nwell), formed in the semiconductor sub-
`strate 226 of the IC, a top shield plate 225 formed in the M5
`metal layer, and conductive curtains 240, 242.
`The shield capacitor portion 203 forms a conductive sheath
`around the core capacitor portion 201, which has interleaved
`top and bottom node conductive filaments that provide high
`specific lateral capacitance in the M1 and M3 metal layers,
`and vertical capacitance between the bottom node elements in
`M1 and M3 and the top node elements in M2, which is
`adjacent to both M1 and M3. The shield capacitor portion
`adds additional capacitance by coupling to the top node con-
`ductive elements in M1, M2, and M3. In a typical embodi-
`ment, each layer of interleaved filaments will have hundreds
`of filaments and the lateral coupling between the filaments is
`a significant portion of the total capacitance of the integrated
`capacitor.
`The secondbottom plate layer B‘ is formed in the poly layer
`of the IC. In an alternative embodiment, the second bottom
`plate layer is formed as strips in a metal layer, such as M1 or
`M2, in a backend stack that has additional metal layers. Uti-
`lizing the poly layer for the second bottom plate layer allows
`a shielded integrated capacitor (without the optional VDD
`shield) to be formed in a four-metal-layer IC. In an alternative
`embodiment, a conductive well formed in the semiconductor
`substrate is used as the second bottom plate layer, allowing an
`embodiment to be fabricated in three metal layers of an IC, or
`allowing additional metal layers for increasing the specific
`capacitance of a capacitor of a given area. The dielectric layer
`above the substrate and poly layer (not separately shown) is
`commonly called an inter-layer dielectric (“ILD”), and the
`conductive element 228 connecting the poly layer to the N+
`conductive area 230 of the substrate is commonly called a
`contact, as opposed to a via. A gate dielectric layer (not
`separately shown) between the poly and the N-well is typi-
`cally much thinner than the ILD layer.
`FIG. 2B is not drawn to scale. Generally, the thicknesses of
`the IMD and ILD layers are greater than the spacing between
`the interleaved conductive strips (e.g., T1 and B1) in the
`interleaved layers M3 and M1. In an exemplary embodiment,
`
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`US 7,994,609 B2
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`7
`the ILD layer is about 300 nm thick silicon oxide, while the
`dielectric layer between the poly layer and M1 layer is about
`100 nm thick and the higher layers are about 250 nm. The
`minimum separation between metal traces in a layer is typi-
`cally much smaller, thus the sidewall capacitance between T1 5
`and B1, for example, is greater than the vertical capacitance
`between T1 and B. Similarly,
`the sidewall capacitance
`between the ends of the top plate conductive matrix (e.g., T1,
`T4, T5, T8, and both ends of T) and the conductive curtains
`236, 238; and the end vias 250, 252 and curtain vias 254, 251
`(and corresponding vias on other sides) provide additional
`capacitance that compensates for the lack of interleaving in
`the M4, M2 and poly layers. As node technology shrinks and
`the minimum dimension between conductive strips in the
`interleaved layers decr