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`1013
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`INTELLECTUAL VENTURES MANAGEMENT, LLC
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`Petitioner
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`V.
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`XILINX, INC.
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`Patent Owner
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`Case 1PR2012-00023
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`Patent 7,994,609
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`SECOND DECLARATION OF MORGAN T. JOHNSON
`IN SUPPORT OF INTELLECTUAL VENTURES MANAGEMENT, LLC’S
`REPLY TO PATENT OWNER’S RESPONSE
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`
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`I, Morgan Johnson, declare as follows:
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`-2-
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`1.
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`I have been retained by Sterne, Kessler, Goldstein, and Fox PLLC on
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`behalf of Intellectual Ventures Management, LLC ("Intellectual Ventures
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`Management") for the above-captioned
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`inter partes review proceeding. I
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`understand that this proceeding involves U.S. Patent No. 7,994,609 ("the ’609
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`Patent") entitled "Shielding for Integrated Capacitors," and that the ’609 Patent is
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`currently assigned to Xilinx, Inc.
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`2.
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`I have reviewed and am familiar with the specification of the ’609
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`Patent filed on November 21, 2008 and issued on August 9, 2011. A copy of the
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`’609 Patent is provided as IVM 1001. I will cite to the specification using the
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`following format: (’609 Patent, 1:1-10). This example citation points to the ’609
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`patent specification at column 1, lines 1-10.
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`3.
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`I have reviewed and am familiar with U.S. Patent No. 6,737,698 to
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`Paul et al. (hereinafter "Paul"), U.S. Patent No. 7,439,570 to Anthony (hereinafter
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`"Anthony"), U.S. Patent No. 7,286,071 to Hsueh et al. (hereinafter "Hsueh"), U.S.
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`Patent No. 6,903,918 to Brennan (hereinafter "Brennan"), U.S. Patent No.
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`7,238,981 to Marotta (hereinafter "Marotta"), and U.S. Patent Application
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`Publication No. 2008/0128857 to Bi (hereinafter "Bi").
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`4.
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`I am familiar with the technology at issue as of the November 21,
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`-3-
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`2008 filing date of the ’609 Patent.
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`5.
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`I have been asked to provide my technical review, analysis, insights,
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`and opinions regarding the above-noted references that form the basis for the
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`grounds of rejection set forth in the Petition for
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`Inter Partes Review of the ’609
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`Patent.
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`I. (cid:9)
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`Qualifications
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`6.
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`I have more than 29 years of experience in the electronic interconnect
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`and semiconductor industries.
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`7.
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`I earned a Bachelor of Science degree in Graphics from the University
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`of Oregon. My studies included subjects in advanced mathematics related to
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`geodesic domes. I also attended The Art Center College of Design in Pasadena,
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`California, where I majored in Industrial Design.
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`8.
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`I currently serve as Chief Scientist at Advanced Inquiry Systems, Inc.
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`(AISI), a company that I founded in 2003. As Chief Scientist, my research focuses
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`on tools and interfaces for full-wafer testing of products such as NAND and NOR
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`flash, Dynamic Random Access Memory (DRAM), and certain logic devices. My
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`research is additionally driven by the semiconductor industry’s demand for highly-
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`parallel wafer testing of System-on-Chips (SOCs), such as processors for mobile
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`devices. Through my research, AISI has implemented a device that achieves
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`contact with up to 500,000 pads per wafer during tests. AISI was founded on my
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`patented work in this area and benefits from over 30 issued patents.
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`9.
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`I co-founded Prototype Solutions Corporation in 1994, a company
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`focused on using advanced interconnect and packaging technology to provide
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`quick-turn prototypes and hardware emulation using programmable logic devices
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`such as Field Programmable Gate Arrays (FPGAs). The technology is used to
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`prototype highly-complex Central Processing Units (CPUs), Graphic Processing
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`Units (GPUs), System on Chips (SOCs), and Application Specific Integrated
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`Circuits (ASICs).
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`10.
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`I founded LaserPath Corp. in 1983. Laserpath was a semiconductor
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`company focused on laser programmable semiconductor gate arrays. The
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`foundation of this technology was based on my inventions and patents. LaserPath
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`achieved over 200 design wins in the first 9 months of sales(cid:151)setting a record.
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`LaserPath’s technology included Gate Arrays programmed with a laser in a
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`ceramic package, tested, and delivered to customer in as little as two hours and
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`more typically within 5 business days. This rapid Gate Array turnaround time and
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`large number of design wins drastically shifted the ASIC business from a 12-week
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`delivery to a new standard of 3- week delivery.
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`11.
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`From 1981 to 1982, I researched controlled impedance, instant turn-
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`around circuit boards for the Cray 2 computer system. My research was funded by
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`Cray Computer Corporation(cid:151)Boulder, Colorado Team. This research was the
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`genesis for my later-developed technology that evolved into LaserPath.
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`12.
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`In addition to my semiconductor industry experience, I am an inventor
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`on 36 U.S. patents related to interconnects, high-speed connectors, and
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`semiconductors. Also, I have a faculty appointment as Adjunct Professor in the
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`Electrical Engineering School at Portland State University in Portland, Oregon. I
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`have also been a guest lecturer at the Jet Propulsion Laboratory (JPL) in Pasadena,
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`California.
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`13.
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`I have provided testimony in the form of a declaration in three other
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`inter partes review proceedings:
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`. Intellectual Ventures Management, LLC v. Xilinx, Inc., Case
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`1PR2012-00018.
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`Inter Partes Review of U.S.P. 7,994,609 (cid:9)
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`. Intellectual Ventures Management, LLC v. Xilinx, Inc., Case
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`SUM
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`1PR2012-00019.
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`. Intellectual Ventures Management, LLC v. Xilinx, Inc., Case
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`IPR20 12-00020.
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`14. My Curriculum Vitae is attached as Exhibit IVM1 015, which contains
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`further details on my education, experience, publications, patents, and other
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`qualifications to render an expert opinion. My work on this case is being billed at
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`a rate of $300.00 per hour, with reimbursement for actual expenses. My
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`compensation is not contingent upon the outcome of this inter partes review.
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`II. My Understanding of Obviousness
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`15.
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`It is my understanding that a claimed invention is unpatentable if the
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`differences between the invention and the prior art are such that the subject matter
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`as a whole would have been obvious at the time the invention was made to a
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`person having ordinary skill in the art to which the subject matter pertains.
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`16.
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`It is my understanding that "obviousness" is a question of law based
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`on underlying factual issues including the content of the prior art and the level of
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`skill in the art. I understand that for a single reference or a combination of
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`references to anticipate the claimed invention, a person of ordinary skill in the art
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`Inter Partes Review of U.S.P. 7,99409 (cid:9)
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`must have been able to arrive at the claims by altering or combining the applied
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`-7-
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`references.
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`17.
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`I also understand that when considering the obviousness of a patent
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`claim, one should consider whether a teaching, suggestion, or motivation to
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`combine the references exists so as to avoid impermissibly applying hindsight
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`when considering the prior art. I understand this test should not be rigidly applied,
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`but that the test can be important to avoid such hindsight.
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`III. Summary of Opinions
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`18.
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`I have reviewed Patent Owner’s Response including the Declaration
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`of Dr. Blanchard dated May 7, 2013 and the deposition of Dr. Blanchard on
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`August 9, 2013, Patent Owner’s Expert. As discussed below and in my first
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`Declaration, in my opinion claims 1-19 are unpatentable.
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`III. Claim 2
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`19.
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`I disagree with Patent Owner’s position that Anthony does not
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`disclose a shield plate implemented with polysilicon. I have reproduced FIG. 3B of
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`Anthony below. I note that Anthony at 4:49-52 states: "[a]s an alternative to the
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`use of a metal layer as shown in FIG. 3B. . .the bottom shield plate 36 can be
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`implemented with a polysilicon or diffusion layer." In my opinion, this portion of
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`Anthony states that bottom shield plate 36 can be formed in a poly layer.
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`39
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`39
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`37
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`FIG. 38
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`20. I have reproduced FIG. 8 of Paul below. As I explained in my first
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`Declaration, one of ordinary skill in the art in 2008 would have been able to form
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`metal layer 1 in a poly layer instead of a metal layer. (IVM1002, ¶
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`50.) In
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`particular, a number of different computer-aided design tools were available in
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`2008 that would have enabled one of ordinary skill in the art to design the
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`capacitor shown in FIG. 8 of Paul with metal layer 1 replaced with a poly layer.
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`One of ordinary skill in the art would want to make this modification for a number
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`of different reasons. For example, a designer may face constraints on the number
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`of metal layers that can be used. Using a poly layer instead of a metal layer would
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`save a metal layer that can be used for another purpose.
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`S
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`080 -.
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`METAL 4-
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`r (cid:9)
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`812 (cid:9)
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`- 814
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`A (cid:9)
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`888
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`! (cid:9) II
`Al
`6! (cid:9)
`L_J
`L (cid:9)
`
`r (cid:9)
`
`ri
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`LJ
`
`r (cid:9)
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`L9k L (cid:9)
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`II (cid:9) II (cid:9)
`161 (cid:9)
`IAI (cid:9)
`A (cid:9)
`L (cid:9)
`8; L (cid:9)
`814
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`MErAL
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`MET8L2-. A (cid:9)
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`814
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`METAL 1-.l A (cid:9)
`8 (cid:9)
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`ri (cid:9)
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`Li (cid:9)
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`6
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`818
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`FIG. 8
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`III. Claim 8
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`21. I also disagree with Patent Owner’s position that claim 8 requires
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`"adjacent" conductive elements to be in the same layer. In my opinion, nothing in
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`claim 8 requires that all of the conductive elements in the second conductive layer
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`are connected to the same node. Having reviewed FIG. 2B of the ’609 Patent,
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`which I have reproduced below, it is my understanding that BI, B2 of layer M3
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`and element B5 of layer Ml are all "adjacent" to element T of layer M2. In my
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`opinion, one of ordinary skill in the art would appreciate that one element can be
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`"adjacent" to another element without being in the same layer, e.g., by being
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`directly above or below the other element.
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`225(cid:151)
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`I (cid:9)
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`I
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`IBL
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`Mb (cid:9)
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`I (cid:9)
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`M4
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`M3 238
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`242 (cid:9)
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`222 (cid:9)
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`Ml (cid:9)
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`Poly (cid:9)
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`N. (cid:9)
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`Substrate
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`-10-
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`V,o Shed
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`203 (cid:9)
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`201 (cid:9)
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`220
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`AK-
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`T (cid:9)
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`
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`hLIl
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`V-u Shield (N-well)
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`FIG. 2B
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`22.
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`I understand that Patent Owner defines an "unbalanced" capacitor as
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`one that has more conducting elements connected to one node than the other. I
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`disagree with Patent Owner that Paul only discloses "balanced" capacitors. In my
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`opinion, Paul discloses both "balanced" and "unbalanced" capacitors. For example,
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`FIG. 5 of Paul, which has an equal number of conductive elements coupled to
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`Nodes A and B appears to be a "balanced" capacitor. On the other hand, FIG. 8 has
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`more conductive elements coupled to Node A than to Node B by virtue of side
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`shield 812. If side shield 812 is sufficiently close to elements 804 and 806 located
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`to its right so as to contribute to the total capacitance of the capacitor, then FIG. 8
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`is an "unbalanced" capacitor.
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`23.
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`Patent Owner further attempted to distinguish claim 8 from Paul by
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`arguing that claim 8 requires an unbalanced capacitor that serves as a "switching
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`capacitor." In my opinion, this argument has no merit. Whether a capacitor is a
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`"switching" capacitor depends on whether it is coupled to a switch, not whether it
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`is balanced or unbalanced. As Dr. Blanchard states, switching capacitors add to or
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`subtract from the capacitance of a circuit based on the state of a switch coupled to
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`the capacitor. (Blanchard Deposition, 84:1-11.) For example, in FIG. 1 of the ’609
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`Patent, reproduced below, capacitor 104 is configured as a switching capacitor.
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`(See Blanchard Deposition, 84:1-11.)
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`119
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`I
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`FIG. I
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`Both a balanced and an unbalanced capacitor can be used for this application,
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`albeit with certain performance differences. The performance differences are
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`predictable.
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`24. I further note that both the capacitors shown in Paul and the capacitor
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`shown in FIG. G of my first Declaration function as capacitors. In my opinion, the
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`possibility of changing a "balanced" capacitor to an "unbalanced" capacitor would
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`not discourage one skilled in the art from combining Paul and Brennan to form the
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`capacitor shown in FIG. G of the First Johnson Declaration.
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`IV. Proposed Claims 22-29
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`25. Having reviewed Paul, Anthony, Hseuh, and Brennan, it is my
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`opinion that one of ordinary skill in the art would have been able to combine the
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`features of these references. For example, designers had a number of computer-
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`aided design tools that allowed designers to both modify layouts of existing
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`capacitors and to simulate the results of any of these modifications.
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`V. Proposed Claim 30
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`26. I understand that Xilinx has proposed the following substitute claim
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`30:
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`A capacitor in an integrated circuit ("IC")
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`comprising:
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`a core capacitor portion having a first plurality of
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`conductive elements electrically connected to and
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`forming a first part of a first node of the capacitor formed
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`in a first conductive layer of the IC and a second plurality
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`of conductive elements electrically connected to and
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`forming a first part of a second node of the capacitor
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`formed in the first conductive layer, the first plurality of
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`conductive elements alternating with the second plurality
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`of conductive elements in the first conductive layer, and
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`a third plurality of conductive elements electrically
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`connected to and forming a second part of the first node
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`formed in a second conductive layer adjacent to the first
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`conductive layer, at least portions of some of the second
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`plurality of conductive elements overlying and vertically
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`coupling to at least portions of some of the third plurality
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`of conductive elements;
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`a shield capacitor portion having a fourth plurality
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`of conductive elements formed in at least the first
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`conductive layer of the IC, the second conductive layer
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`of the IC, a third conductive layer of the IC, and a fourth
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`conductive poly layer of the IC, the first conductive layer
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`and the second conductive layer each being between the
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`third conductive layer and the fourth poly conductive
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`layer, the shield capacitor portion being electrically
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`connected to and forming a second part of the second
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`node of the capacitor and surrounding the first plurality
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`of conductive elements and the third plurality of
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`conductive elements, and
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`a reference shield electrically connected to a
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`reference node of the IC other than the second node of
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`the capacitor, the shield capacitor portion being disposed
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`between the reference shield and the core capacitor
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`portion, wherein the reference shield includes a substrate
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`portion of a substrate of the IC, a first conductive curtain
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`extending from the substrate portion, and a second
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`conductive curtain extending from the substrate portion.
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`27.
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`In my opinion proposed substitute claim 30 would have been obvious
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`to one skilled in the art in view of Paul and Anthony.
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`28.
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`For example, the capacitor shown in FIG. D.2 of my first Declaration,
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`which shows the capacitor of Paul modified according to Anthony, illustrates all of
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`the limitations of proposed claim 30 except for the "fourth layer," i.e., the layer
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`including bottom shield plate 810, being a poly layer.
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`29.
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`In my opinion it would have been obvious to form the "fourth layer"
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`in a poly layer. Anthony states that bottom shield plate 36 can be formed out of a
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`poly layer. Anthony, 4:49-52. In view of this disclosure, it would have been
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`obvious to similarly form the "fourth layer" in a "poly" layer. Indeed, as I
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`explained in my first Declaration, a person of ordinary skill in the art would have
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`known about "double poly" processes that can be used to form two layers of a
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`capacitor out of poly. First Johnson Declaration, ¶ 88. This process could also be
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`used to form both the layer including bottom shield plate 36 and the "fourth layer"
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`out of poly. Forming the "fourth layer" out of poly would lead to predictable
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`changes in the capacitor. One of ordinary skill in the art would have been able to
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`predict and accommodate those changes using design tools available in 2008. This
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`change to the capacitor shown in FIG. D.2 of my first Declaration would save a
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`conductive layer for another purpose.
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`30. In my opinion, proposed substitute claim 30 would also have been
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`obvious over Anthony in view of Bi. In view of Anthony’s disclosure that bottom
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`shield plate 36 could be formed in a poly layer or a metal layer (4:49-52), one of
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`ordinary skill in the art would be able to form the plate 24 of FIG. 2B of Anthony
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`out of a poly layer. As I explain above, design tools were available to one of
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`ordinary skill in the art in 2008 that would allow a designer to design plate 24 out
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`of poly instead of metal. Further, one of ordinary skill in the art would have been
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`motivated to make form the "fourth layer" of FIG. 2B of Anthony out of poly to
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`save a metal layer.
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`XI. Conclusion
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`31. I hereby declare that all statements made herein of my own
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`knowledge are true and that all statements made on information and belief are
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`believed to be true; and further that these statements were made with the
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`knowledge that willful false statements and the like so made are punishable by fine
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`or imprisonment, or both, under Section 1001 of Title 18 of the United States
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`Code.
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`Executed on August 23, 2013 at Portland, Oregon.
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