UNITED STATES PATENT AND TRADEMARK OFFICE
`
`1013
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTELLECTUAL VENTURES MANAGEMENT, LLC
`
`Petitioner
`
`V.
`
`XILINX, INC.
`
`Patent Owner
`
`Case 1PR2012-00023
`
`Patent 7,994,609
`
`SECOND DECLARATION OF MORGAN T. JOHNSON
`IN SUPPORT OF INTELLECTUAL VENTURES MANAGEMENT, LLC’S
`REPLY TO PATENT OWNER’S RESPONSE
`
`
`
`1013
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTELLECTUAL VENTURES MANAGEMENT, LLC
`
`Petitioner
`
`V.
`
`XILINX, INC.
`
`Patent Owner
`
`Case 1PR2012-00023
`
`Patent 7,994,609
`
`SECOND DECLARATION OF MORGAN T. JOHNSON
`IN SUPPORT OF INTELLECTUAL VENTURES MANAGEMENT, LLC’S
`REPLY TO PATENT OWNER’S RESPONSE
`
`
`
`I, Morgan Johnson, declare as follows:
`
`-2-
`
`1.
`
`I have been retained by Sterne, Kessler, Goldstein, and Fox PLLC on
`
`behalf of Intellectual Ventures Management, LLC ("Intellectual Ventures
`
`Management") for the above-captioned
`
`inter partes review proceeding. I
`
`understand that this proceeding involves U.S. Patent No. 7,994,609 ("the ’609
`
`Patent") entitled "Shielding for Integrated Capacitors," and that the ’609 Patent is
`
`currently assigned to Xilinx, Inc.
`
`2.
`
`I have reviewed and am familiar with the specification of the ’609
`
`Patent filed on November 21, 2008 and issued on August 9, 2011. A copy of the
`
`’609 Patent is provided as IVM 1001. I will cite to the specification using the
`
`following format: (’609 Patent, 1:1-10). This example citation points to the ’609
`
`patent specification at column 1, lines 1-10.
`
`3.
`
`I have reviewed and am familiar with U.S. Patent No. 6,737,698 to
`
`Paul et al. (hereinafter "Paul"), U.S. Patent No. 7,439,570 to Anthony (hereinafter
`
`"Anthony"), U.S. Patent No. 7,286,071 to Hsueh et al. (hereinafter "Hsueh"), U.S.
`
`Patent No. 6,903,918 to Brennan (hereinafter "Brennan"), U.S. Patent No.
`
`7,238,981 to Marotta (hereinafter "Marotta"), and U.S. Patent Application
`
`Publication No. 2008/0128857 to Bi (hereinafter "Bi").
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`Inter Partes Review of U.S.P. 7 9994,609 (cid:9)
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`3059.70 1IPRO
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`4.
`
`I am familiar with the technology at issue as of the November 21,
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`-3-
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`2008 filing date of the ’609 Patent.
`
`5.
`
`I have been asked to provide my technical review, analysis, insights,
`
`and opinions regarding the above-noted references that form the basis for the
`
`grounds of rejection set forth in the Petition for
`
`Inter Partes Review of the ’609
`
`Patent.
`
`I. (cid:9)
`
`Qualifications
`
`6.
`
`I have more than 29 years of experience in the electronic interconnect
`
`and semiconductor industries.
`
`7.
`
`I earned a Bachelor of Science degree in Graphics from the University
`
`of Oregon. My studies included subjects in advanced mathematics related to
`
`geodesic domes. I also attended The Art Center College of Design in Pasadena,
`
`California, where I majored in Industrial Design.
`
`8.
`
`I currently serve as Chief Scientist at Advanced Inquiry Systems, Inc.
`
`(AISI), a company that I founded in 2003. As Chief Scientist, my research focuses
`
`on tools and interfaces for full-wafer testing of products such as NAND and NOR
`
`flash, Dynamic Random Access Memory (DRAM), and certain logic devices. My
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`research is additionally driven by the semiconductor industry’s demand for highly-
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`Inter Partes Review of U.S.P. 719949609 (cid:9)
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`3059.70 1IPRO
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`parallel wafer testing of System-on-Chips (SOCs), such as processors for mobile
`
`devices. Through my research, AISI has implemented a device that achieves
`
`contact with up to 500,000 pads per wafer during tests. AISI was founded on my
`
`patented work in this area and benefits from over 30 issued patents.
`
`9.
`
`I co-founded Prototype Solutions Corporation in 1994, a company
`
`focused on using advanced interconnect and packaging technology to provide
`
`quick-turn prototypes and hardware emulation using programmable logic devices
`
`such as Field Programmable Gate Arrays (FPGAs). The technology is used to
`
`prototype highly-complex Central Processing Units (CPUs), Graphic Processing
`
`Units (GPUs), System on Chips (SOCs), and Application Specific Integrated
`
`Circuits (ASICs).
`
`10.
`
`I founded LaserPath Corp. in 1983. Laserpath was a semiconductor
`
`company focused on laser programmable semiconductor gate arrays. The
`
`foundation of this technology was based on my inventions and patents. LaserPath
`
`achieved over 200 design wins in the first 9 months of sales(cid:151)setting a record.
`
`LaserPath’s technology included Gate Arrays programmed with a laser in a
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`ceramic package, tested, and delivered to customer in as little as two hours and
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`more typically within 5 business days. This rapid Gate Array turnaround time and
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`Inter Partes Review of U.S.P. 7,994 9609 (cid:9)
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`3059.70 1IPRO
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`-5-
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`large number of design wins drastically shifted the ASIC business from a 12-week
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`delivery to a new standard of 3- week delivery.
`
`11.
`
`From 1981 to 1982, I researched controlled impedance, instant turn-
`
`around circuit boards for the Cray 2 computer system. My research was funded by
`
`Cray Computer Corporation(cid:151)Boulder, Colorado Team. This research was the
`
`genesis for my later-developed technology that evolved into LaserPath.
`
`12.
`
`In addition to my semiconductor industry experience, I am an inventor
`
`on 36 U.S. patents related to interconnects, high-speed connectors, and
`
`semiconductors. Also, I have a faculty appointment as Adjunct Professor in the
`
`Electrical Engineering School at Portland State University in Portland, Oregon. I
`
`have also been a guest lecturer at the Jet Propulsion Laboratory (JPL) in Pasadena,
`
`California.
`
`13.
`
`I have provided testimony in the form of a declaration in three other
`
`inter partes review proceedings:
`
`. Intellectual Ventures Management, LLC v. Xilinx, Inc., Case
`
`1PR2012-00018.
`
`Inter Partes Review of U.S.P. 7,994,609 (cid:9)
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`3059.70 1IPRO
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`. Intellectual Ventures Management, LLC v. Xilinx, Inc., Case
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`SUM
`
`1PR2012-00019.
`
`. Intellectual Ventures Management, LLC v. Xilinx, Inc., Case
`
`IPR20 12-00020.
`
`14. My Curriculum Vitae is attached as Exhibit IVM1 015, which contains
`
`further details on my education, experience, publications, patents, and other
`
`qualifications to render an expert opinion. My work on this case is being billed at
`
`a rate of $300.00 per hour, with reimbursement for actual expenses. My
`
`compensation is not contingent upon the outcome of this inter partes review.
`
`II. My Understanding of Obviousness
`
`15.
`
`It is my understanding that a claimed invention is unpatentable if the
`
`differences between the invention and the prior art are such that the subject matter
`
`as a whole would have been obvious at the time the invention was made to a
`
`person having ordinary skill in the art to which the subject matter pertains.
`
`16.
`
`It is my understanding that "obviousness" is a question of law based
`
`on underlying factual issues including the content of the prior art and the level of
`
`skill in the art. I understand that for a single reference or a combination of
`
`references to anticipate the claimed invention, a person of ordinary skill in the art
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`Inter Partes Review of U.S.P. 7,99409 (cid:9)
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`3059.70 1IPRO
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`must have been able to arrive at the claims by altering or combining the applied
`
`-7-
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`references.
`
`17.
`
`I also understand that when considering the obviousness of a patent
`
`claim, one should consider whether a teaching, suggestion, or motivation to
`
`combine the references exists so as to avoid impermissibly applying hindsight
`
`when considering the prior art. I understand this test should not be rigidly applied,
`
`but that the test can be important to avoid such hindsight.
`
`III. Summary of Opinions
`
`18.
`
`I have reviewed Patent Owner’s Response including the Declaration
`
`of Dr. Blanchard dated May 7, 2013 and the deposition of Dr. Blanchard on
`
`August 9, 2013, Patent Owner’s Expert. As discussed below and in my first
`
`Declaration, in my opinion claims 1-19 are unpatentable.
`
`III. Claim 2
`
`19.
`
`I disagree with Patent Owner’s position that Anthony does not
`
`disclose a shield plate implemented with polysilicon. I have reproduced FIG. 3B of
`
`Anthony below. I note that Anthony at 4:49-52 states: "[a]s an alternative to the
`
`use of a metal layer as shown in FIG. 3B. . .the bottom shield plate 36 can be
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`Inter Partes Review of U.S.P. 7 1994,609 (cid:9)
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`3059.701IPRO
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`implemented with a polysilicon or diffusion layer." In my opinion, this portion of
`
`Anthony states that bottom shield plate 36 can be formed in a poly layer.
`
`39
`
`39
`
`37
`
`FIG. 38
`
`20. I have reproduced FIG. 8 of Paul below. As I explained in my first
`
`Declaration, one of ordinary skill in the art in 2008 would have been able to form
`
`metal layer 1 in a poly layer instead of a metal layer. (IVM1002, ¶
`
`50.) In
`
`particular, a number of different computer-aided design tools were available in
`
`2008 that would have enabled one of ordinary skill in the art to design the
`
`capacitor shown in FIG. 8 of Paul with metal layer 1 replaced with a poly layer.
`
`One of ordinary skill in the art would want to make this modification for a number
`
`of different reasons. For example, a designer may face constraints on the number
`
`of metal layers that can be used. Using a poly layer instead of a metal layer would
`
`save a metal layer that can be used for another purpose.
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`Inter Partes Review of U.S.P. 7 999409 (cid:9)
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`3059.70 1IPRO
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`S
`
`080 -.
`
`METAL 4-
`
`r (cid:9)
`
`812 (cid:9)
`
`- 814
`
`A (cid:9)
`
`888
`
`! (cid:9) II
`Al
`6! (cid:9)
`L_J
`L (cid:9)
`
`r (cid:9)
`
`ri
`
`LJ
`
`r (cid:9)
`
`L9k L (cid:9)
`
`II (cid:9) II (cid:9)
`161 (cid:9)
`IAI (cid:9)
`A (cid:9)
`L (cid:9)
`8; L (cid:9)
`814
`
`MErAL
`
`MET8L2-. A (cid:9)
`
`814
`
`METAL 1-.l A (cid:9)
`8 (cid:9)
`
`ri (cid:9)
`
`Li (cid:9)
`
`6
`
`818
`
`FIG. 8
`
`III. Claim 8
`
`21. I also disagree with Patent Owner’s position that claim 8 requires
`
`"adjacent" conductive elements to be in the same layer. In my opinion, nothing in
`
`claim 8 requires that all of the conductive elements in the second conductive layer
`
`are connected to the same node. Having reviewed FIG. 2B of the ’609 Patent,
`
`which I have reproduced below, it is my understanding that BI, B2 of layer M3
`
`and element B5 of layer Ml are all "adjacent" to element T of layer M2. In my
`
`opinion, one of ordinary skill in the art would appreciate that one element can be
`
`"adjacent" to another element without being in the same layer, e.g., by being
`
`directly above or below the other element.
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`Inter Partes Review of U.S.P. 7,99409 (cid:9)
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`3059.70 1IPRO
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`
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`225(cid:151)
`
`I (cid:9)
`
`I
`
`IBL
`
`Mb (cid:9)
`
`I (cid:9)
`
`M4
`
`M3 238
`
`242 (cid:9)
`
`222 (cid:9)
`
`Ml (cid:9)
`
`Poly (cid:9)
`
`N. (cid:9)
`
`Substrate
`
`-10-
`
`V,o Shed
`
`203 (cid:9)
`
`201 (cid:9)
`
`220
`
`AK-
`
`T (cid:9)
`
`
`
`hLIl
`
`V-u Shield (N-well)
`
`FIG. 2B
`
`22.
`
`I understand that Patent Owner defines an "unbalanced" capacitor as
`
`one that has more conducting elements connected to one node than the other. I
`
`disagree with Patent Owner that Paul only discloses "balanced" capacitors. In my
`
`opinion, Paul discloses both "balanced" and "unbalanced" capacitors. For example,
`
`FIG. 5 of Paul, which has an equal number of conductive elements coupled to
`
`Nodes A and B appears to be a "balanced" capacitor. On the other hand, FIG. 8 has
`
`more conductive elements coupled to Node A than to Node B by virtue of side
`
`shield 812. If side shield 812 is sufficiently close to elements 804 and 806 located
`
`to its right so as to contribute to the total capacitance of the capacitor, then FIG. 8
`
`is an "unbalanced" capacitor.
`
`23.
`
`Patent Owner further attempted to distinguish claim 8 from Paul by
`
`arguing that claim 8 requires an unbalanced capacitor that serves as a "switching
`
`Inter Partes Review of U.S.P. 7 1,9941609 (cid:9)
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`3059.70 1IPRO
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`(cid:9)
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`-11-
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`capacitor." In my opinion, this argument has no merit. Whether a capacitor is a
`
`"switching" capacitor depends on whether it is coupled to a switch, not whether it
`
`is balanced or unbalanced. As Dr. Blanchard states, switching capacitors add to or
`
`subtract from the capacitance of a circuit based on the state of a switch coupled to
`
`the capacitor. (Blanchard Deposition, 84:1-11.) For example, in FIG. 1 of the ’609
`
`Patent, reproduced below, capacitor 104 is configured as a switching capacitor.
`
`(See Blanchard Deposition, 84:1-11.)
`
`119
`
`I
`
`FIG. I
`
`Both a balanced and an unbalanced capacitor can be used for this application,
`
`albeit with certain performance differences. The performance differences are
`
`predictable.
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`Inter Partes Review of U.S.P. 7 99945609 (cid:9)
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`3059.701IPRO
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`wpm
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`24. I further note that both the capacitors shown in Paul and the capacitor
`
`shown in FIG. G of my first Declaration function as capacitors. In my opinion, the
`
`possibility of changing a "balanced" capacitor to an "unbalanced" capacitor would
`
`not discourage one skilled in the art from combining Paul and Brennan to form the
`
`capacitor shown in FIG. G of the First Johnson Declaration.
`
`IV. Proposed Claims 22-29
`
`25. Having reviewed Paul, Anthony, Hseuh, and Brennan, it is my
`
`opinion that one of ordinary skill in the art would have been able to combine the
`
`features of these references. For example, designers had a number of computer-
`
`aided design tools that allowed designers to both modify layouts of existing
`
`capacitors and to simulate the results of any of these modifications.
`
`V. Proposed Claim 30
`
`26. I understand that Xilinx has proposed the following substitute claim
`
`30:
`
`A capacitor in an integrated circuit ("IC")
`
`comprising:
`
`a core capacitor portion having a first plurality of
`
`conductive elements electrically connected to and
`
`forming a first part of a first node of the capacitor formed
`3059.70 1IPRO
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`Inter Partes Review of U.S.P. 7,99409 (cid:9)
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`- 13 -
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`in a first conductive layer of the IC and a second plurality
`
`of conductive elements electrically connected to and
`
`forming a first part of a second node of the capacitor
`
`formed in the first conductive layer, the first plurality of
`
`conductive elements alternating with the second plurality
`
`of conductive elements in the first conductive layer, and
`
`a third plurality of conductive elements electrically
`
`connected to and forming a second part of the first node
`
`formed in a second conductive layer adjacent to the first
`
`conductive layer, at least portions of some of the second
`
`plurality of conductive elements overlying and vertically
`
`coupling to at least portions of some of the third plurality
`
`of conductive elements;
`
`a shield capacitor portion having a fourth plurality
`
`of conductive elements formed in at least the first
`
`conductive layer of the IC, the second conductive layer
`
`of the IC, a third conductive layer of the IC, and a fourth
`
`conductive poly layer of the IC, the first conductive layer
`
`and the second conductive layer each being between the
`
`third conductive layer and the fourth poly conductive
`
`layer, the shield capacitor portion being electrically
`
`connected to and forming a second part of the second
`
`node of the capacitor and surrounding the first plurality
`
`of conductive elements and the third plurality of
`
`conductive elements, and
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`Inter Partes Review of U.S.P. 7 9994,609 (cid:9)
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`- 14 -
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`a reference shield electrically connected to a
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`reference node of the IC other than the second node of
`
`the capacitor, the shield capacitor portion being disposed
`
`between the reference shield and the core capacitor
`
`portion, wherein the reference shield includes a substrate
`
`portion of a substrate of the IC, a first conductive curtain
`
`extending from the substrate portion, and a second
`
`conductive curtain extending from the substrate portion.
`
`27.
`
`In my opinion proposed substitute claim 30 would have been obvious
`
`to one skilled in the art in view of Paul and Anthony.
`
`28.
`
`For example, the capacitor shown in FIG. D.2 of my first Declaration,
`
`which shows the capacitor of Paul modified according to Anthony, illustrates all of
`
`the limitations of proposed claim 30 except for the "fourth layer," i.e., the layer
`
`including bottom shield plate 810, being a poly layer.
`
`29.
`
`In my opinion it would have been obvious to form the "fourth layer"
`
`in a poly layer. Anthony states that bottom shield plate 36 can be formed out of a
`
`poly layer. Anthony, 4:49-52. In view of this disclosure, it would have been
`
`obvious to similarly form the "fourth layer" in a "poly" layer. Indeed, as I
`
`explained in my first Declaration, a person of ordinary skill in the art would have
`
`known about "double poly" processes that can be used to form two layers of a
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`Inter Partes Review of U.S.P. 7,994,609 (cid:9)
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`- 15 -
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`capacitor out of poly. First Johnson Declaration, ¶ 88. This process could also be
`
`used to form both the layer including bottom shield plate 36 and the "fourth layer"
`
`out of poly. Forming the "fourth layer" out of poly would lead to predictable
`
`changes in the capacitor. One of ordinary skill in the art would have been able to
`
`predict and accommodate those changes using design tools available in 2008. This
`
`change to the capacitor shown in FIG. D.2 of my first Declaration would save a
`
`conductive layer for another purpose.
`
`30. In my opinion, proposed substitute claim 30 would also have been
`
`obvious over Anthony in view of Bi. In view of Anthony’s disclosure that bottom
`
`shield plate 36 could be formed in a poly layer or a metal layer (4:49-52), one of
`
`ordinary skill in the art would be able to form the plate 24 of FIG. 2B of Anthony
`
`out of a poly layer. As I explain above, design tools were available to one of
`
`ordinary skill in the art in 2008 that would allow a designer to design plate 24 out
`
`of poly instead of metal. Further, one of ordinary skill in the art would have been
`
`motivated to make form the "fourth layer" of FIG. 2B of Anthony out of poly to
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`save a metal layer.
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`Inter Partes Review of U.S.P. 7,994 1609 (cid:9)
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`XI. Conclusion
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`- 16 -
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`31. I hereby declare that all statements made herein of my own
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`knowledge are true and that all statements made on information and belief are
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`believed to be true; and further that these statements were made with the
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`knowledge that willful false statements and the like so made are punishable by fine
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`or imprisonment, or both, under Section 1001 of Title 18 of the United States
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`Code.
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`Executed on August 23, 2013 at Portland, Oregon.
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`Inter Partes Review of U.S.P. 7,994,609 (cid:9)
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`3059.701IPRO
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