throbber
Blanchard Decl.
`
`IPR20 12-00023
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTELLECTUAL VENTURES MANAGEMENT, LLC
`
`Petitioner
`
`V.
`
`Patent of XILINX, INC.
`
`Patent Owner
`
`Case IPR20l2—00023
`
`Patent 7,994,609
`
`Title: SHIELDING FOR INTEGRATED CAPACITORS
`
`
`DECLARATION OF RICHARD A. BLANCHARD PH.D.
`
`UNDER 37 C.F.R.
`
`1.68
`
`1, Richard Blanchard, do hereby declare:
`
`1.
`
`I am making this declaration at the request of Xilinx, Inc. in the matter
`
`of the Inter Partes Review of U.S. Patent No 7,994,609 (“the ’609 Patent”) to
`
`Quinn, initiated by petitioner Intellectual Ventures Management, LLC (IVM).
`
`2.
`
`In the preparation of this declaration, I have studied:
`
`(1)
`
`The Petition for Inter Parte Review (“Petition”), Paper 3;
`
`—l—
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR2012—00023
`
`(2)
`
`The ’609 Patent, IVM—1001;
`
`(3)
`
`The prosecution history of the ’609 Patent, IVM—1003 — 1005;
`
`(4)
`
`U.S. Patent No. 6,737,698 (“Paul”), IVM—1006;
`
`(5)
`
`U.S. Patent No. 7,439,570 (“Anthony”), IVM—1007;
`
`(6)
`
`U.S. Patent No. 7,286,071 (“Hsueh”), IVM—1008;
`
`(7)
`
`U.S. Patent No. 6,903,918 (“Brennan”), IVM— 1009;
`
`(8)
`
`U.S. Pub. No. 2008/0128857 (“Bi”), IVM1010;
`
`(9)
`
`U.S. Patent No. 7,238,981 (“Marotta”), IVM— 101 1;
`
`(10) Declaration of Morgan Johnson, IVM—1002; and
`
`(11) The Decision entered Feb. 12, 2013 (“Decision”), Paper 11.
`
`3.
`
`In forming the opinions expressed below, I have considered:
`
`(1)
`
`The documents listed above,
`
`(2)
`
`The relevant legal standards, including the standard for obviousness
`
`provided in KSR International Co. v. Teleflex, Inc., 550 U.S. 398 (2007) and
`
`any additional authoritative documents as cited in the body of this
`
`declaration, and
`
`(3) My knowledge and experience based upon my work in this area as
`
`described below.
`
`—2—
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR2012—00023
`
`4.
`
`I am familiar with and am a practitioner of the technology at issue and
`
`am aware of the state of the art at the time the application leading to the ’609
`
`Patent was filed. The earliest priority date is November 21, 2008. Based on the
`
`technologies disclosed in the ’609 Patent, I believe that one of ordinary skill in the
`
`art would include someone who has a B.S. degree in Electrical Engineering or
`
`equivalent training, as well as 3-5 years of experience in the field of integrated
`
`circuit device design and layout and semiconductor fabrication technology .
`
`Unless otherwise stated, when I give my understanding and analysis below, it is
`
`consistent with the level of one of ordinary skill in these technologies at and
`
`around the filing date of the ‘609 patent.
`
`5.
`
`I am a consultant for Thomson Reuters Expert Witness Services
`
`(formerly known as Silicon Valley Expert Witness Group), a consulting company
`
`specializing in expert witness litigation support and technology consulting. I also
`
`provide technical consulting services to the semiconductor and electronics industry
`
`through Blanchard Associates.
`
`6.
`
`My academic credentials include both a Bachelor of Science
`
`Degree in Electrical Engineering (BSEE) and a Master of Science Degree in
`
`Electrical Engineering (MSEE) from the Massachusetts Institute of
`
`Technology in 1968 and 1970, respectively.
`
`I subsequently obtained a Ph.D.
`
`-3-
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR20 12-00023
`
`in Electrical Engineering in 1982 from Stanford University.
`
`7.
`
`My professional background and technical qualifications are stated
`
`above and are also reflected in my Curriculum Vitae, which is attached as XLNX—
`
`2007. I am being compensated at a rate of $275.00 per hour, with reimbursement
`
`for actual expenses, for my work related to this Petition for Inter Partes Review.
`
`My compensation is not dependent on and in no way affects the substance of my
`
`statements in this Declaration.
`
`8.
`
`I have worked or consulted for more than 40 years as an
`
`Electrical Engineer. My primary focus has been on the development,
`
`manufacture, operation, and use of devices and integrated circuits, the
`
`assembly of these devices and integrated circuits, products that use them,
`
`and their failures. My employment history following my graduation from
`
`MIT began at Fairchild Semiconductor in 1970. At Fairchild, my
`
`responsibilities included circuit and device design, process development, and
`
`product engineering in the Linear Integrated Circuits Department.
`
`9.
`
`In 1974, I joined Foothill College as an Associate Professor in
`
`the Engineering & Technology Division. My responsibilities included
`
`developing a program in Semiconductor Technology as well as teaching
`
`other courses in the division. While at Foothill College, I co—founded two
`
`-4-
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR20 12-00023
`
`companies, Cognition and Supertex, and later joined Supertex as a Vice
`
`President in 1978. At Supertex, I designed and developed discrete DMOS
`
`(double—diffused metal oxide semiconductor) transistors, as well as
`
`integrated circuits that contained DMOS transistors. At Supertex, I also
`
`supervised the in—house assembly area, which included responsibility for the
`
`associated manufacturing processes.
`
`10.
`
`I left Suptertex to join Siliconix in 1982, where I soon became
`
`Vice President of Engineering, with the responsibility for directing all of the
`
`company's product design and development. At Siliconix, I directed and
`
`contributed to the development of both discrete transistors and integrated
`
`circuits, including aspects of their assembly.
`
`11.
`
`In 1987, I joined IXYS Corporation as a Senior Vice President
`
`with the responsibility for organizing an integrated circuit department. At
`
`IXYS, I developed integrated circuits that contained DMOS devices or that
`
`interfaced to DMOS devices. My responsibilities included the design,
`
`assembly, and testing of these integrated circuits.
`
`12.
`
`These duties continued until 1991, when I left IXYS to set up
`
`Blanchard Associates, a consulting firm specializing in semiconductor
`
`technology, including intellectual property. Soon thereafter, I was invited to
`
`-5-
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR2012—00023
`
`join Failure Analysis Associates, which I did in late 1991. At Failure
`
`Analysis Associates, I investigated failures in electrical and electronic
`
`systems in addition to performing design and development consulting.
`
`13.
`
`I left Failure Analysis in 1998 to join IP Managers, which later
`
`merged with Silicon Valley Expert Witness Group, now known as Thomson
`
`Reuters Expert Witness Services ("Thomson Reuters"). At Thomson
`
`Reuters, I work with companies on patent and trade secret matters.
`
`I also
`
`consult for a number of semiconductor companies, working with them to
`
`develop products and intellectual property, or assisting them in other
`
`technical areas through Blanchard Associates. Design and Development
`
`projects that I have worked on range from the design and evaluation of
`
`specific components, to the selection of the technology appropriate for the
`
`fabrication of different subsystems of a system.
`
`14.
`
`I am a member of a number of professional societies, including
`
`the Institute of Electrical and Electronic Engineers, the International
`
`Microelectronics and Packaging Society, the American Vacuum Society, the
`
`Electronic Device Failure Analysis Society, and the Electrostatic Discharge
`
`Society.
`
`15. A copy of my curriculum vitae is attached as XLNX—2007.
`
`-6-
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR20 12-00023
`
`Additional information regarding my education, technical experience and
`
`publications, including a list of the US patents of which I am an inventor, is
`
`included therein.
`
`Relevant Legal Standards
`
`16.
`
`I have been asked to provide my opinions regarding whether the
`
`claims of the ’609 Patent are anticipated or would have been obvious to a person
`
`having ordinary skill in the art at the time of the alleged invention, in light of the
`
`prior art. It is my understanding that, to anticipate a claim under 35 U.S.C. § 102, a
`
`reference must teach every element of the claim. Further, it is my understanding
`
`that a claimed invention is unpatentable under 35 U.S.C. § 103 if the differences
`
`between the invention and the prior art are such that the subject matter as a whole
`
`would have been obvious at the time the invention was made to a person having
`
`ordinary skill in the art to which the subject matter pertains. I also understand that
`
`the obviousness analysis takes into account factual inquiries including the level of
`
`ordinary skill in the art, the scope and content of the prior art, and the differences
`
`between the prior art and the claimed subject matter.
`
`17.
`
`It is my understanding that the Supreme Court has recognized several
`
`rationales for combining references or modifying a reference to show obviousness
`
`of claimed subject matter. Some of these rationales include the following:
`
`—7—
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR20 12-00023
`
`combining prior art elements according to known methods to yield predictable
`
`results; simple substitution of one known element for another to obtain predictable
`
`results; use of a known technique to improve a similar device (method, or product)
`
`in the same way; applying a known technique to a known device (method, or
`
`product) ready for improvement to yield predictable results; choosing from a finite
`
`number of identified, predictable solutions, with a reasonable expectation of
`
`success; and some teaching, suggestion, or motivation in the prior art that would
`
`have led one of ordinary skill to modify the prior art reference or to combine prior
`
`art reference teachings to arrive at the claimed invention.
`
`18.
`
`It is my understanding that some claims can be interpreted as “means
`
`plus function” claims under 35 U.S.C. § 112, paragraph 6. I understand that
`
`determining the broadest reasonable interpretation of “means plus function”
`
`claims requires first, defining the particular function of the limitation and second,
`
`identifying the corresponding structure for that function in the specification. I also
`
`understand that structure disclosed in the specification is corresponding structure
`
`only if the specification or prosecution history clearly links or associates that
`
`structure to the function recited in the claim.
`
`Anthony
`
`19. Anthony teaches the use of shielding layers of metal that are
`
`-8-
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR2012-00023
`
`present below and above the inter-digitated fingers of the metal-to-metal
`
`capacitors. These shielding layers reduce the parasitic capacitance to ground,
`
`and shield one capacitor node from other circuit nodes. 3:50-63. Capacitors
`
`fabricated in this fashion are shown in FIGS. 3 and 4. FIG. 4 of Anthony is
`
`reproduced and annotated below.
`
`-
`
`— ' ' ;;f:;;"“
`
`{%'is\\\\\\\\\\\(\ \gf
`I4////////,<~.
`
`- — — capacitor
`
`'f A§
`
`§\XX\R\'§\
`
`‘4! W.&
`
`:: -;;:’§:::;"“
`
`Anthony, FIG. 4
`
`20. Anthony states that the capacitor 30 is formed by “plates 33 and 34”
`
`and “terminals 31 and 32.” 4:35-38. Plates 33 and 34 are formed in “additional
`
`layers of metal.” 423-4. The capacitor 30 of FIG. 4 is shielded by features
`
`including the metal plate 35, and the diffused layer 46. 4266-522. In other words,
`
`-9-
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR2012—00023
`
`Anthony’s capacitor in FIG. 4 has a first plate 33 and a second plate 34 where both
`
`plates are formed of metal layers overlying the substrate, not in poly or in the
`
`diffusion. Anthony’s reference shield plates 36/46 are formed in the metal layer
`
`(36) and in the diffusion layer (46), and are not connected to either node of the
`
`capacitor. Anthony does not teach a node of the conductor being in either the
`
`diffused layer or poly.
`
`Hsueh
`
`21. Hsueh teaches a system for displaying images by driving
`
`individual pixels of a display screen using thin film transistors. A two stage
`
`digital—to—analog converter that includes switched capacitors is part of the
`
`drive circuitry. 1:42-50.
`
`Brennan
`
`22. Brennan teaches a shielded planar capacitor. As shown in FIG. 2
`
`of Brennan, reproduced below, a capacitor has two nodes 106, 112, separated
`
`by a relatively thin dielectric 110. A shield is formed around the capacitor,
`
`and is separated from the capacitors by relatively thick dielectric layers
`
`104/114 having a small dielectric constant. The combination of a relatively
`
`thick dielectric layer and a small dielectric constant significantly reduces any
`
`capacitive coupling. 2:26-35.
`
`—10—
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR20 12-00023
`
`23.
`
`Brennan is directed to capacitors with only plate layers, and no layers
`
`with alternating conducting elements. The number of plate layers are always
`
`balanced between the two nodes. Brennan extolls the benefits of using only plate
`
`layers, stating that they “simplify planar capacitor fabrication at the metal
`
`interconnect layer and via layers.” 3:28-30. Brennan further describes the
`
`benefits of using “slotted” capacitor plates, including improved quality of planar
`
`capacitor plates and that the trace and slot widths in a plate layer provide “filtering
`
`of relatively high frequency EMI noise.” 6:58—7:9.
`
`,2,
`
`},
`
`/10210335
`:5 J‘:"—-q.1«,:<-.;/in-v;..-;»5.«
`
`
`
`235
`
`
`
`
`,,\
`
`112
`
`,u-,.-,».,.
`
`
`
`236
`
` 106
`
`
`
`
`24.
`
`Bi shows the use of a multi—finger capacitor fabricated using a
`
`number of metal layers in an IC. The fingers connected to the input node are
`
`interleaved with the fingers connected to the output node. A conductive layer
`
`or plate below the bottom layer of interleaved fingers ia also connected to the
`
`—l l—
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR20 12-00023
`
`input node between the substrate and the first and second layer of fingers,
`
`reducing the parasitic capacitance of the output node.
`
`‘][l8.
`
`Marotta
`
`25. Marotta teaches integrated capacitor structures that include the use
`
`of a doped region of silicon in the capacitor structure. Both a single layer of
`
`poly above a doped layer of silicon (Fig. 3) and an inter—digitated metal
`
`capacitor above a doped layer of silicon and below a second metal layer (Figs.
`
`5 and 5A) are included. Marotta does not teach a node of the capacitor being in
`
`either the diffused layer or poly.
`
`Paul
`
`26.
`
`Paul is directed to capacitors, including structures with top and bottom
`
`shields, each tied to a different node of the capacitor. 2:37-48. A capacitor
`
`structure that includes both a top shield and a side shield that are connected
`
`together is also present. Fig. 8. Paul is directed to a balanced capacitor, in which
`
`the number of plates or conducting elements are always balanced between the two
`
`nodes. Paul does not disclose that the shield capacitor portion is a poly layer of the
`
`IC or that a second node shield is formed in the poly layer.
`
`27. Also, Paul does not teach a plate layer having a plurality of
`
`conducting elements connected to a common node. Specifically, Paul’s FIG. 13
`
`-12-
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR20 12-00023
`
`teaches two interior layers having a plurality of conducting elements, the layers in
`
`Metal 3 and Metal 2. FIG. 13 of Paul is reproduced below.
`
`In both these interior
`
`layers, the conducting elements alternate between node A and node B. There is no
`
`interior layer of conducting elements that do not alternate (a plate layer).
`
`METAL 1-+
`
`alternating
`conductive elements
`
`Discussion Of ’609 Patent
`
`28.
`
`The ‘609 patent is directed to a capacitor, and more specifically, to
`
`shielding for a capacitor in an integrated circuit. Title. The background section of
`
`the patent discusses how capacitors are used for many different purposes in an IC,
`
`one example being in a switching circuit. An example switching circuit is
`
`provided in FIG. 1 of the patent.
`
`29.
`
`For the sake of example, claims 1-2 of the ‘609 patent are reproduced
`
`below:
`
`— l 3-
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR20 12-00023
`
`1. A capacitor in an integrated circuit ("IC") comprising:
`
`a core capacitor portion having a first plurality of conductive elements
`
`electrically connected to and forrr1ing a first part of a first node of the
`
`capacitor formed in a first conductive layer of the IC and a second plurality
`
`of conductive elements electrically connected to and forming a first part of a
`
`second node of the capacitor formed in the first conductive layer, the first
`
`plurality of conductive elements alternating with the second plurality of
`
`conductive elements in the first conductive layer, and a third plurality of
`
`conductive elements electrically connected to and forming a second part of
`
`the first node formed in a second conductive layer adjacent to the first
`
`conductive layer, at least portions of some of the second plurality of
`
`conductive elements overlying and vertically coupling to at least portions of
`
`some of the third plurality of conductive elements;
`
`a shield capacitor portion having a fourth plurality of conductive elements
`
`formed in at least the first conductive layer of the IC, the second conductive
`
`layer of the IC, a third conductive layer of the IC, and a fourth conductive
`
`layer of the IC, the first conductive layer and the second conductive layer
`
`each being between the third conductive layer and the fourth conductive
`
`layer, the shield capacitor portion being electrically connected to and
`
`forming a second part of the second node of the capacitor and surrounding
`
`the first plurality of conductive elements and the third plurality of
`
`conductive elements; and
`
`a reference shield electrically connected to a reference node of the IC other
`
`than the second node of the capacitor, the shield capacitor portion being
`
`disposed between the reference shield and the core capacitor portion.
`
`-14-
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR20 12-00023
`
`2. The capacitor of claim 1 wherein the third conductive layer is a metal
`
`layer of the IC and the fourth conductive layer is a poly layer of the IC, the
`
`shield capacitor portion including a first node shield plate formed in the
`
`metal layer from a plurality of metal stripes and a second node shield plate
`
`formed in the poly layer.
`
`As can be seen from the claims, the capacitor includes three components: (1) a
`
`core capacitor portion; (2) a shield capacitor portion; and (3) a reference shield.
`
`The first two portions connect to nodes of the capacitor, while the reference shield
`
`connects to a reference node at a different voltage than either capacitor node, such
`
`as power (VDD) or ground.
`
`30.
`
`For the sake of example, FIG. 2B from the ‘609 patent is reproduced
`
`and annotated below, the annotations corresponding to the terms in claims 2 and 1
`
`(upon which claim 2 depends). The capacitor includes two nodes T and B. Node
`
`B includes shield plate B’, which is made of polysilicon. A reference shield
`
`224/225 is also provided in addition to (and separate from) the nodes of the
`
`capacitor and the shield plate B’. The reference shield 224/225 is annotated in the
`
`figure, and in this example is connected to the reference voltage VDD. IVM 1001 at
`
`6:45-46 and 7:31-32.
`
`-15-
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR2012—00023
`
`connected to VDD
`
` reference shield- —
`
`222
`conductive elements- -
`
`connected to node “T”
`
`shield plate,
`connected to node “B”
`
`_ __
`
`L’'‘‘’' A
`
`-Gabs rate
`
`VDDShield(N—we||)
`
`31.
`
`The figure identifies various layers of the IC on the left side. These
`
`include Poly (polysilicon), M1 (metal 1), M2 (metal 2), and so forth. The ‘609
`
`patent teaches that the nodes T and B in layers M2 and M4, respectively, also
`
`include many conductive elements, or conductive strips. They do not appear in
`
`FIG. 2B because the elements are running left to right, but they do appear in FIG.
`
`2A, which provides a perspective view.
`
`32.
`
`It is noted that in the core portion 201,the conductive layer in M2 only
`
`includes conductive elements from the top node (T), while in this region, the
`
`conductive layers M1 and M3 include alternating conductive elements. The ‘609
`
`patent refers to the former type of layer, where there are no alternating conductive
`
`elements, as a “plate” layer.
`
`‘609 patent at 5:57-58. The ‘609 patent explains the
`
`benefit of having a plate layer adjacent to a layer of alternating conductive
`
`-16-
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR20 12-00023
`
`elements as follows:
`
`the core capacitor portion 201... has interleaved top and bottom node
`
`conductive filaments that provide high specific lateral capacitance in the
`
`M1 and M3 metal layers, and vertical capacitance between the bottom node
`
`elements in M1 and M3 and the top node elements in M2, which is adjacent
`
`to both M1 and M3. 6:33-38, emphasis added.
`
`In addition, the conductive elements in the first conductive layer are “orthogonal”
`
`to the conductive elements in the second conductive layer. In so doing, the
`
`capacitors in the ‘609 patent are able to achieve unique lateral and vertical
`
`capacitances.
`
`33.
`
`The configuration of FIG. 2B, as shown above, also produces an
`
`unbalanced capacitor. The ‘609 patent teaches:
`
`Providing an equal number of conductive strips in a layer for each node
`
`balances the coupling of each node to the substrate, which is desirable in
`
`some applications, but undesirable in others, such as switching applications
`
`where it is desirable to have less coupling at one node. 1:63-67.
`
`34.
`
`The ‘609 patent also describes embodiments that utilize two poly
`
`layers, and embodiments using both a diffusion layer in the semiconductor
`
`substrate along with a poly layer. The patent emphasizes the benefits of using such
`
`layers, including being able to have a solid plate, instead of a plate with multiple
`
`elements or strips. 5:8—28. In so doing, the capacitors in the ‘609 patent are able to
`
`-17-
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR20 12-00023
`
`achieve unique lateral and vertical capacitances, as compared to capacitors that
`
`have all nodes in metal layers.
`
`35.
`
`In the Declaration of Morgan Johnson, Mr. Johnson has constructed a
`
`modified figure, labeled FIG. G, that is supposedly based, at least in part, on FIG.
`
`13 of Paul and FIG. 4 of Brennan. Johnson Decl. at 44-46. The capacitor
`
`described in FIG. G has converted the balanced capacitor of Paul (and the balanced
`
`capacitor of Brennan) into an unbalanced transistor by inserting the middle (the so-
`
`called 2nd layer) of the capacitor connected to node “B,” and relabeling the bottom
`
`plate (the so—called 4”‘ layer) as being connected to node “A”. That is, the
`
`capacitor of FIG. G now includes two plates connected to node A, one connected
`
`to node B, and two layers with elements connecting to A and B in an alternating
`
`manner. This new arrangement goes well beyond the scope of either Paul or
`
`Morgan. That is, this is not merely adding another set of nodes to perform their
`
`known function, but this is changing the functional operation of the resulting
`
`capacitor in a way not previously described.
`
`-18-
`
`XLNX—2006
`
`

`
`Blanchard Decl.
`
`IPR2012-00023
`
`36.
`
`I hereby declare that all statements made herein of my own
`
`knowledge are true and that all statements made on information and belief are
`
`believed to be true; and further that these statements were made with the
`
`knowledge that willful false statements and the like so made are punishable by
`
`fine or imprisonment, or both, as required under Section 1001 of Title 18 of
`
`the United States Code.
`
`_
`It
`Executed this e~,_ day of May 2013 1n Los Altos, CA.
`
`Respectfully submitted,
`
`‘QM R
`
`Richard A. Blanchard
`
`-19-
`
`XLNX-2006

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