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`IPR20 12-00023
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`INTELLECTUAL VENTURES MANAGEMENT, LLC
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`Petitioner
`
`V.
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`Patent of XILINX, INC.
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`Patent Owner
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`Case IPR20l2—00023
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`Patent 7,994,609
`
`Title: SHIELDING FOR INTEGRATED CAPACITORS
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`
`DECLARATION OF RICHARD A. BLANCHARD PH.D.
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`UNDER 37 C.F.R.
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`1.68
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`1, Richard Blanchard, do hereby declare:
`
`1.
`
`I am making this declaration at the request of Xilinx, Inc. in the matter
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`of the Inter Partes Review of U.S. Patent No 7,994,609 (“the ’609 Patent”) to
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`Quinn, initiated by petitioner Intellectual Ventures Management, LLC (IVM).
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`2.
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`In the preparation of this declaration, I have studied:
`
`(1)
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`The Petition for Inter Parte Review (“Petition”), Paper 3;
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`—l—
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`XLNX—2006
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`Blanchard Decl.
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`IPR2012—00023
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`(2)
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`The ’609 Patent, IVM—1001;
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`(3)
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`The prosecution history of the ’609 Patent, IVM—1003 — 1005;
`
`(4)
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`U.S. Patent No. 6,737,698 (“Paul”), IVM—1006;
`
`(5)
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`U.S. Patent No. 7,439,570 (“Anthony”), IVM—1007;
`
`(6)
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`U.S. Patent No. 7,286,071 (“Hsueh”), IVM—1008;
`
`(7)
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`U.S. Patent No. 6,903,918 (“Brennan”), IVM— 1009;
`
`(8)
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`U.S. Pub. No. 2008/0128857 (“Bi”), IVM1010;
`
`(9)
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`U.S. Patent No. 7,238,981 (“Marotta”), IVM— 101 1;
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`(10) Declaration of Morgan Johnson, IVM—1002; and
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`(11) The Decision entered Feb. 12, 2013 (“Decision”), Paper 11.
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`3.
`
`In forming the opinions expressed below, I have considered:
`
`(1)
`
`The documents listed above,
`
`(2)
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`The relevant legal standards, including the standard for obviousness
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`provided in KSR International Co. v. Teleflex, Inc., 550 U.S. 398 (2007) and
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`any additional authoritative documents as cited in the body of this
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`declaration, and
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`(3) My knowledge and experience based upon my work in this area as
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`described below.
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`—2—
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`XLNX—2006
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`
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`Blanchard Decl.
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`IPR2012—00023
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`4.
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`I am familiar with and am a practitioner of the technology at issue and
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`am aware of the state of the art at the time the application leading to the ’609
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`Patent was filed. The earliest priority date is November 21, 2008. Based on the
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`technologies disclosed in the ’609 Patent, I believe that one of ordinary skill in the
`
`art would include someone who has a B.S. degree in Electrical Engineering or
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`equivalent training, as well as 3-5 years of experience in the field of integrated
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`circuit device design and layout and semiconductor fabrication technology .
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`Unless otherwise stated, when I give my understanding and analysis below, it is
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`consistent with the level of one of ordinary skill in these technologies at and
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`around the filing date of the ‘609 patent.
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`5.
`
`I am a consultant for Thomson Reuters Expert Witness Services
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`(formerly known as Silicon Valley Expert Witness Group), a consulting company
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`specializing in expert witness litigation support and technology consulting. I also
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`provide technical consulting services to the semiconductor and electronics industry
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`through Blanchard Associates.
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`6.
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`My academic credentials include both a Bachelor of Science
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`Degree in Electrical Engineering (BSEE) and a Master of Science Degree in
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`Electrical Engineering (MSEE) from the Massachusetts Institute of
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`Technology in 1968 and 1970, respectively.
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`I subsequently obtained a Ph.D.
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`-3-
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`XLNX—2006
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`Blanchard Decl.
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`IPR20 12-00023
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`in Electrical Engineering in 1982 from Stanford University.
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`7.
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`My professional background and technical qualifications are stated
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`above and are also reflected in my Curriculum Vitae, which is attached as XLNX—
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`2007. I am being compensated at a rate of $275.00 per hour, with reimbursement
`
`for actual expenses, for my work related to this Petition for Inter Partes Review.
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`My compensation is not dependent on and in no way affects the substance of my
`
`statements in this Declaration.
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`8.
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`I have worked or consulted for more than 40 years as an
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`Electrical Engineer. My primary focus has been on the development,
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`manufacture, operation, and use of devices and integrated circuits, the
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`assembly of these devices and integrated circuits, products that use them,
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`and their failures. My employment history following my graduation from
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`MIT began at Fairchild Semiconductor in 1970. At Fairchild, my
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`responsibilities included circuit and device design, process development, and
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`product engineering in the Linear Integrated Circuits Department.
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`9.
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`In 1974, I joined Foothill College as an Associate Professor in
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`the Engineering & Technology Division. My responsibilities included
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`developing a program in Semiconductor Technology as well as teaching
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`other courses in the division. While at Foothill College, I co—founded two
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`-4-
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`XLNX—2006
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`Blanchard Decl.
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`IPR20 12-00023
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`companies, Cognition and Supertex, and later joined Supertex as a Vice
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`President in 1978. At Supertex, I designed and developed discrete DMOS
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`(double—diffused metal oxide semiconductor) transistors, as well as
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`integrated circuits that contained DMOS transistors. At Supertex, I also
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`supervised the in—house assembly area, which included responsibility for the
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`associated manufacturing processes.
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`10.
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`I left Suptertex to join Siliconix in 1982, where I soon became
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`Vice President of Engineering, with the responsibility for directing all of the
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`company's product design and development. At Siliconix, I directed and
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`contributed to the development of both discrete transistors and integrated
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`circuits, including aspects of their assembly.
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`11.
`
`In 1987, I joined IXYS Corporation as a Senior Vice President
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`with the responsibility for organizing an integrated circuit department. At
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`IXYS, I developed integrated circuits that contained DMOS devices or that
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`interfaced to DMOS devices. My responsibilities included the design,
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`assembly, and testing of these integrated circuits.
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`12.
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`These duties continued until 1991, when I left IXYS to set up
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`Blanchard Associates, a consulting firm specializing in semiconductor
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`technology, including intellectual property. Soon thereafter, I was invited to
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`-5-
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`XLNX—2006
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`Blanchard Decl.
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`IPR2012—00023
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`join Failure Analysis Associates, which I did in late 1991. At Failure
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`Analysis Associates, I investigated failures in electrical and electronic
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`systems in addition to performing design and development consulting.
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`13.
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`I left Failure Analysis in 1998 to join IP Managers, which later
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`merged with Silicon Valley Expert Witness Group, now known as Thomson
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`Reuters Expert Witness Services ("Thomson Reuters"). At Thomson
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`Reuters, I work with companies on patent and trade secret matters.
`
`I also
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`consult for a number of semiconductor companies, working with them to
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`develop products and intellectual property, or assisting them in other
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`technical areas through Blanchard Associates. Design and Development
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`projects that I have worked on range from the design and evaluation of
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`specific components, to the selection of the technology appropriate for the
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`fabrication of different subsystems of a system.
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`14.
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`I am a member of a number of professional societies, including
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`the Institute of Electrical and Electronic Engineers, the International
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`Microelectronics and Packaging Society, the American Vacuum Society, the
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`Electronic Device Failure Analysis Society, and the Electrostatic Discharge
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`Society.
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`15. A copy of my curriculum vitae is attached as XLNX—2007.
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`-6-
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`XLNX—2006
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`Blanchard Decl.
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`IPR20 12-00023
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`Additional information regarding my education, technical experience and
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`publications, including a list of the US patents of which I am an inventor, is
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`included therein.
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`Relevant Legal Standards
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`16.
`
`I have been asked to provide my opinions regarding whether the
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`claims of the ’609 Patent are anticipated or would have been obvious to a person
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`having ordinary skill in the art at the time of the alleged invention, in light of the
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`prior art. It is my understanding that, to anticipate a claim under 35 U.S.C. § 102, a
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`reference must teach every element of the claim. Further, it is my understanding
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`that a claimed invention is unpatentable under 35 U.S.C. § 103 if the differences
`
`between the invention and the prior art are such that the subject matter as a whole
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`would have been obvious at the time the invention was made to a person having
`
`ordinary skill in the art to which the subject matter pertains. I also understand that
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`the obviousness analysis takes into account factual inquiries including the level of
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`ordinary skill in the art, the scope and content of the prior art, and the differences
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`between the prior art and the claimed subject matter.
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`17.
`
`It is my understanding that the Supreme Court has recognized several
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`rationales for combining references or modifying a reference to show obviousness
`
`of claimed subject matter. Some of these rationales include the following:
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`—7—
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`Blanchard Decl.
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`IPR20 12-00023
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`combining prior art elements according to known methods to yield predictable
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`results; simple substitution of one known element for another to obtain predictable
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`results; use of a known technique to improve a similar device (method, or product)
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`in the same way; applying a known technique to a known device (method, or
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`product) ready for improvement to yield predictable results; choosing from a finite
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`number of identified, predictable solutions, with a reasonable expectation of
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`success; and some teaching, suggestion, or motivation in the prior art that would
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`have led one of ordinary skill to modify the prior art reference or to combine prior
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`art reference teachings to arrive at the claimed invention.
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`18.
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`It is my understanding that some claims can be interpreted as “means
`
`plus function” claims under 35 U.S.C. § 112, paragraph 6. I understand that
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`determining the broadest reasonable interpretation of “means plus function”
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`claims requires first, defining the particular function of the limitation and second,
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`identifying the corresponding structure for that function in the specification. I also
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`understand that structure disclosed in the specification is corresponding structure
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`only if the specification or prosecution history clearly links or associates that
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`structure to the function recited in the claim.
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`Anthony
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`19. Anthony teaches the use of shielding layers of metal that are
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`-8-
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`XLNX—2006
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`Blanchard Decl.
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`IPR2012-00023
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`present below and above the inter-digitated fingers of the metal-to-metal
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`capacitors. These shielding layers reduce the parasitic capacitance to ground,
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`and shield one capacitor node from other circuit nodes. 3:50-63. Capacitors
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`fabricated in this fashion are shown in FIGS. 3 and 4. FIG. 4 of Anthony is
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`reproduced and annotated below.
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`-
`
`— ' ' ;;f:;;"“
`
`{%'is\\\\\\\\\\\(\ \gf
`I4////////,<~.
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`- — — capacitor
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`'f A§
`
`§\XX\R\'§\
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`‘4! W.&
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`:: -;;:’§:::;"“
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`Anthony, FIG. 4
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`20. Anthony states that the capacitor 30 is formed by “plates 33 and 34”
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`and “terminals 31 and 32.” 4:35-38. Plates 33 and 34 are formed in “additional
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`layers of metal.” 423-4. The capacitor 30 of FIG. 4 is shielded by features
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`including the metal plate 35, and the diffused layer 46. 4266-522. In other words,
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`-9-
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`Blanchard Decl.
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`IPR2012—00023
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`Anthony’s capacitor in FIG. 4 has a first plate 33 and a second plate 34 where both
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`plates are formed of metal layers overlying the substrate, not in poly or in the
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`diffusion. Anthony’s reference shield plates 36/46 are formed in the metal layer
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`(36) and in the diffusion layer (46), and are not connected to either node of the
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`capacitor. Anthony does not teach a node of the conductor being in either the
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`diffused layer or poly.
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`Hsueh
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`21. Hsueh teaches a system for displaying images by driving
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`individual pixels of a display screen using thin film transistors. A two stage
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`digital—to—analog converter that includes switched capacitors is part of the
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`drive circuitry. 1:42-50.
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`Brennan
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`22. Brennan teaches a shielded planar capacitor. As shown in FIG. 2
`
`of Brennan, reproduced below, a capacitor has two nodes 106, 112, separated
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`by a relatively thin dielectric 110. A shield is formed around the capacitor,
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`and is separated from the capacitors by relatively thick dielectric layers
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`104/114 having a small dielectric constant. The combination of a relatively
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`thick dielectric layer and a small dielectric constant significantly reduces any
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`capacitive coupling. 2:26-35.
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`—10—
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`XLNX—2006
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`Blanchard Decl.
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`IPR20 12-00023
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`23.
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`Brennan is directed to capacitors with only plate layers, and no layers
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`with alternating conducting elements. The number of plate layers are always
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`balanced between the two nodes. Brennan extolls the benefits of using only plate
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`layers, stating that they “simplify planar capacitor fabrication at the metal
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`interconnect layer and via layers.” 3:28-30. Brennan further describes the
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`benefits of using “slotted” capacitor plates, including improved quality of planar
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`capacitor plates and that the trace and slot widths in a plate layer provide “filtering
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`of relatively high frequency EMI noise.” 6:58—7:9.
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`,2,
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`},
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`/10210335
`:5 J‘:"—-q.1«,:<-.;/in-v;..-;»5.«
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`
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`235
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`
`
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`,,\
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`112
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`,u-,.-,».,.
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`
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`236
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` 106
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`
`
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`24.
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`Bi shows the use of a multi—finger capacitor fabricated using a
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`number of metal layers in an IC. The fingers connected to the input node are
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`interleaved with the fingers connected to the output node. A conductive layer
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`or plate below the bottom layer of interleaved fingers ia also connected to the
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`—l l—
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`XLNX—2006
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`Blanchard Decl.
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`IPR20 12-00023
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`input node between the substrate and the first and second layer of fingers,
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`reducing the parasitic capacitance of the output node.
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`‘][l8.
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`Marotta
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`25. Marotta teaches integrated capacitor structures that include the use
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`of a doped region of silicon in the capacitor structure. Both a single layer of
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`poly above a doped layer of silicon (Fig. 3) and an inter—digitated metal
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`capacitor above a doped layer of silicon and below a second metal layer (Figs.
`
`5 and 5A) are included. Marotta does not teach a node of the capacitor being in
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`either the diffused layer or poly.
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`Paul
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`26.
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`Paul is directed to capacitors, including structures with top and bottom
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`shields, each tied to a different node of the capacitor. 2:37-48. A capacitor
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`structure that includes both a top shield and a side shield that are connected
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`together is also present. Fig. 8. Paul is directed to a balanced capacitor, in which
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`the number of plates or conducting elements are always balanced between the two
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`nodes. Paul does not disclose that the shield capacitor portion is a poly layer of the
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`IC or that a second node shield is formed in the poly layer.
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`27. Also, Paul does not teach a plate layer having a plurality of
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`conducting elements connected to a common node. Specifically, Paul’s FIG. 13
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`-12-
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`XLNX—2006
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`Blanchard Decl.
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`IPR20 12-00023
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`teaches two interior layers having a plurality of conducting elements, the layers in
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`Metal 3 and Metal 2. FIG. 13 of Paul is reproduced below.
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`In both these interior
`
`layers, the conducting elements alternate between node A and node B. There is no
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`interior layer of conducting elements that do not alternate (a plate layer).
`
`METAL 1-+
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`alternating
`conductive elements
`
`Discussion Of ’609 Patent
`
`28.
`
`The ‘609 patent is directed to a capacitor, and more specifically, to
`
`shielding for a capacitor in an integrated circuit. Title. The background section of
`
`the patent discusses how capacitors are used for many different purposes in an IC,
`
`one example being in a switching circuit. An example switching circuit is
`
`provided in FIG. 1 of the patent.
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`29.
`
`For the sake of example, claims 1-2 of the ‘609 patent are reproduced
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`below:
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`— l 3-
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`XLNX—2006
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`Blanchard Decl.
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`IPR20 12-00023
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`1. A capacitor in an integrated circuit ("IC") comprising:
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`a core capacitor portion having a first plurality of conductive elements
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`electrically connected to and forrr1ing a first part of a first node of the
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`capacitor formed in a first conductive layer of the IC and a second plurality
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`of conductive elements electrically connected to and forming a first part of a
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`second node of the capacitor formed in the first conductive layer, the first
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`plurality of conductive elements alternating with the second plurality of
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`conductive elements in the first conductive layer, and a third plurality of
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`conductive elements electrically connected to and forming a second part of
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`the first node formed in a second conductive layer adjacent to the first
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`conductive layer, at least portions of some of the second plurality of
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`conductive elements overlying and vertically coupling to at least portions of
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`some of the third plurality of conductive elements;
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`a shield capacitor portion having a fourth plurality of conductive elements
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`formed in at least the first conductive layer of the IC, the second conductive
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`layer of the IC, a third conductive layer of the IC, and a fourth conductive
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`layer of the IC, the first conductive layer and the second conductive layer
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`each being between the third conductive layer and the fourth conductive
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`layer, the shield capacitor portion being electrically connected to and
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`forming a second part of the second node of the capacitor and surrounding
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`the first plurality of conductive elements and the third plurality of
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`conductive elements; and
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`a reference shield electrically connected to a reference node of the IC other
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`than the second node of the capacitor, the shield capacitor portion being
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`disposed between the reference shield and the core capacitor portion.
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`-14-
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`Blanchard Decl.
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`2. The capacitor of claim 1 wherein the third conductive layer is a metal
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`layer of the IC and the fourth conductive layer is a poly layer of the IC, the
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`shield capacitor portion including a first node shield plate formed in the
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`metal layer from a plurality of metal stripes and a second node shield plate
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`formed in the poly layer.
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`As can be seen from the claims, the capacitor includes three components: (1) a
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`core capacitor portion; (2) a shield capacitor portion; and (3) a reference shield.
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`The first two portions connect to nodes of the capacitor, while the reference shield
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`connects to a reference node at a different voltage than either capacitor node, such
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`as power (VDD) or ground.
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`30.
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`For the sake of example, FIG. 2B from the ‘609 patent is reproduced
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`and annotated below, the annotations corresponding to the terms in claims 2 and 1
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`(upon which claim 2 depends). The capacitor includes two nodes T and B. Node
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`B includes shield plate B’, which is made of polysilicon. A reference shield
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`224/225 is also provided in addition to (and separate from) the nodes of the
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`capacitor and the shield plate B’. The reference shield 224/225 is annotated in the
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`figure, and in this example is connected to the reference voltage VDD. IVM 1001 at
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`6:45-46 and 7:31-32.
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`XLNX—2006
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`IPR2012—00023
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`connected to VDD
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` reference shield- —
`
`222
`conductive elements- -
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`connected to node “T”
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`shield plate,
`connected to node “B”
`
`_ __
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`L’'‘‘’' A
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`-Gabs rate
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`VDDShield(N—we||)
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`31.
`
`The figure identifies various layers of the IC on the left side. These
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`include Poly (polysilicon), M1 (metal 1), M2 (metal 2), and so forth. The ‘609
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`patent teaches that the nodes T and B in layers M2 and M4, respectively, also
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`include many conductive elements, or conductive strips. They do not appear in
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`FIG. 2B because the elements are running left to right, but they do appear in FIG.
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`2A, which provides a perspective view.
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`32.
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`It is noted that in the core portion 201,the conductive layer in M2 only
`
`includes conductive elements from the top node (T), while in this region, the
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`conductive layers M1 and M3 include alternating conductive elements. The ‘609
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`patent refers to the former type of layer, where there are no alternating conductive
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`elements, as a “plate” layer.
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`‘609 patent at 5:57-58. The ‘609 patent explains the
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`benefit of having a plate layer adjacent to a layer of alternating conductive
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`-16-
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`XLNX—2006
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`Blanchard Decl.
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`elements as follows:
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`the core capacitor portion 201... has interleaved top and bottom node
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`conductive filaments that provide high specific lateral capacitance in the
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`M1 and M3 metal layers, and vertical capacitance between the bottom node
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`elements in M1 and M3 and the top node elements in M2, which is adjacent
`
`to both M1 and M3. 6:33-38, emphasis added.
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`In addition, the conductive elements in the first conductive layer are “orthogonal”
`
`to the conductive elements in the second conductive layer. In so doing, the
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`capacitors in the ‘609 patent are able to achieve unique lateral and vertical
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`capacitances.
`
`33.
`
`The configuration of FIG. 2B, as shown above, also produces an
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`unbalanced capacitor. The ‘609 patent teaches:
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`Providing an equal number of conductive strips in a layer for each node
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`balances the coupling of each node to the substrate, which is desirable in
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`some applications, but undesirable in others, such as switching applications
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`where it is desirable to have less coupling at one node. 1:63-67.
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`34.
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`The ‘609 patent also describes embodiments that utilize two poly
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`layers, and embodiments using both a diffusion layer in the semiconductor
`
`substrate along with a poly layer. The patent emphasizes the benefits of using such
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`layers, including being able to have a solid plate, instead of a plate with multiple
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`elements or strips. 5:8—28. In so doing, the capacitors in the ‘609 patent are able to
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`-17-
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`Blanchard Decl.
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`achieve unique lateral and vertical capacitances, as compared to capacitors that
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`have all nodes in metal layers.
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`35.
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`In the Declaration of Morgan Johnson, Mr. Johnson has constructed a
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`modified figure, labeled FIG. G, that is supposedly based, at least in part, on FIG.
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`13 of Paul and FIG. 4 of Brennan. Johnson Decl. at 44-46. The capacitor
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`described in FIG. G has converted the balanced capacitor of Paul (and the balanced
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`capacitor of Brennan) into an unbalanced transistor by inserting the middle (the so-
`
`called 2nd layer) of the capacitor connected to node “B,” and relabeling the bottom
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`plate (the so—called 4”‘ layer) as being connected to node “A”. That is, the
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`capacitor of FIG. G now includes two plates connected to node A, one connected
`
`to node B, and two layers with elements connecting to A and B in an alternating
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`manner. This new arrangement goes well beyond the scope of either Paul or
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`Morgan. That is, this is not merely adding another set of nodes to perform their
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`known function, but this is changing the functional operation of the resulting
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`capacitor in a way not previously described.
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`-18-
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`XLNX—2006
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`Blanchard Decl.
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`IPR2012-00023
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`36.
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`I hereby declare that all statements made herein of my own
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`knowledge are true and that all statements made on information and belief are
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`believed to be true; and further that these statements were made with the
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`knowledge that willful false statements and the like so made are punishable by
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`fine or imprisonment, or both, as required under Section 1001 of Title 18 of
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`the United States Code.
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`_
`It
`Executed this e~,_ day of May 2013 1n Los Altos, CA.
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`Respectfully submitted,
`
`‘QM R
`
`Richard A. Blanchard
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`-19-
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`XLNX-2006