(12) Unlted States Patent
`(10) Patent N0.:
`US 6,680,218 132
`
`Chung et al.
`(45) Date of Patent:
`Jan. 20, 2004
`
`US006680218B2
`
`(54) FABRICATION METHOD FOR VERTICAL
`ELECTRONIC CIRCUIT PACKAGE AND
`SYSTEM
`
`............... 257/700
`6,495,912 B1 * 12/2002 Huang et a1.
`............... 257/779
`6,555,920 B2
`4/2003 Chung et a1.
`6,556,453 B2 *
`4/2003 Figueroa et a1.
`............ 361/763
`
`(75)
`
`Inventors: Chee-Yee Chung, Chandler, AZ (US);
`David G. Figueroa, Mesa, AZ (US);
`Robert L. Sankman, Phoenix, AZ (US)
`
`* cited by examiner
`
`(73) Assignee:
`
`Intel Corporation, Santa Clara, CA
`(US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term Of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.2 10/371,659
`
`Filed:
`
`(22)
`(65)
`
`Feb. 21’ 2003
`Prior Publication Data
`
`US 2003/0151146 A1 Aug. 14, 2003
`
`Related US. Application Data
`
`(62)
`
`23:31:? Oglgpgliscgggggo’ 09/8974369’ filed on JUL 2’ 2001’
`
`(51)
`Int. Cl.7 ...........
`----- H01L 21/44
` (52) U-S- Cl ------------------------------ 438/108
`(58) Field of Search ................................. 438/108,106;
`257/778
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`Przntary ExamL/ter—Davrd Nelms
`Asszstant Exammer—Thao Le
`(74) Attorney, Agent, or Firm—Schwegman, Lundberg,
`Woessner & Kluth, P.A.
`
`(57)
`
`ABSTRACT
`
`An electronic circuit package includes a vertical package
`section (304, FIG. 3) electrically connected to a horizontal
`package section (306, FIG. 3). The vertical package section
`includes multiple conductive layers (512, 514, 516, FIG. 5)
`oriented in parallel With a vertical plane. A first set Of bond
`pads (606, FIG. 6) on the vertical section’s horizontal top
`surface (608, FIG. 6) can be connected to the bond pads
`(602, FIG. 6) Of an integrated circuit (302, FIG. 3). Asecond
`set Of bond pads (612, FIG. 6) on the vertical section’s
`horizontal bottom surface (614, FIG. 6) can be connected to
`bond pads (616, FIG. 6) on the horizontal package section.
`The conductive layers Of the vertical section perform a bond
`pad pitch conversion in a first direction, and conductive
`structures (906, 908, 910, FIG. 9) within the horizontal
`package section perform a bond pad pitch conversion in a
`second direction.
`
`6,031,282 A
`
`2/2000 Jones et a1.
`
`................. 257/692
`
`21 Claim, 10 Drawing Sheets
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`302
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`

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`US. Patent
`
`Jan. 20, 2004
`
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`US 6,680,218 B2
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`PRIOR ART
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`

`

`US. Patent
`
`Jan. 20, 2004
`
`Sheet 2 0f 10
`
`US 6,680,218 132
`
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`

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`US. Patent
`
`Jan. 20, 2004
`
`Sheet 3 0f 10
`
`US 6,680,218 B2
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`US. Patent
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`Jan. 20, 2004
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`Sheet 4 0f 10
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`US 6,680,218 B2
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`Jan. 20, 2004
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`Jan. 20, 2004
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`US 6,680,218 B2
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`US. Patent
`
`Jan. 20, 2004
`
`Sheet 7 0f 10
`
`US 6,680,218 B2
`
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`

`

`US. Patent
`
`Jan. 20, 2004
`
`Sheet 8 0f 10
`
`US 6,680,218 132
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`US. Patent
`
`Jan. 20, 2004
`
`Sheet 9 0f 10
`
`US 6,680,218 132
`
`1002
`
`1004
`
`1006
`
`1008
`
`1010
`
`1012
`
`1014
`
`BEGIN
`
`FABRICATE VERTICAL AND
`HORIZONTAL PACKAGE
`STRUCTURES
`
`
`
`SINGULATE VERTICAL AND
`HORIZONTAL SECTIONS
`
`FORM BOND PADS
`
`CONNECT DECOUPLING
`CAPACITORS
`
`CONNECT VERTICAL AND
`
`
`
`HORIZONTAL PACKAGE
`SECTIONS
`
`CONNECT DIE
`
`CONNECT PACKAGE TO PC
`BOARD
`
`FIG. 10
`
`

`

`US. Patent
`
`Jan. 20, 2004
`
`Sheet 10 0f 10
`
`US 6,680,218 B2
`
`CIRCUIT
`
`PACKAGE
`
`PC BOARD
`
`POWER SUPPLY
`
`FIG. 11
`
`

`

`US 6,680,218 B2
`
`1
`FABRICATION METHOD FOR VERTICAL
`ELECTRONIC CIRCUIT PACKAGE AND
`SYSTEM
`
`This application is a divisional of US. patent application
`Ser. No. 09/897,369, filed Jul. 2, 2001, now US. Pat. No.
`6,555,920 which is incorporated herein by reference in its
`entirety.
`TECHNICAL FIELD OF THE INVENTION
`
`The present invention relates generally to electronic cir-
`cuit packages and methods of fabrication therefor, and more
`particularly, to integrated circuit packages having bond pads
`that are directly connected with vertically-oriented conduc-
`tive layers, rather than with vias or horizontally-oriented
`conductive layers.
`BACKGROUND OF THE INVENTION
`
`Signals, power, and ground typically are routed to and
`from an integrated circuit (IC) through conductive bond
`pads on the bottom of the IC, which mate with complemen-
`tary bond pads on the top surface of an IC package. This is
`common for ICs that use ball grid array (BGA) (e.g., “flip
`chips”) and land grid array (LGA) interconnection technolo-
`gies. Alternatively, wire bonds are often used to electrically
`connect an IC and an IC package.
`FIG. 1 illustrates a cross-sectional view of an electronic
`
`includes an IC 102 and package 104 in
`assembly that
`accordance with the prior art. Bond pads 106 on the bottom
`surface of IC 102 electrically connected to complementary
`bond pads 108 on the top surface of IC package 104 using
`solder bumps or balls 110. The IC package bond pads 108
`are, in turn, electrically connected to vias 112. Vias 112 are
`plated and/or filled holes in the package’s dielectric layers,
`which are used to interconnect various conductive layers 114
`within the package 104, and/or connectors 108, 116 on the
`top and/or bottom surfaces, respectively, of the package 104.
`Package 104 is electrically connected to a socket 118 or
`interposer (not shown), through soldered or pinned connec-
`tors 116. Socket 118, in turn, is electrically connected to a
`printed circuit (PC) board 122 using pinned or soldered
`connections. Alternatively, package 104 can be connected
`directly to PC board 122 without the use of an intermediate
`socket or interposer. Using prior art technologies,
`input/
`output (I/O) signals, power, and ground are supplied from
`PC board 122 to IC 102 through socket 118, connectors 116,
`conductive layers 114, vias 112, pads 108, and solder balls
`110.
`
`FIG. 2 illustrates a top view of an IC package, which
`includes multiple rows of pads 202, 204 in accordance with
`the prior art. Pads 204 within a center region 206 of the
`package typically are allocated to power and ground. In
`contrast, pads 202 within a peripheral region 208 typically
`are allocated to I/O signals.
`Current packaging technologies are limited in the location
`and number of pads 202 that can be dedicated to I/O signals
`because of the need to separately fan out, through vias and
`traces, each I/O signal from the IC pad pitch to the package
`pad pitch. In current flip chip packages, only the outer few
`rows of pads 202 can be dedicated to I/O signals. Thus, for
`example, in a package having 40><40 rows of pads, only
`about 300 pads can be dedicated to I/O signals, while about
`1300 pads can be dedicated to power and ground. In order
`to increase the number of I/O signals that can be fanned out,
`it is necessary to use finer design rules (e.g., smaller line
`spacing and pad pitches), increase the size of the IC, and/or
`
`2
`increase the number of package layers. Using finer design
`rules translates to more expensive materials and manufac-
`turing techniques.
`IC package size and package layer increases are undesir-
`able in many applications, because the consumer-driven
`trend within industry is to reduce the size of electronic
`systems. Accordingly, what are needed are package designs
`that enable higher I/O counts without increases in IC sizes,
`package layer counts or finer package design rules.
`In addition to issues relating to limited numbers of I/O
`signals, noise in the power and ground lines increasingly
`becomes a problem with current IC package designs. This is
`primarily due to escalating circuit frequencies, which result
`in increased high frequency transients. To reduce such noise,
`capacitors known as decoupling capacitors are often used to
`provide a stable signal or stable supply of power to the
`circuitry. Decoupling capacitors are also used to suppress
`unwanted radiation, to dampen voltage overshoot when an
`electronic device (e.g., a processor) is powered down, and to
`dampen voltage droop when the device powers up.
`Decoupling capacitors are generally placed as close as
`practical to a die load in order to increase the capacitors’
`effectiveness. Often, the capacitors are surface mounted to
`the die side or land side of the package upon which the die
`is mounted, or embedded within the package itself. Refer-
`ring again to FIG. 1, die side capacitors 130 (“DSC”) and
`land side capacitors (not shown) (“LSC”) are mounted on IC
`package 104 in accordance with the prior art. DSCs 130, as
`their name implies, are mounted on the same side of the
`package 102 as the IC 102. In contrast, LSCs are mounted
`on the opposite side of the package 104 as the IC 102.
`Embedded chip capacitors (not shown) (“ECC”) can be
`embedded within the package 104 and electrically connected
`to package planes and/or pads through conductive vias.
`When a “first level” voltage droop occurs, the electrically
`closest, off-chip capacitors (e.g., ECCs, if they are available)
`will respond first to supply the current needed to bolster the
`die voltage. When the charge stored within these first level
`capacitors begins to deplete, a “second level” voltage droop
`occurs, and other off-chip capacitors (e.g., DSCs and/or
`LSCs) will respond, if they are available.
`The capacitors’ terminals are connected to the integrated
`circuit load through conductive structures (e.g., pads, vias,
`and power or ground planes), thus enabling the capacitors
`130 to provide decoupling capacitance to the integrated
`circuit. Connection of the capacitors 130 to the load and to
`each other through the package’s conductive structures
`results in “vertical” and “lateral” inductances to eXist in the
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`supply and return loop between the capacitors 130 and the
`IC load. These vertical and lateral inductances tend to slow
`
`50
`
`the response time of off-chip capacitors, which may cause
`the first and second level voltage droops to be unacceptably
`low.
`
`55
`
`60
`
`65
`
`Vertical inductance issues can be addressed by placing
`off-chip capacitors 130 as electrically close as possible to the
`die load, such as by using ECCs, which typically can be
`placed closer to the load than surface mounted capacitors.
`Similarly,
`lateral inductance issues can be addressed by
`placing adjacent capacitors as close as possible to each other.
`As the frequencies and edge rates of electronic devices
`continue to advance, there is an increasing need for higher
`levels of decoupling capacitance. However, increasing the
`numbers of discrete decoupling capacitors typically results
`in increased package sizes. Therefore, what are needed are
`packages that can provide higher levels of decoupling
`capacitance, without increased package sizes, and at reduced
`inductance levels.
`
`

`

`US 6,680,218 B2
`
`3
`BRIEF DESCRIPTION OF THE DRAWING
`
`FIG. 1 illustrates a cross-sectional view of an electronic
`
`assembly that includes an integrated circuit and package in
`accordance with the prior art;
`FIG. 2 illustrates a top view of an integrated circuit
`package in accordance with the prior art;
`FIG. 3 illustrates a three-dimensional view of an electrical
`
`assembly in accordance with one embodiment of the present
`invention;
`FIG. 4 illustrates a top view of the electrical assembly
`shown in FIG. 3;
`FIG. 5 illustrates a cross-sectional view of the electrical
`
`10
`
`assembly of FIG. 3, along section lines 5—5;
`FIG. 6 illustrates a cross-sectional view of the electrical
`
`15
`
`assembly of FIG. 3, along section lines 6—6;
`FIG. 7 illustrates a top view of a vertical section of an
`integrated circuit package in accordance with one embodi-
`ment of the present invention;
`FIG. 8 illustrates a top view of a horizontal section of an
`integrated circuit package in accordance with one embodi-
`ment of the present invention;
`FIG. 9 illustrates a cross-sectional view of the horizontal
`
`section of FIG. 8 along section lines 9—9;
`FIG. 10 illustrates a flowchart of a method for fabricating
`an electrical assembly in accordance with one embodiment
`of the present invention; and
`FIG. 11 illustrates an electronic system in accordance
`with one embodiment of the present invention.
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`Various embodiments of the present invention provide an
`electronic circuit package (e.g., an integrated circuit
`package) that
`includes a vertical package section and a
`horizontal package section. The vertical section performs a
`bond pad pitch conversion in a first direction, and the
`horizontal section performs a bond pad pitch conversion in
`a second direction, resulting in a complete bond pad pitch
`conversion between an electronic circuit’s bond pads and
`connectors on the bottom surface of the package.
`The vertical package section includes multiple conductive
`layers arranged in parallel with a vertical plane. Bond pads
`on the top surface of the vertical package section can be
`electrically connected to complementary bond pads of an
`electronic circuit. Bond pads on the bottom surface of the
`vertical package section are at a greater pitch than the top
`surface pads, and can be electrically connected to comple-
`mentary bond pads on the top surface of the horizontal
`package section. The horizontal package section includes
`conductive layers arranged in parallel with a horizontal
`plane.
`FIG. 3 illustrates a three-dimensional view of an electrical
`
`assembly in accordance with one embodiment of the present
`invention. The electrical assembly includes an integrated
`circuit 302 (IC) and an IC package consisting of a vertical
`package section 304 and a horizontal package section 306.
`In one embodiment, the electrical assembly also included a
`set of first level decoupling capacitors 308 and a set of
`second level decoupling capacitors 310.
`In other
`embodiments, either or both capacitors 308 or 310 are
`excluded. For ease of explanation, the description below
`makes reference to an orthogonal set of axes, X, Y, and Z,
`which are depicted, in FIG. 3, below and to the left of the
`horizontal package section 306.
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`IC 302 could be any of a number of types of ICs. In one
`embodiment of the present
`invention,
`IC 302 is a
`microprocessor, although IC 302 could be an application
`specific integrated circuit (ASIC), memory device or many
`other types of devices in other embodiments.
`In one
`embodiment, IC 302 is a “flip chip” type of IC, meaning that
`the input/output terminations on the chip can occur at any
`point on its surface. After the chip has been readied for
`attachment to the vertical section 304 of the package, the
`chip is flipped over and attached, via solder bumps or balls
`to matching pads on the top surface 312 of the vertical
`section 304. Alternatively, IC 302 could be wire bonded,
`where input/output terminations are connected to the vertical
`section 304 using bond wires to pads on the top surface of
`the vertical section 304. Although the description herein
`refers to connecting a single IC or other device to the top
`surface of a vertical section 304 of a package, more than one
`IC or other device could be connected to the top surface of
`a vertical section, in other embodiments.
`In one embodiment, each row of bond pads on the top
`surface 312 of the vertical section 304 is electrically con-
`nected to one of multiple conductive layers within vertical
`section 304. Vertical package section 304 includes the
`multiple layers of conductive material separated by multiple
`layers of dielectric material. Each of the conductive and
`dielectric layers are arranged in parallel with each other and
`with a vertical plane, as indicated by lines 314. As will be
`illustrated and described in detail later, a set of bond pads are
`located on the top surface of the vertical package section
`304, where the top surface is parallel with a horizontal plane
`that is perpendicular to the vertical plane. In other words, the
`top surface 312 of the vertical section 304 is oriented along
`a horizontal, X-Y plane, while the conductive and dielectric
`layers of the vertical section 304 are oriented along vertical,
`Y—Z planes. This is in contrast to prior art packages, where
`the top surface of a package is oriented along a parallel plane
`to the various conductive and dielectric layers of the pack-
`age. Also unlike prior art packages, no vias are used to
`interconnect the conductive layers or to interconnect the
`bond pads on the top surface of vertical section 304 to the
`bond pads on the bottom surface of vertical section 304, in
`accordance with one embodiment. Instead, planes or traces
`formed from the conductive layers are used to interconnect
`the top and bottom surface bond pads of vertical section 304.
`Many ICs (e.g., flip chips in particular) are designed with
`a pitch between bond pads of approximately 200—300
`microns. Because it
`is possible to create structures with
`approximately 100 microns between adjacent conductive
`layers using standard printed circuit board materials, such
`materials are used to construct vertical section 304, in one
`embodiment. Typically, these materials and the associated
`manufacturing techniques are substantially less expensive
`than commonly used integrated circuit packaging materials
`and manufacturing techniques, where finer design rules are
`used. Therefore, the IC package of various embodiments of
`the present invention can be manufactured at a lower cost
`than prior art packages.
`the number of conductive layers
`In one embodiment,
`within vertical section 304 corresponds to the number of
`rows of bond pads on the bottom surface of IC 302. Thus,
`for example, if IC 302 has 40x40 rows of bond pads on its
`bottom surface, vertical section 304 would include 40 con-
`ductive layers. In the description and Figures, below, an IC
`having 10x10 rows of bond pads is described. This number
`of rows is for ease of illustration only, and is not intended to
`limit the scope if the application. In various embodiments,
`the IC package could accommodate an IC having more or
`fewer rows of bond pads as well.
`
`

`

`US 6,680,218 B2
`
`5
`The number of dielectric layers within vertical section
`304 is related to the number of conductive layers.
`Specifically, in one embodiment, a dielectric layer exists on
`both sides of each conductive layer. Accordingly,
`for
`example, if the vertical section 304 includes 40 conductive
`layers, the vertical section 304 would include 41 dielectric
`layers.
`In alternate embodiments, either or both of the
`outermost conductive layers could be located on the surface
`of the vertical section 304. In the previous example, this
`means that the vertical section 304 would include 40 or 39
`
`dielectric layers, respectively.
`The function of the vertical section 304 is to carry I/O
`signals, power, and ground between the horizontal section
`306 of the package and the IC 302. In addition,
`in one
`embodiment, the vertical section 304 serves to convert the
`pitch, along the Y-axis, from the bond pad pitch of IC 302
`to a larger pitch, such as the desired pitch for mating the
`package’s bottom surface connections with a next level of
`interconnect (e.g., an interposer, socket, printed circuit board
`or other substrate).
`level
`In one embodiment, a set of one or more first
`decoupling capacitors 308 are electrically and physically
`connected to side surfaces of vertical section 304. In one
`
`embodiment, these capacitors 308 are discrete, multi-layer
`capacitors (e.g., ceramic capacitors) having two or more
`terminals. Capacitors 308 are mounted on bond pads (not
`shown) on the side surfaces of vertical section 304, and
`electrically connected to conductive layers within vertical
`section 304 through vias (not shown). Although only four
`capacitors 308 is shown on one side of vertical section 304,
`more or fewer capacitors could be used as well. In addition,
`more than one row of capacitors could be attached to a side
`of vertical section 304 or capacitors 308 could be attached
`to more than one side.
`
`In one embodiment, as will be described in more detail
`below, one or more of the outer conductive layers of vertical
`section 304 are dedicated to power and ground. The use of
`closely-spaced planes for power and ground planes, and the
`close proximity of capacitors 308 to IC 302 can result in a
`lower inductance path between capacitors 308 and IC 302
`than is possible using prior art packages.
`In other
`embodiments, the outer conductive layers are not dedicated
`to power and/or ground, but other layers are instead dedi-
`cated to power and/or ground.
`Vertical section 304 is electrically connected to horizontal
`section 306, in one embodiment. In particular, bond pads
`(not shown) on the bottom surface of vertical section 304 are
`electrically connected to bond pads (not shown) on the top
`surface 316 of the horizontal section 306 of the package.
`These connections could be made, for example, using com-
`mon surface mount
`technologies (e.g., BGA or LGA
`technologies), although the connections also could be made
`using other technologies as well.
`Horizontal section 306 includes multiple layers of con-
`ductive materials separated by multiple layers of dielectric
`materials. The conductive and dielectric layers of horizontal
`section 306 are oriented in a parallel direction to the top
`surface 316 of the horizontal section 306, as indicated by
`lines 318. In other words, the top surface 316 and conductive
`layers of the horizontal section 306 are oriented along a
`horizontal, X-Y plane.
`The bottom surface of horizontal section 306, which also
`is horizontally oriented, includes connectors (not shown)
`(e. g., bond pads or pins), which enable the horizontal section
`306 to be mated with a next level of interconnect. The
`
`function of the horizontal section 306 is to carry I/O signals,
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`power, and ground between the next level of interconnect
`and vertical section 304. In addition, in one embodiment, the
`horizontal section 306 serves to convert the pitch, along the
`X-axis, from the bond pad pitch of IC 302 to a larger pitch,
`such as the desired pitch for mating the package’s bottom
`surface connections with the next level of interconnect. By
`using the vertical section 304 to convert the pad pitch along
`the Y-axis and using the horizontal section 306 to convert the
`pad pitch along the X-axis, a complete pitch conversion is
`achieved by the package. In an alternate embodiment, the
`package could produce a partial pitch conversion, and an
`interposer or other substrate could be used to complete the
`pitch conversion.
`By using the vertical section 304 to fan out I/O signals, a
`portion of the pitch conversion can be accomplished without
`the necessity for finer design rules, increased die sizes or
`increased package layer counts. In addition, it is possible to
`fan out I/O signals from any region of the IC, rather than just
`from the outer few rows. This also allows more pads to be
`dedicated to I/O signals than is possible using prior art
`packaging technologies.
`In one embodiment, a set of one or more second level
`decoupling capacitors 310 are electrically and physically
`connected to the top surface 316 of horizontal section 306
`and one or more of the conductive layers within horizontal
`section 306. In one embodiment, these capacitors 310 are
`discrete, multi-layer capacitors (e.g., ceramic capacitors)
`having two or more terminals. Capacitors 310 are mounted
`on bond pads (not shown) on the top surface 316 of
`horizontal section 306, and electrically connected to con-
`ductive layers within horizontal section 306 through vias
`(not shown). Although only one row of four capacitors 310
`is shown on each side of the top surface 316 of horizontal
`section 306, more or fewer capacitors could be used as well.
`In addition, more than one row of capacitors could be
`attached to either or both sides of the top surface 316 of
`horizontal section 306, and capacitors also could be attached
`to the bottom surface of horizontal section 306.
`
`Besides connecting decoupling capacitors 308, 310 to the
`vertical and horizontal sections 304, 306 of the package,
`other components could be connected to the package as well.
`For example, termination resistors for various I/O signal
`paths could be connected to the horizontal and/or vertical
`sections 306, 304.
`In the description, above, an IC package is described that
`includes a vertical section 304 and a horizontal section 306.
`
`In an alternate embodiment, the IC package could include
`only a vertical section 304, and the functionality of the
`horizontal section 306 could be performed by a printed
`circuit board or other substrate to which the package is
`electrically connected. In such an embodiment, the vertical
`section 304 would be connected directly to the printed
`circuit board or other substrate (e.g., using BGA or LGA
`technologies), instead of being connected to a horizontal
`section.
`
`FIG. 4 illustrates a top view of the electrical assembly
`shown in FIG. 3. Specifically, FIG. 4 shows a top view (i.e.,
`a view in the X-Y plane, see axes on FIG. 3) of IC 302,
`vertical section 304, horizontal section 306,
`first
`level
`capacitors 308, and second level capacitors 310.
`The relative and actual dimensions of the vertical section
`
`304 and horizontal section 306 can vary greatly. For
`example,
`the width 402 of vertical section 304 can be
`roughly equal to the width of the IC 302, although this is not
`necessarily so. The width 402 of the vertical section 304
`could be, for example, in a range of approximately 14" to 1",
`
`

`

`US 6,680,218 B2
`
`7
`although it could be wider or narrower as well. The length
`404 of the vertical section 304 is approximately equal to the
`length 404 of the horizontal section 306, in one embodiment,
`although this is not necessarily so. The lengths 404 of the
`vertical and horizontal sections 304, 306 can be roughly
`equal to the length of a standard package that would mate
`with the next level of interconnect. For example, the lengths
`404 could be in a range of approximately 1A1" to 3", although
`they could be wider or narrower as well. Similarly, the width
`406 of the horizontal section 306 can be roughly equal to the
`width of a standard package that would mate with the next
`level of interconnect. The width 406 could be roughly the
`same as the length 404, or the width 406 could be larger or
`smaller than the length 404.
`FIG. 5 illustrates a cross-sectional view of the electrical
`
`assembly of FIG. 3, along section lines 5—5. As described
`previously, bond pads on the bottom surface of IC 302 are
`electrically connected to a complimentary set of bond pads
`on the top surface of vertical section 304 via solder bumps
`or balls,
`in one embodiment. The bond pads of vertical
`section 304 are electrically connected to conductive layers
`512, 514, 516 within vertical section 304.
`Each of these conductive layers 512, 514, 516 could
`include substantially planar areas of conductive material
`and/or conductive traces, which electrically connect the top
`surface bond pads with bond pads on the bottom surface of
`vertical section 304. In one embodiment, a set of one or
`more outer conductive layers 512 or 514 include the sub-
`stantially planar conductive areas, and are dedicated to
`carrying power or ground from horizontal section 306 to IC
`302. In one embodiment, when multiple layers 512, 514 are
`dedicated to each of power and ground, these layers alternate
`between power and ground in order to minimize the induc-
`tance of the conductive loops for first level and second level
`capacitors 308, 310. A second set of one or more inner
`conductive layers 516 include the conductive traces, and are
`dedicated to carrying I/O signals. Each of these conductive
`traces is used to conduct an I/O signal from one top surface
`bond pad to one bottom surface bond pad.
`For ease of illustration, the example illustrated in FIG. 5
`shows ten conductive layers 512, 514, 516, where only two
`layers 512, 514 are used for each of power and ground. This
`leaves six layers 516 that can be dedicated to I/O signals. In
`a more typical package designed for an IC with 40x40 bond
`pads, 40 conductive layers would exist in the vertical section
`304, and perhaps 10 outer layers would be dedicated to
`power and 10 outer layers would be dedicated to ground,
`leaving 20 inner layers that can be dedicated to I/O signals.
`Because I/O signals could be carried across all 40 bond pads
`connected to each of the inner 20 layers, this translates to the
`ability to dedicate up to 800 bond pads to I/O signals. This
`represents a marked improvement over prior art packages,
`where only the outer few rows of bond pads could be
`dedicated to I/O signals because of escape routing issues.
`Assuming a 40x40 pad package, where the outer three rows
`are dedicated to I/O signals, a prior art package could carry
`only about 440 1/0 signals.
`As described previously, one or more discrete, first level
`capacitors 308 are connectable to conductive structures
`(e.g., vias), which electrically connect conductive layers
`512, 514 with one or more side surfaces of vertical section
`304. By using outer layers 512, 514 to connect capacitors
`308 and to convey power and ground, the electrical distance
`between first
`level capacitors 308 and IC 302 can be
`minimized, resulting in a relatively small loop area and a
`relatively low inductance path. In addition, the planar struc-
`tures of outer layers 512, 514 can serve to shield the inner
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`conductive layers 516, thus reducing the amount of external
`noise that could interfere with signals carried across inner
`conductive layers 516. In other embodiments, power, ground
`and I/O signals could be exchanged using any combination
`of outer layers 512, 514 or inner layers 516.
`A set of bond pads on the bottom surface of vertical
`section 304 are electrically connected to a complimentary
`set of bond pads on the top surface of horizontal section 306
`via solder bumps or balls, in one embodiment. The height
`524 of the vertical section 304 is dependent on the number
`of signals being fanned out by vertical section 304, and the
`aspect ratio between the IC pad pitch and the package pad
`pitch, which relates to the amount of space necessary to
`perform the pitch conversion in the Y direction (see axes on
`FIG. 3) between the bond pads on the top surface of the
`vertical section 304 and the bond pads on the top surface of
`the horizontal section 306. In general, the number of signals
`to be fanned out and/or the magnitude of the aspect ratio are
`proportional to the height 524 of the vertical section 304. For
`example, the height 524 of the vertical section 304 could be
`in a range of approximately 1A1" to 1", although it could be
`taller or shorter as well.
`
`The top surface bond pads of horizontal section 306 are
`electrically connected to vias 538 and conductive layers 540,
`542, 544 within horizontal section 306. Each of these
`conductive layers 540, 542, 544 could include planar con-
`ductive areas and/or traces. Along with vias 538, 546,
`conductive layers 540, 542, 544 electrically connect the set
`of top surface bond pads with a set of connectors (e.g., bond
`pads 550 or pins) on the bottom surface 552 of horizontal
`section 306. In one embodiment, one or more top conductive
`layers 540 or 542 are dedicated to carrying power from the
`next level of interconnect (not shown) to vertical section
`304, and one or more top conductive layers 542 or 540 are
`dedicated to connecting vertical section 304 to ground.
`For ease of illustration, the