`
`(12) United States Patent
`US 7,566,960 B1
`(10) Patent N0.:
`Conn
`
`(45) Date of Patent: Jul. 28, 2009
`
`(54)
`
`(75)
`
`INTERPOSING STRUCTURE
`
`6,104,082 A *
`
`8/2000 Berlin et al.
`
`................ 257/665
`
`Inventor: Robert O. Conn, Los Gatos, CA (US)
`
`(73)
`
`Assignee: Xilinx, Inc., San Jose, CA (US)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 112 days.
`
`(Continued)
`FOREIGN PATENT DOCUMENTS
`
`JP
`
`5-160198
`
`*
`
`6/1993
`
`(21)
`
`Appl. No.: 10/698,704
`
`(22)
`
`Filed:
`
`Oct. 31, 2003
`
`Int. Cl.
`
`(51)
`
`(2006.01)
`H05K 1/02
`(2006.01)
`H05K 1/00
`(2006.01)
`H01L 23/02
`US. Cl.
`.............................. 257/686; 257/E23068;
`257/E2307; 257/E23079; 257/777; 257/698;
`257/737; 257/738; 257/723; 257/724; 257/700;
`257/924; 257/678; 361/749; 361/764; 361/735;
`361/790; 361/803; 361/804; 361/767; 361/780;
`361/794
`
`Field of Classification Search ................. 257/686,
`257/777, E23068, E2307, E23079, 737,
`257/738, 723, 724, 700, 698, 924, 678; 361/749,
`361/764, 735, 790, 803, 804, 767, 780, 794;
`438/109, 106, 107
`See application file for complete search history.
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`(52)
`
`(58)
`
`(56)
`
`.................. 361/795
`l/1992 Feng et a1.
`5,081,563 A *
`l/1993 Chance et a1.
`.............. 257/678
`5,177,594 A *
`5,352,926 A * 10/1994 Andrews .................... 257/717
`5,474,458 A * 12/1995 Vafi et a1.
`..................... 439/91
`5,633,785 A
`5/1997 Parker et 31.
`5,640,051 A *
`6/1997 Tomura et a1.
`........... 257/778
`5,705,858 A *
`l/1998 Tsukamoto .......... 257/778
`
`8/1998 Klein ......................... 361/774
`5,796,590 A *
`5,854,534 A
`12/1998 Berlin et a1.
`5,973,930 A * 10/1999 Ikeda et a1.
`
`................. 361/768
`
`(Continued)
`OTHER PUBLICATIONS
`
`U.S.App1. No. 10/698,690, filed Oct. 31, 2003, Conn.
`
`(Continued)
`
`Primary ExamineriAlexander 0 Williams
`(74) Attorney, Agent, or FirmiLester Wallace; Robert M.
`Brush
`
`(57)
`
`ABSTRACT
`
`A capacitive interposer (caposer) is disposed inside an inte-
`grated circuit package between a die and an inside surface of
`the package. Conductive layers within the caposer constitute
`a bypass capacitor. In a through-hole caposer, micro-bumps
`on the die pass through through-holes in the caposer and
`contact corresponding landing pads on the package. As they
`pass through the caposer, power and ground micro-bumps
`make contact with the plates of the bypass capacitor. In a via
`caposer, power and ground micro-bumps on the die are
`coupled to power and ground landing pads on the package as
`well as to the plates of the bypass capacitor by power and
`ground vias that extend through the caposer. In signal redis-
`tribution caposer, conductors within the caposer redistribute
`signals between die micro-bumps and package landing pads.
`In an impedance matching caposer, termination structures
`within the caposer provide impedance matching to a printed
`circuit board trace.
`
`13 Claims, 16 Drawing Sheets
`
`{J
`
`553;)”ch
`1012
`
`CAPOSER
`1018
`
`'TTTTJJTTTTT“
`o. _.-_.4 .- .- ,
`
`
`
`SOLDER
`BALLS
`
`1014
`L$“A%'§G
`
`IVM 1001
`IPR of U.S. Pat. No. 7, 566, 960
`
`
`
`US 7,566,960 B1
`
`Page 2
`
`US. PATENT DOCUMENTS
`
`~~~~~~~~~~~~~ 257/678
`
`6,137,161 A * 10/2000 Gillilandetal.
`6,144,225 A
`11/2000 Lesea
`6,242,932 B1*
`6/2001 Hembree .................... 324/755
`~361/704
`6,246,583 131*
`6/2001 Cronin etal~
`
`~438/118
`6,294,407 B1*
`9/2001 Jacobs ~~~~~~~~
`1/2002 Alagaratnametal.
`6,335,491 B1*
`174/260
`6/2002 HirashimaetaL ~~~~~~~~~~ 257/737
`6400019 B1*
`6,417,688 B1
`7/2002 Dabral etal.
`361/306.3
`6,477,034 B1* 11/2002 Chakravorty et al.
`6,525,922 B2*
`2/2003 Wineretal.
`...........
`361/306.3
`~-
`6529027 131*
`3/2003 Akrametal.
`324/758
`
`4/2003 Edwards et al~
`6,541,365 B2*
`438/612
`6555920 B2*
`4/2003 Chung etal~
`257/779
`
`.257/700
`6,563,210 B2*
`5/2003 Sankman
`
`9/2003 Bohr ~~~~~~~~~~~~~~~~
`~257/700
`6,617,681 B1*
`
`9/2003 Alagaratnam et a1.
`6,618,938 131*
`29/840
`...........
`6,661,088 B1 * 12/2003 Yoda et a1.
`257/700
`6,664,643 B2* 12/2003 Emoto ........
`.257/777
`6,671,947 B2*
`1/2004 Bohr ..........
`.. 29/846
`
`................ 438/108
`6,680,218 B2*
`1/2004 Chung et a1.
`6,683,781 B2
`1/2004 Ho etal.
`6,699,046 B2
`3/2004 Ho etal.
`6,717,821 B2*
`4/2004 Miller et a1.
`................ 361/760
`6,724,638 131*
`4/2004 Inagaki et a1.
`..
`.. 361/763
`
`6,734,540 B2*
`5/2004 Fritz .......................... 257/686
`6,754,407 B2
`6/2004 Chakravorty etal.
`6,756,628 B2*
`6/2004 Echigo et a1.
`............... 257/306
`
`438/107
`6,833,285 131* 12/2004 Ahn et 31~
`~~~~~~
`6,856,167 B2*
`2/2005 Ozguz et a1.
`326/41
`
`4/2005 Conn ~~~~~~~~~~~~~~~
`- 174/534
`6,875,921 Bl *
`5/2005 Alexander et a1.
`257/678
`6,891,258 B1*
`
`..
`6,894,396 B2*
`5/2005 Shioga et a1.
`257/777
`6,970,362 B1* 11/2005 Chakravorty ................ 361/782
`
`
`
`6/2007 Conn
`7,233,061 B1
`............... 257/778
`7/2007 Farooqetal.
`7,245,022 B2*
`2001/0040272 A1* 11/2001 Mashino ..................... 257/532
`2002/0036340 A1*
`3/2002 Matsuo et a1.
`.............. 257/698
`
`2002/0041489 A1*
`4/2002 Fritz
`361/767
`7/2002 Winer et a1.
`............. 361/306.3
`2002/0085336 A1*
`2002/0088977 A1*
`7/2002 Morietal.
`.................... 257/68
`2002/0182804 A1* 12/2002 Echigo et al.
`438/250
`
`1/2003 Sathe ......................... 257/780
`2003/0001287 A1*
`2003/0006494 A1*
`1/2003
`257/686
`2003/0164548 A1*
`9/2003
`. 257/738
`2004/0027813 A1*
`2/2004
`361/767
`2004/0067605 A1*
`4/2004 Koizumi
`..................... 438/108
`
`2004/0201367 A1* 10/2004 Echigo et a1.
`320/166
`.......... 324/754
`2004/0239349 A1* 12/2004 Yamagishi et a1.
`2005/0017333 A1
`1/2005 Bohr
`2005/0179128 A1*
`8/2005 Shiogaet a1.
`
`
`
`............... 257/724
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`JP
`JP
`
`”1998
`*
`10'32070
`9/1999
`*
`11460860
`2004'79745 A * ”004
`2005444163
`* ”005
`
`OTHER PUBLICATIONS
`U~S~APP1~ No, 10/698,906, filed Oct. 31, 2003, Conn.
`U.S.App1. No. 10/377,863,filed Feb. 28, 2003, Trimberger etal.
`Adel
`Corporation;
`Application
`Note
`«The
`A0161
`ExtenderiExtending the Life of Existing Designs”; Jan. 2002;
`available fromActelCorporation; pp, 1.4,
`Fujipoly; Electronic Packaging Components, downloaded Oct. 10,
`2003 from Fujipolyflpages.
`
`* cited by examiner
`
`
`
`US. Patent
`
`Jul. 28, 2009
`
`Sheet 1 0f 16
`
`US 7,566,960 B1
`
`PACKAGED DEVICE 102
`
`
`
`INTEHPOSER 103 zl’lzt’lz
`
`
`
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`VII/III/I/I/I/I/Il/I/I/I/I/I/I/I/A
`
`212421212
`
`
`
`/
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`
`I
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`I
`I
`I
`
`/
`
`’
`
`PLANE 220
`
`AREA 230
`
`
`
`
`
`US. Patent
`
`Jul. 28, 2009
`
`Sheet 2 0f 16
`
`US 7,566,960 B1
`
`103 THROUGH
`PLANE 220
`
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`FIG. 4
`
`
`
`U.S. Patent
`
`Jul. 28, 2009
`
`Sheet 3 of 16
`
`US 7,566,960 B1
`
`541
`
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`
`Jul. 28, 2009
`
`Sheet 4 of 16
`
`US 7,566,960 B1
`
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`
`US. Patent
`
`Jul. 28, 2009
`
`Sheet 5 0f 16
`
`US 7,566,960 B1
`
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`
`US. Patent
`
`Jul. 28, 2009
`
`Sheet 6 0f 16
`
`US 7,566,960 B1
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`US. Patent
`
`Jul. 28, 2009
`
`Sheet 7 0f 16
`
`US 7,566,960 B1
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`Sheet 14 0f 16
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`US 7,566,960 B1
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`Sheet 15 0f 16
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`Sheet 16 0f 16
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`US 7,566,960 B1
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`US 7,566,960 B1
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`2
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`The present invention relates to an interposer disposed
`inside an integrated circuit package between a die and the
`package, wherein the interposer provides bypass capacitance,
`signal redistribution functionality and/or signal termination
`structures close to the semiconductor die.
`
`BACKGROUND INFORMATION
`
`Systems that include integrated circuit (IC) devices typi-
`cally include decoupling capacitors (also known as bypass
`capacitors) as well. A typical decoupling capacitor is a
`capacitor coupled between the power and ground pins (i.e.,
`terminals) of a packaged IC to reduce noise on the power
`system within the IC. While in some cases the IC itself
`includes some decoupling capacitance, the amount of capaci-
`tance required is such that one or more additional discrete
`decoupling capacitors are usually added external to the pack-
`aged device.
`the location of these discrete decoupling
`In the past,
`capacitors was a less important issue. The switching fre-
`quency of a device was relatively low, e.g., in the range of
`hundreds of kHz (kilohertz) to tens of MHZ (megahertz). The
`transient currents within the device were also relatively low.
`Hence, parasitic inductance in the printed circuit board (PCB)
`mountings was not an important consideration. For example,
`for an IC mounted in a medium-performance package,
`whether leaded or surface-mounted to the PCB, a 0.1 uF
`(microfarad) decoupling capacitor could typically be
`mounted on the PCB anywhere within a few inches of the
`packaged IC.
`Many ICs now operate at clock frequencies in the hundreds
`of MHZ. At these higher frequencies, transient currents are
`significantly higher than in the past, and parasitic inductance
`is a much more important issue. Parasitic inductance within
`the capacitors themselves has been reduced by improving the
`packaging of the capacitors, e.g., by using only surface-
`mount packages and by reducing the size of the packages.
`(Smaller packages inherently have a lower parasitic induc-
`tance.) Parasitic inductance within the PCB mountings has
`also been reduced through improved layout techniques, e.g.,
`by using dedicated power planes in the PCB, by improving
`capacitor land geometries, and by careful placement of the
`capacitors to reduce the distance between the packaged IC
`and the capacitors.
`However, as operating frequencies continue to increase,
`even these measures become inadequate. One bottleneck in
`the current path between a decoupling capacitor and the asso-
`ciated packaged IC are the vias that transport charge from the
`capacitor lands through the PCB to the powerplanes, and then
`from the power planes through the PCB to the device. These
`vias can contribute parasitic inductance in the range of l .5 nH
`(nanohenrys) each. If this via inductance could be reduced or
`eliminated, providing for high-frequency transient current
`would be much easier.
`
`Therefore, it is desirable to provide systems and structures
`that provide decoupling capacitance to IC devices with
`reduced capacitor parasitic inductance. It is further desirable
`to reduce via parasitic inductance in these systems and struc-
`tures.
`
`In addition to the issues set forth above, an active circuit
`disposed on an integrated circuit die typically draws spikes of
`current from local power supply lines on the integrated circuit
`die. An active circuit, for example, can have a VCC power
`
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