STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTELLECTUAL VENTURES MANAGEMENT, LLC
`Petitioner
`
`V.
`
`XILINX, INC.
`Patent Owner
`
`Case IPR2012-00018
`
`Patent 7,566,960
`
`DECLARATION OF MORGAN T. JGHNSON IN SUPFORT OF
`
`PETITEONER’S REPLY TO PATENT OWNER
`
`RESPONSE TO PETITION
`
`IVM1011
`
`IPR2012-00018
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTELLECTUAL VENTURES MANAGEMENT, LLC
`Petitioner
`
`V.
`
`XILINX, INC.
`Patent Owner
`
`Case IPR2012-00018
`
`Patent 7,566,960
`
`DECLARATION OF MORGAN T. JGHNSON IN SUPFORT OF
`
`PETITEONER’S REPLY TO PATENT OWNER
`
`RESPONSE TO PETITION
`
`IVM1011
`
`IPR2012-00018
`
`
`
`IPR2012-00018
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`Patent 7,566,960
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`I, Morgan T. Johnson, declare as follows:
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`1.
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`I have been retained by Intellectual Ventures Management, LLC
`
`(“IVM”) to provide declaratory evidence in inter partes review of U.S. Patent No.
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`7,566,960 to Robert O. Conn (“the ‘960 Patent”), which is assigned to Xilinx, Inc.
`
`2.
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`I have reviewed and am familiar with the specification and the
`
`claims of the ‘960 Patent filed on October 31, 2003.
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`3.
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`I have reviewed and am familiar with the following references:
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`U.S. Patent No. 6,730,540 to Siniaguine (“Siniaguine”; IVM 1004); U.S. Patent
`
`No. 6,469,908 to Patel et al. (“Patel”; IVM 1005); U.S. Patent No. 6,970,362 to
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`Chakravortfy (“Chakravorty ‘362”; IVM 1007); and U.S. Patent No. 6,423,570 to
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`Ma et al. (“Ma”; IVM 1008). I understand that these references form the basis for
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`the grounds of rejections set forth in the Petition for Inter Partes Review of the
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`‘960 Patent. I have also reviewed the Declaration of Dr. Dean Neikirk in support of
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`the Patent Owner Response (“Neikirk Declaration”; XLNX 2007). I will cite to
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`these references using the following format: (IVM 1004, 1:1-10). This example
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`citation points to the Siniaguine specification at colunm 1, lines 1-10.
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`4.
`
`I am familiar with and am a practitioner of the technology at issue
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`and the state of the art at the time the application leading to the ‘960 Patent was
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`2
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`IPR20 12-0001 8
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`Patent 7,566,960
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`filed. The filing date of the ‘960 Patent was October 31, 2003. Based on the
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`technologies disclosed in the ‘960 Patent, I believe that one of ordinary skill in the
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`art would have a B.S. degree in Electrical Engineering or equivalent training, as
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`well as 3-5 years of experience in the field of electronics packaging and
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`interconnect design.
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`5.
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`I have been asked to provide my technical review, analysis,
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`insights and opinions regarding the above-noted references.
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`Qualifications
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`6.
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`I have more than 29 years of experience in the electronic
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`interconnect and semiconductor industries.
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`7.
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`I earned a Bachelor of Science degree in Graphics from the
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`University of Oregon. My studies included subjects in advanced mathematics
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`related to geodesic domes. I also attended The Art Center College of Design in
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`Pasadena, California, where I majored in Industrial Design.
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`8.
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`I currently serve as Chief Scientist at Advanced Inquiry Systems,
`
`Inc. (AISI), a company that I founded in 2002. As Chief Scientist, my research
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`focuses on tools and interfaces for full-wafer testing of products such as NAND
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`3
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`IPR2012—00018
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`Patent 7,566,960
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`and NOR flash, Dynamic Random Access Memory (DRAM) and certain logic
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`devices. My research is additionally driven by the semiconductor industry’s
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`demand for highly-parallel wafer testing of System-on-Chips (SOCs), such as
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`processors for mobile devices. Through my research, AISI has implemented a
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`device that achieves contact with up to 500,000 pads per wafer during tests. AISI
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`was founded on my patented work in this area and benefits from over 30 issued
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`patents.
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`9.
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`I co-founded Prototype Solutions Corporation in 1994, a company
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`focused on using advanced interconnect and packaging technology to provide
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`quick-tum prototypes and hardware emulation using programmable logic devices
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`such as Field Programmable Gate Arrays (FPGAS). The technology is used to
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`prototype highly—complex Central Processing Units (CPUs), Graphic Processing
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`Units (GPUS), System on Chips (SOCS) and Application Specific Integrated
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`Circuits (ASICS).
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`10.
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`I founded LaserPath Corp. in 1983. LaserPath was a
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`semiconductor company focused on laser programmable semiconductor gate
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`arrays. The foundation of this technology was based on my inventions and patents.
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`LaserPath achieved over 200 design wins in the first 9 months of sales—setting a
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`4
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`IPR2012-00018
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`record. LaserPath’s technology included Gate Arrays programmed with a laser in a
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`ceramic package, tested and delivered to customer in as little as two hours and
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`more typically within 5 business days. This rapid Gate Array turnaround time and
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`large number of design wins drastically shifted the ASIC business from a 12-week
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`delivery to a new standard of 3- week delivery.
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`1 1.
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`From 1980-1981, I researched controlled impedance, instant tum-
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`around circuit boards for the Cray 2 computer system. My research was funded by
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`Cray Computer Corporation—Boulder, Colorado Team. This research included the
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`development of laser-programmed printed circuit boards, multi-chip module
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`structures and emitter—coupled logic on-chip wiring. This research was the genesis
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`for my later-developed technology that evolved into LaserPath.
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`12.
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`In addition to my semiconductor industry experience, I am an
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`inventor on 36 U.S. patents related to interconnects, high-speed connectors and
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`semiconductors. Also, I have a faculty appointment as Adjunct Professor in the
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`Electrical Engineering School at Portland State University in Portland, Oregon. I
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`have also been a guest lecturer at the Jet Propulsion Laboratory (JPL) in Pasadena,
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`California.
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`
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`IPR2012-00018
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`13. My professional background and technical qualifications are stated
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`above and are also reflected in my Curriculum Vitae, which is attached as IVM
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`1020. I am being compensated at a rate of $300.00 per hour, with reimbursement
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`for actual expenses, for my work related to this inter partes review proceeding. My
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`compensation is not dependent on and in no way affects the substance of my
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`statements in this Declaration.
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`14.
`
`I understand that “anticipation” is a question of fact and that for a
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`reference to anticipate a claimed invention it must disclose each and every element
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`set forth in the claim for that invention. I further understand that the requirement of
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`strict identity between the claim and the reference is not met if a single element or
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`limitation required by the claim is missing from the applied reference.
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`15.
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`It is my further understanding that a prior art reference is
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`anticipatory only if it discloses each and every limitation of the claim (as properly
`
`construed) at issue. In other words, every limitation of a claim must identically
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`appear in a single prior art reference for it to anticipate a claim.
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`16.
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`It is also my understanding that a claimed invention is unpatentable
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`if the differences between the invention and the prior art are such that the subject
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`IPR20l2-00018
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`matter as a whole would have been obvious at the time the invention was made to a
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`person having ordinary skill in the art to which the subj ect matter pertains.
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`17.
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`It is my understanding that “obviousness” is a question of law
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`based on underlying factual issues including the content of the prior art and the
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`level of skill in the art. I understand that for a single reference or a combination of
`
`references to anticipate the claimed invention, a person of ordinary skill in the art
`
`must have been able to arrive at the claims by altering or combining the applied
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`references.
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`18.
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`I also understand that when considering the obviousness of a patent
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`claim, one should consider whether a teaching, suggestion, or motivation to
`
`combine the references exists so as to avoid impennissibly applying hindsight
`
`when considering the prior art. I understand this test should not be rigidly applied,
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`but that the test can be important to avoid such hindsight.
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`Analysis
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`and Patel.
`
`19.
`
`I now turn to certain aspects of Chakravorty ‘362, Siniaguine, Ma
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`
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`IPR2012-00018
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`Patent 7,566,960
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`20.
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`Interposer 310 in FIG. 3 of Chakravorty ‘3 62 is disposed in an
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`integrated circuit package. Chakravorty ‘3 62 discloses that, in reference to FIG. 3
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`and other embodiments, “the inventive subject matter is not to be construed as
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`limited to use in C4 packages, and it can be used with any other type of IC package
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`where the herein-described features of the inventive subject matter provide an
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`advantage.” IVM 1007, 10:8-11. The term “C4” is an abbreviation for controlled
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`collapse chip connection. C4 packages are a type of integrated circuit (IC)
`
`package. C4 integrated circuit packages are also referred to as “flip chip”
`
`integrated circuit packages.
`
`21.
`
`In FIG. 3 of Chakravorty, interposer 310 is disposed between an IC
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`die 300 and a primary substrate 320. Solder balls 301 provide electrical contacts
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`between IC die 300 and interposer 310. Similarly, solder balls 311 provide
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`electrical contacts between interposer 310 and primary substrate 320. The
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`arrangement of IC die 300, interposer 310, primary substrate 320 and solder balls
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`301 and 311 in FIG. 3 is the same as the relative arrangement of IC die 40,
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`interposer 50, primary substrate 60 and solder bumps 42 and 58 in FIG. 2 of
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`Chakravorty ‘362. Solder balls 301 and 311 in FIG. 3 form a portion of the C4
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`integrated circuit package.
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`
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`22. Another portion of the C4 integrated circuit package in FIG. 3 of
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`Chakravorty ‘362 is an underfall encapsulant that fills in the areas between solder
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`balls 30l(between IC die 300 and interposer 310) and the areas between solder
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`balls 31 1 (between interposer 310 and primary substrate 320). Interposer 310 can
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`be fabricated using high thermal coefficient of expansion (HITCE) technology. See
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`IVM 1007, 7:42-46. Primary substrate 320 can be fabricated from an organic
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`material, which is also subject to HITCE. See id., 421-3. An underfill encapsulant is
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`required to mitigate the effects of HITCE. It is well known that underfill
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`encapsulants serve this purpose:
`
`One of the major reasons why solder-bumped flip chip on
`low-cost or organic CSP substrates works is because of the
`underfill epoxy encapsulant. It reduces the effect of the
`global thermal expansion mismatch between the silicon chip
`and the organic substrate, i.e., it reduces the stresses and
`strains in the flip-chip solder bumps (since the chip and the
`substrate are tightly held by the underfill) and redistributes
`over the entire chip area the stresses and strains that would
`otherwise be increasingly concentrated near the corner
`solder bumps of the chip. Other advantages of underfill
`encapsulant are that it protects the chip from moisture, ionic
`contaminants, radiation, and hostile operating environments
`such as thermal, mechanical pull, shear, and twist, and
`shock/vibration.
`
`IVM 1014, p. 19.
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`
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`23.
`
`In referring to FIG. 3 of Chakravorty ‘362, the C4 integrated
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`circuit package includes primary substrate 320 and underfill encapsulant between
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`IC die 300 and interposer 310 and between interposer 310 and primary substrate
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`320. The underfill encapsulant can surround interposer 310, in which the underfill
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`encapsulant forms sidewalls of the C4 integrated circuit package—thus
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`surrounding interposer 310. Here, interposer 310 is disposed inside the C4
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`integrated circuit package. Further, the portion or area in which solder balls 311
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`reside in FIG. 3 of Chakravorty ‘362 is an inside surface of the C4 integrated
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`circuit package. Interposer 310 is also between IC die 300 and the inside surface of
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`the C4 integrated circuit package.
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`24.
`
`Similar to Chakravorty ‘362, Siniaguine also discloses an
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`integrated circuit package. FIG. 12 of Siniaguine illustrates a ball grid array (BGA)
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`package. See IVM 1004, 7:61-62. A BGA package is a type of integrated circuit
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`package.
`
`25.
`
`In FIG. 12 of Siniaguine, “[w]iring substrate 330 is a BGA
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`substrate (e.g., plastic) with solder balls 810 on the bottom .
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`.
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`.
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`. Underfill 830 fills
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`the area between the circuits 310, 320 and the area between interposer 320 and
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`substrate 330.” IVM 1004, 7:62-66. Underfill 830 serves a similar purpose as the
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`10
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`
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`underfill encapsulant of Chakravorty ‘362 discussed above. Also, the arrangement
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`of circuit 310, interposer 320 and substrate 330 is the same as the relative
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`arrangement of IC die 40, interposer 50 and primary substrate 60 from FIG. 2 of
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`Chakravortfy ‘3 62.
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`26.
`
`Dr. Neikirk states that “IVM did not assert that Siniaguine
`
`provides any teaching relevant to ‘an interposing structure disposed inside the
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`integrated circuit package.’ I agree that it does not.” XLNX 2007, nn 35. I disagree
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`with Dr. Neikirk. Indeed, the BGA integrated circuit package of Siniaguine
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`includes wiring substrate 330 (e.g., BGA substrate) and underfill 830. As
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`illustrated in FIG. 12, underfill 830 surrounds interposer 320, in which underfill
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`830 forms sidewalls of the BGA integrated circuit package. This is similar to a fill
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`material 1520 in FIG. 15 of Siniaguine, which illustrates that fill material 1520
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`forms the right and left sidewalls of an integrated circuit package; thus surrounding
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`interposer 320. See IVM 1004, 8:20-55. As a result, interposer 320 in FIG. 12 is
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`disposed inside the BGA integrated circuit package. Further, the portion or area in
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`which contacts 323 (not annotated) reside in FIG. 12 of Siniaguine is an inside
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`surface of the BGA integrated circuit package. In reference to FIG. 4 of
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`Siniaguine, pads 388 are disposed on the inside surface of the BGA integrated
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`ll
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`circuit package. lnterposer 320 is also between IC 310 and the inside surface of the
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`BGA integrated circuit package.
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`27.
`
`I now turn to the combination of the teachings from Siniaguine
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`with the teachings from Ma. In my declaration in support of inter partes review of
`
`the ‘960 Patent, I stated that:
`
`The modifications to the first pattern of micro-bumps disposed
`on IC 310 in FIG. 4 of Siniaguine to have a substantially
`identical pattern as the second pattern of pads 388 disposed on
`wiring substrate 330 as taught by Ma would have been a
`relatively simple substitution of the micro—bump/pad pattem
`illustrated in FIG. 4 of Siniaguine with the micro—bump/pad
`pattern illustrated in FIG. 18 of Ma. This substitution can be
`applied using known packaging techniques and would not
`change the operation of the semiconductor integrated circuit
`structure of Siniaguine. Rather, the substitution would provide
`flexibility in the signal distribution between IC 310 and wiring
`substrate 330 of Siniaguine.
`
`IVM 1002, ‘ll 89.
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`The above statement is one reason an electronic packaging designer would modify
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`the first pattern of micro-bumps disposed on IC 310 in FIG. 4 of Siniaguine to
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`have a substantially identical pattern as the second pattem of pads 388 based on the
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`teachings of Ma.
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`12
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`28.
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`Dr. Neikirk states that “even if Siniaguine could be properly
`
`combined with Ma or Chakravorty ‘362, the combination does not teach ‘wherein
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`the first pattern and the second pattem are substantially identical patterns’ as
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`recited in claim l.” XLNX 2007, €| 46. In his declaration, Dr. Neikirk illustrates a
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`combination of FIG. 18 of Ma placed on top of FIG. 4 of Siniaguine. See id., ‘,1 47.
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`Based on this figure, Dr., Neikirk states that “Ma shows that small solder balls 228
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`are regularly spaced apart, while Siniaguine shows that pads 388 are irregularly
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`spaced apart. The gap between the third pad and the fourth pad is substantially
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`larger than the gap between any other two pads. Thus, even though there are five
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`solder balls 228 and five pads 388, their patterns of arrangement are not
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`substantially identical.” Id. , emphasis in oréginal. I disagree with Dr. Neikirk
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`because Siniaguine does not disclose the dimensions of the micro—bumps disposed
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`on IC 310 or pads 388 in FIG. 4. Siniaguine also does not disclose that FIG. 4 is
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`drawn to scale. Indeed, Siniaguine states that “[t]he examples in this section are
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`provided for illustration and not to limit the invention. The invention is not lirrsited
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`to particular circuits, materials, processes, process parameters equipment, or
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`dimensions.” IVM 1004, 3:35-38.
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`13
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`29.
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`Similarly, Ma does not disclose the dimensions of the micro-
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`bump/pad pattern illustrated in FIG. 18. Ma also does not disclose that FIG. 18 is
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`drawn to scale.
`
`30.
`
`Based on their disclosures, FIG. 4 of Siniaguine and FIG. 18 of Ma
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`can be used as a guideline to manufacture micro-bumps disposed on IC 310 in FIG.
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`4 of Siniaguine to have a substantially identical pattern as the pads 388 disposed on
`
`wiring substrate 330 as taught by FIG. 18 of Ma. For example, the pattern of solder
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`balls 228 in FIG. 18 of Ma (e.g., 1 X N array, where N is an integer greater than 1)
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`and the pattern of pads in 388 in FIG. 4 of Siniaguine (e.g., 1 X N array, where N is
`
`an integer greater than 1) can be designed such that they are identical to one
`
`another. Since the pattem of solder balls 228 and the pattern of pads 388 both have
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`a 1 X N array pattern, their patterns are identical to one another.
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`31.
`
`In addition to having identical patterns, the pattern of solder balls
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`and the pattern of pads 388 may be designed such their respective sizings/spacings
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`are similar to one another. Siniaguine and Ma however do not disclose sufficient
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`information on FIGS. 4 and 18, respectively, to manufacture the resulting
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`combination to scale. Thus, overlaying figures from Siniaguine and Ma with one
`
`another—such as the attempt by Dr .Neikirk on page 20 of his declaration——does
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`14
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`not provide an accurate depiction of relative sizings/spacings within each of the
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`references’ figures, as well as relative sizings/spacings between a combination of
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`figures from the references.
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`32.
`
`Dr. Neikirk states that “[m]odifying the interposer of Siniaguine
`
`such that ‘the first pattern and the second pattern are substantially identical
`
`patterns’ would render the interposer [of Siniaguine] inoperable for its intended
`
`purpose of distributing clock signals.” XLNX 2007, 1] 42. I disagree with Dr.
`
`Neikirk because the clock distribution network of Siniaguine can be implemented
`
`with the first pattern of micro—bumps disposed on IC 310 in FIG. 4 of Siniaguine
`
`having a substantially identical pattem as the second pattem of pads 388—e.g., the
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`number of micro—bumps can equal the number of pads. In referring to FIG. 4,
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`Siniaguine states that “[i]n one example, contact pad 323.1 is a power supply input.
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`Contact pad 323.3 is a ground input. Contact pad 323.2 [is] an input, output, or
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`input/output terminal for a signal. The invention is not limited to any particular
`
`signals that can be routed through interposer 320.” IVM 1004, 4:31-35. Further,
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`“[c]ontact pads 323 are bonded to pads 388 on wiréng substrate 330.” Id., 4:36-37.
`
`33.
`
`Since interposer 320 is not limited to any particular signals routed
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`through it, the first pattern of micro—bumps disposed on IC 310 can have a
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`15
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`Patent 7,566,960
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`substantially identical pattern as the second pattern of pads 388—e.g., the number
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`of micro-bumps can equal the number of pads. For example, interposer 320 can
`
`have a first pad 388 electrically coupled to a first micro-bump on IC 310, a second
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`pad 388 electrically coupled to a second micro-bump on IC 310 and a third pad
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`388 electrically coupled to a third micro-bump on IC 310. First pad 388 can be a
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`power supply input, second pad 388 can be a ground input and third pad 388 can
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`be a clock input. Correspondingly, the first micro-bump can provide the power
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`supply signal, the second micro-bump can provide the ground signal and the third
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`micro-bump can provide the clock signal to IC 310. In this example, the number of
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`micro-bumps (3) equals the number of pads (3).
`
`34.
`
`In the above example, a clock distribution network can be
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`implemented with a single clock input to IC 310 provided by the third micro-bump
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`(from interposer 320). Multiple clock inputs to IC 310 (from multiple micro-
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`bumps) are not required to implement the clock distribution network. This is
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`because Siniaguine states that “[i]nterposer 320 may contain only a part of a clock
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`distribution network. For example, interposer 320 may contain only a sub-tree
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`1 10S (FIG. 6) of a tree network 110. Sub-tree l 10S consists of a number of tree
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`levels including the root 120. The rest of network 110 may be in circuit 3 10.” See
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`16
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`Patent 7,566,960
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`IVM 1004, 5:54-58. The clock distribution network implemented in interposer 320
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`and circuit 310 is not limited to the clock structure of FIG. 6. Other clock
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`structures—like the structure of FIG. 2—can be implemented in interposer 320 and
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`circuit 310. See IVM 1004, 3:46-49 (“Circuit 320 is an interposer that contains
`
`clock distribution networks 110. The clock distribution networks can be of any
`
`type, including the types shown in FIGS. 1, 2, or other types, known or to be
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`inVented.”).
`
`35.
`
`The grid-type clock distribution network in FIG. 2 can be
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`implemented in interposer 320 and circuit 310. This grid-type clock distribution
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`network has lines 150 that form a grid with horizontal and Vertical lines being
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`connected at intersection points. See IVM 1004, 1:28-36. A clock signal is
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`delivered to a terminal 120 at the center of the grid, amplified by a buffer 160.1
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`and distributed to buffers 160.2 at the edges of the grid. See id. Each buffer 160.2
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`drives a horizontal or Vertical line 150. See id. Clock terminals 130 can be
`
`positioned on lines 150 and connected to circuit blocks. See id.
`
`36.
`
`In implementing the grid-type clock distribution network of FIG. 2
`
`in interposer 320 and circuit 310 of FIG. 4, interposer 320 can contain a portion of
`
`the clock distribution network and circuit 310 can contain the remainder of the
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`17
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`network. For example, interposer 320 can include clock terminal 120 (eg, a clock
`
`input from third pad 388) and buffer 160.1. The amplified clock signal from buffer
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`160.1 can feed into IC 310 via the third micro-bump. The remainder of the clock
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`distribution network——e.g., buffers 160.2, horizontal/Vertical lines 50 and clock
`
`terminals l30—can be implemented in circuit 310. Buffers 160.2 would receive
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`the amplified clock signal from buffer 160.1 via the third micro-bump and
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`distribute the clock signal to terminals 130 Via horizontal/Vertical lines 50.
`
`37.
`
`In summary, implementation of the grid-type clock distribution
`
`network of FIG. 2 in interposer 320 and circuit 310 of FIG. 4 is one example in
`
`which a clock distribution network can be implemented in the interposer design of
`
`Siniaguine while maintaining an equal number of micro-bumps and pads 388.
`
`38.
`
`The number of micro-bumps and pads 388 can also be equal to one
`
`another in other clock distribution examples. For example, interposer 320 can have
`
`a first pad 388 electrically coupled to a first micro-bump on IC 310, a second pad
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`388 electrically coupled to a second micro-bump on IC 310, a third pad 388
`
`electrically coupled to third, fourth and fifth micro-bumps on IC 310 and fourth,
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`fifth and sixth pads 388 coupled to a sixth micro-bump on IC 310. First pad 388
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`can be a power supply input, second pad 388 can be a ground input, third pad 388
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`18
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`Patent 7,566,960
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`can be a clock input and fourth, fifth and sixth pads 388 can be clock outputs.
`
`Correspondingly, the first micro-bump can provide the power supply signal to IC
`
`310, the second micro-bump can provide the ground signal to IC 310, the third,
`
`fourth and fifth micro-bumps can provide clock signals to IC 310 and the sixth
`
`micro-bump can provide a clock output from IC 310. The sixth micro-bump can
`
`provide the clock output to fourth, fifth and sixth pads 388, which can be
`
`electrically coupled to external circuits that use the clock output from the sixth
`
`micro-bump (Via IC 310). In this example, the number of micro-bumps (6) equals
`
`the number of pads (6).
`
`39. My analysis above with regard to Chakravorty ‘362, Siniaguine
`
`and Ma does not change my analysis as to the combination of Chakravorty ‘362,
`
`Siniaguine and Patel from my declaration in support of inter partes review of the
`
`‘960 Patent. See IVM 1002, fiffi 82-83. The analysis above also does not change my
`
`analysis as to the combination of Siniaguine, Ma, Chakravorty ‘362 and Patel from
`
`my declaration in support of inter partes review of the ‘960 Patent. See IVM 1002,
`
`n 1 04-105.
`
`I hereby declare that all statements made herein of my own knowledge are
`
`true and that all statements made on information and belief are believed to be true;
`
`19
`
`
`
`IPR2012-00018
`
`Patent 7,566,960
`
`and further that these statements were made with the knowledge that willful false
`
`statements and the like so made are punishable by fine or imprisonment, or both,
`
`under Section 1001 of Title 18 of the United States Code.
`
`Executed this 2 '7 day of August 2013 in Portland, OR.
`
`Respectfully subi -,
`/
`
`//
`
`/ 0N
`
`'
`t_.z"""" \
`M 1. T If
`/
`
`\__
`/ \
`
`/
`
`20
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