0
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`•
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`TEXAS INSTRUMENTS
`
`7000
`
`TMS7000 Family Microarchitecture
`
`User's Guide
`
`COMPASS EXH. 1010 - Page 1 of 43
`
`

`

`IMPORTANT NOTICES
`
`Texas Instruments reserves the right to make changes at any time to improve design and to supply the best possible product for the
`spectrum of users.
`
`The TMS7000 Family Microarchitecture User's Guide (MP #0611 is printed in the United States of America and is copyrighted by
`Texas Instruments Incorporated. All rights reserved. No part of these publications may be reproduced in any manner including
`storage in a retrieval system or transmittal via electronic means, or other reproduction in any form or any method (electronic,
`mechanical, photocopying, recording, or otherwise) without prior written permission of Texas Instruments Incorporated.
`
`Information contained in these publications is believed to be accurate and reliable. However, responsibility is neither assumed for its
`use nor for any infringement of patents or rights of others that may result from its use. No license is granted by implication or other-
`wise under any patent or patent right of Texas Instruments or others.
`
`COMPASS EXH. 1010 - Page 2 of 43
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`

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`TMS7000 FAMILY MICROARCHITECTURE USER'S GUIDE
`
`TABLE OF CONTENTS
`
`1.
`
`2.
`
`3.
`
`4.
`
`INTRODUCTION (cid:9)
`1.1
`General Information (cid:9)
`Initial Family Members (cid:9)
`1.2
`1.3
`TMS7000 Family Address Space (cid:9)
`1.4
`Basic TMS7000 Architecture (cid:9)
`
`MICROINSTRUCTION EXECUTION (cid:9)
`2.1
`Microinstruction Format (cid:9)
`Microinstruction Cycle Timing (cid:9)
`2.2
`Memory Cycle Timing (cid:9)
`2.3
`Short Memory References (cid:9)
`2.3.1
`2.3.2
`Long Memory References (cid:9)
`2.3.3
`Interrupt Vector Reads (cid:9)
`2.4
`Memory Control Signals (cid:9)
`
`TMS7000 CPU INTERNAL ORGANIZATION (cid:9)
`3.1
`Organization of the TMS7000 CPU (cid:9)
`P BUS (cid:9)
`3.2
`3.3
`N BUS (cid:9)
`3.4
`AL BUS (cid:9)
`3.5
`AH BUS (cid:9)
`3.6
`0 BUS (cid:9)
`3.7
`MD BUS (cid:9)
`3.8
`ALU Operation (cid:9)
`3.9
`Shifter Operation (cid:9)
`3.10
`IR Register (cid:9)
`3.11
`Status Register (cid:9)
`3.11.1 STC — Status Carry Bit (cid:9)
`3.11.2 STSB — Status Sign Bit (cid:9)
`3.11.3 STEZ — Status Equal to Zero Bit (cid:9)
`3.11.4 STINT — Status Interrupt Enable Bit (cid:9)
`3.12
`BCD Constant Register (cid:9)
`3.13
`Other Registers (cid:9)
`
`MICROINSTRUCTION SEQUENCE CONTROL (cid:9)
`4.1
`Overview (cid:9)
`4.2
`Dispatch Conditions (cid:9)
`4.2.1
`Unconditional Branching — JUNC (cid:9)
`Function Dispatch — IRL (cid:9)
`4.2.2
`4.2.3
`Test Sign Bit — JT7 (cid:9)
`4.2.4
`Test if Zero — JUZ (cid:9)
`4.2.5
`Test if Interrupt — INT (cid:9)
`4.2.6
`Group Dispatch — IRH (cid:9)
`4.2.7
`Test if Carry — JC (cid:9)
`4.2.8
`Test Status Register — MJMP (cid:9)
`4.3
`Reset Operation (cid:9)
`
`iii
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`PAGE
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`1
`1
`1
`2
`3
`
`5
`5
`- (cid:9) 6
`7
`7
`9
`10
`11
`
`13
`13
`13
`15
`15
`16
`16
`17
`18
`20
`21
`23
`24
`24
`24
`24
`24
`27
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`28
`28
`29
`29
`29
`30
`31
`31
`32
`33
`34
`35
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`COMPASS EXH. 1010 - Page 3 of 43
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`

`

`FIGURE
`
`PAGE
`
`LIST OF FIGURES
`
`1-1
`TMS7000 Family Address Space (cid:9)
`1-2
`TMS7000 Overall Block Diagram (cid:9)
`2-1
`Sample of a MICASM Statement (cid:9)
`Microinstruction Cycle Phases (cid:9)
`2-2
`2-3
`On-Chip RAM Memory Cycle Timing (cid:9)
`2-4
`Long Memory Cycle Timing (cid:9)
`2-5
`Interrupt Vector Reads (cid:9)
`2-6
`Interrupt Vector References (cid:9)
`3-1
`Central Processing Unit Data Paths (cid:9)
`3-2
`P BUS Sources (cid:9)
`3-3
`N BUS Sources (cid:9)
`3-4
`AL BUS Source (cid:9)
`3-5
`AH BUS Sources (cid:9)
`3-6
`LOWWRITE11-01 Description (cid:9)
`3-7
`0 BUS Destinations (cid:9)
`3-8
`MD BUS Destinations (cid:9)
`3-9
`ALU Block Diagram (cid:9)
`3-10 ALU Functions (cid:9)
`3-11 ALU Carry in Values (cid:9)
`3-12 A Microcode Example (cid:9)
`3-13 Shift/ALU Carry-in Controls (cid:9)
`3-14 Shifter Operation (cid:9)
`3-15
`IR Register Formats (cid:9)
`3-16 Status Register (cid:9)
`3-17
`ST Register Sources (cid:9)
`3-18 BCD Correction Constant Generation (cid:9)
`3-19 BCD Arithmetic Operation Timing (cid:9)
`3-20 MICASM Statement (cid:9)
`4-1
`Microinstruction Dispatch Example (cid:9)
`4-2
`Next Micro Address Generation (cid:9)
`4-3
`IRL Dispatch (cid:9)
`4-4
`JT7 Dispatch (cid:9)
`4-5
`JUZ Dispatch (cid:9)
`4-6
`INT Dispatch (cid:9)
`4-7
`TMS7000 Group Numbers (cid:9)
`4-8
`IRH Dispatch (cid:9)
`4-9
`JC Dispatch (cid:9)
`4-10 Macro Jump Conditions (cid:9)
`4-11 MJ M P Dispatch (cid:9)
`
`LIST OF TABLES
`
`TABLE (cid:9)
`2-1 (cid:9)
`2-2 (cid:9)
`
`Microinstruction Word Format (cid:9)
`Memory Control (cid:9)
`
`iv
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` 2
` 3
` 6
` 7
` 8
` 9
` 10
` 11
` 14
` 15
` 15
` 16
` 16
` 16
` 17
` 18
` 18
` 19
` 19
` 20
` 21
` 22
` 22
` 23
` 23
` 25
` 26
` 27
` 28
` 29
` 30
` 30
` 31
` 31
` 32
` 33
` 34
` 34
` 34
`
`PAGE
` 5
` 12
`
`COMPASS EXH. 1010 - Page 4 of 43
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`

`

`SECTION 1
`
`INTRODUCTION
`
`1.1 (cid:9)
`
`GENERAL INFORMATION
`
`The Texas Instruments TMS7000 Family of single-chip microcomputers is based around a microprogrammable Central
`Processing Unit (CPU), which can be interfaced to combinations of on-chip RAM, ROM, and I/O circuitry to provide a
`powerful family of single-chip microcomputers. The TMS7000 CPU implements a 64K byte logical address space and in-
`terfaces with I/O registers, timer circuit controls, and other useful on-chip functions by referencing certain addresses
`within the address space.
`
`This document contains a description of the internal architecture of the TMS7000. It describes primarily the operation of
`CPU; the memory and on-chip I/O circuitry may vary among the TMS7000 family members, and will be described in the
`documentation for those individual devices. This document is intended to present information regarding the internal
`architecture of the TMS7000 family necessary for microcoding these devices. A symbolic microinstruction assembler
`called MICASM is provided for assembling microcode instruction mnemonics. This assembler is described in the TMS7000
`Microassembler User's Guide.
`
`Other information relating to the TMS7000 Family of microcomputers is contained in the following documents:
`
`•
`
`•
`
`•
`
`•
`
`•
`
`TMS7000 8-Bit Microcomputer Data Manual (MP #008A)
`
`TMS7000 Assembly Language Programmer's Guide IMP #916)
`
`TMS7000 Microassembler User's Guide IMP #4571
`
`TMS7000 Microcode Development Guide (MP #4581
`
`TMS7000 Microprogrammer's Reference Card (MP #4591
`
`The standard instruction set executed by the TMS7000 Family is described in the TMS7000 Assembly Language Pro-
`grammer's Guide. Internally, the TMS7000 is a microprogrammed processor, whose operation is controlled by a sequence
`of microinstructions. The internal microprogram is stored in the CPU in the Control ROM, or CROM. Each microinstruction
`in the microprogram has the same format, consisting of bit fields which control the following operations:
`
`•
`
`•
`
`•
`
`•
`
`•
`
`•
`
`The gating of microregisters onto internal buses
`
`The operation of the internal Arithmetic Logic Unit (ALU)
`
`The appropriate shifting of the ALU results
`
`The gating of ALU results back into microregisters
`
`The memory controls to on-chip and off-chip memory
`
`The next microinstruction to be executed.
`
`This format is called a horizontal microinstruction format, because every component of the microarchitecture is controlled
`by a single microinstruction word. Such an organization permits a high degree of parallelism in the operation of the micro-
`arch itectu re.
`
`1.2 (cid:9)
`
`INITIAL FAMILY MEMBERS
`
`The TMS7000, TMS7020, and TMS7040 are the initial members of the TMS7000 8-bit Microcomputer Family. The
`TMS7020 provides 128 bytes of RAM, 2K bytes of ROM, and four 8-bit I/O ports. The TMS7040 provides the same 128
`bytes of RAM but contains 4K bytes of ROM. The TMS7000 is identical to the TMS7020 /7040, but it has no on-chip
`ROM. Throughout this document, TMS7000 will in general refer to any member of the TMS7000 family, unless explicitly
`stated otherwise.
`
`1
`
`COMPASS EXH. 1010 - Page 5 of 43
`
`

`

`1.3 (cid:9)
`
`TMS7000 FAMILY ADDRESS SPACE
`
`The TMS7000 family address space is divided into multiple 256-byte pages. Addresses > 0000 to > 007F are utilized as a
`128-byte Register File or RF, and reference the on-chip RAM. On-chip ROM is located at the top of the address space,
`from addresses > F800 to > FFFF for the TMS7020, and > F000 to > FFFF for the TMS7040. The last 48 bytes of
`memory, addresses > FFDO to > FFFF, are reserved for trap and interrupt vectors. The TMS7000 family address space is
`shown in Figure 1-1.
`
`The Peripheral File, or PF, is a special 256-byte page in the memory address space. Each location of the PF is a special con-
`trol or data register. On-chip circuitry interprets PF Registers as I/O control, programmable timer, memory expansion, and
`other registers to control features of the chip. For example, the four I/O ports may be accessed as four registers in the PF.
`Accesses to the Peripheral File are recognized by the Peripheral/Memory Controller (PMC) external to the CPU. In general,
`all chip functions not implemented by the CPU will be implemented by the Peripheral/Memory Controller, and controlled
`via accesses to Peripheral File Registers.
`
`The advantage of defining special pages for the Peripheral and Register files is that accesses to these areas may be made
`by specifying an offset of 8 bits, rather than a full 16-bit memory address. The Register File is located at memory addresses
`> 0000 thru > 007F and the Peripheral File is implemented in the second page of memory address space, from addresses
`>0100 to >01FF.
`
`ADDRESSES
`
`MEMORY
`
`>0000 — >007F
`
`RAM REGISTER FILE
`
`>007F — >00FF
`
`RESERVED
`
`>0100 — >01FF
`
`PERIPHERAL FILE
`
`>0200 — >EFFF
`
`•
`
`MEMORY EXPANSION
`
`>F000 — >F7FF
`
`PROGRAM ROM (TMS7040 ONLY)
`
`>F800 — >FFCF
`
`PROGRAM ROM (TMS7020/40)
`
`>FFDO —>FFFF
`
`TRAP VECTORS
`
`FIGURE 1-1 — TMS7000 FAMILY ADDRESS SPACE
`
`2
`
`COMPASS EXH. 1010 - Page 6 of 43
`
`

`

`1.4 (cid:9)
`
`BASIC TMS7000 ARCHITECTURE
`
`The major components of the TMS7000 architecture are the CPU, the Peripheral/Memory Controller, and the RAM and
`ROM. These components and their interconnections are shown in Figure 1-2.
`
`The Central Processing Unit (CPU) contains the internal registers, which store the operands of an instruction, and the
`Arithmetic Logic Unit (ALU), which operates on the internal register values. A shifter is provided to rotate the output of the
`ALU before its results are either stored in an internal CPU register or written to a memory location. The CPU is described in
`further detail in Section 3.
`
`The Peripheral/Memory Controller (PMC) is a collection of modules which interface the CPU with the I/O ports, memory,
`and the interrupt inputs. The CPU is connected to the PMC via the Address Low (AL), Address High (AH), Memory Data
`(MD) and Control (C) Buses. The MD Bus, AL Bus, and AH Bus are also connected to the on-chip RAM and ROM
`memories.
`
`CENTRAL
`PROCESSING
`UNIT
`
`/8 /8 /8 /7
`
`MD AH AL C
`
`PERIPHERAL
`/MEMORY
`CONTROLLER
`
`RAM
`128 x 8
`
`ROM
`TYPICALLY
`2K/4K x 8
`
`EXTERNAL INTERFACE
`
`r arisaimwaSaSsEs
`
`eammarnoSMENearreliMEN
`
`(cid:9)4 PORT A
`
`8
`
`PORT B
`
`(cid:9) MI PORT C
`
`8
`
`VII.— PORT D
`
`(cid:9)4 RESET
`(cid:9)4 INT1, INT3
`
`4 MEMORY CONTROL (MC)
`
`CRYSTAL
`
`VCC, VSS
`
`40 PINS TOTAL
`
`FIGURE 1-2 — TMS7000 OVERALL BLOCK DIAGRAM
`
`3
`
`COMPASS EXH. 1010 - Page 7 of 43
`
`(cid:9)
`

`

`The Peripheral/Memory Controller (PMC) performs many functions. It interfaces the CPU to the outside world by pro-
`viding control and data registers for I/O ports, interrupts, and internal timer controls. The interface control registers appear
`to the CPU as addresses in the Peripheral File. In the TMS7000, the PF is implemented in the second 256 byte page of
`memory, at addresses >0100 to >01FF. Input/output in the TMS7000 is accomplished by reading and writing bytes in
`the Peripheral File implemented by the PMC. In terms of the microarchitecture, the exact functions of the Peripheral File
`registers are family member dependent.
`
`The Control (C) Bus connecting the PMC and the CPU carries control information required in the interface between these
`two subsections of the TMS7000. The C Bus is made up of seven signals, each of which is described briefly below.
`
`•
`
`•
`
`•
`
`•
`
`•
`
`•
`
`•
`
`#MEM (Memory) — set by the CPU during any memory access.
`
`#MEMCNT (Memory Continue) — set by the CPU during the first cycle of two cycle memory accesses.
`
`#WR (Write) — set to 1 by the CPU to indicate a memory write operation.
`
`STINT (Status Interrupt Enable) — set by the CPU to allow the PMC to assert IACT.
`
`IACT (Interrupt Active) — set by the PMC if a valid interrupt is active and STINT is a 1.
`
`RST (Reset) — set to 1 by the PMC whenever the external RESET pin is a 0.
`
`OTMD (0 Bus to MD Bus Enable) — set by the PMC to enable the 0 Bus to drive the MD Bus.
`
`Each of these signals is discussed in greater depth in later sections of this manual. Further details of interrupt control may
`be found in the TMS7000 8-Bit Microcomputer Data Manual (Part Number MP 008A1.
`
`4
`
`COMPASS EXH. 1010 - Page 8 of 43
`
`

`

`SECTION 2
`
`MICROINSTRUCTION EXECUTION
`
`2.1 (cid:9)
`
`MICROINSTRUCTION FORMAT
`
`This section describes the format of the TMS7000 microinstructions, and details the internal timing of microinstruction
`execution.
`
`The CROM is organized as a 64-bit wide, 160-word memory. The current microarchitecture of the TMS7000 uses 45 bits
`per microinstruction to control its operation. To allow for future expansion of this architecture, however, a total of 64
`microinstruction bits are reserved in the architecture definition. Table 2-1 describes the format of the TMS7000
`microinstruction word.
`
`TABLE 2-1 — MICROINSTRUCTION WORD FORMAT
`
`FIELD
`
`FUNCTION
`
`SECTION
`
`#JMPADDR(7-0)
`#JMPCNTL(2-0)
`#0> PCH
`#MD> T
`#-MD> IR
`
`#LOWWRITE(1-0)
`#-O> ST
`#MD> P
`#PCH> P
`#PCL> P
`
`BASE ADDRESS FOR NEXT INSTRUCTION
`JUMP FUNCTION SELECTION
`GATES 0 BUS TO PCH REGISTER
`GATES MD BUS TO T REGISTER
`GATES MD BUS TO IR REGISTER
`
`SELECTS ONE OF 3 0 BUS DESTINATIONS
`GATES 0 BUS TO ST REGISTER
`GATES MD BUS TOP BUS
`GATES PCH REGISTER TO P BUS
`GATES PCL REGISTER TO P BUS
`
`BITS
`
`63-56
`55-53
`52
`51
`50
`
`49-48
`47
`46
`45
`44
`
`43
`42
`41
`40
`39
`
`38
`37
`36
`35
`34
`
`33
`32
`31
`30
`29
`
`4.1
`4
`3.6
`3.6
`3.7
`
`3.6
`3.6
`3.2
`3.2
`3.2
`
`3.3
`3.3
`3.3
`3.3
`3.3
`
`3.4
`3.4
`3.4
`3.4
`3.5
`
`3.5
`3.5
`2.4
`2.4
`2.4
`
`3.11
`3.9
`3.8
`3.8
`
`#MD> N
`#T> N
`#ST> N
`#BCD> N
`#IR> N
`
`#ONE> AL
`#PAL
`#MAL> AL
`#SP> AL
`#T> AH
`
`#PCH> AH
`#ONE> AH
`#MEMCNT
`#MEM
`#WR
`
`GATES MD BUS TON BUS
`GATES T REGISTER TO N BUS
`GATES ST REGISTER TO N BUS
`GATES BCD CONSTANT TON BUS
`GATES IR REGISTER TO N BUS
`
`GATES CONSTANT ONE TO AL BUS
`GATES P BUS TO AL BUS
`GATES MAL REGISTER TO AL BUS
`GATES SP REGISTER TO AL BUS
`GATES T REGISTER TO AH BUS
`
`GATES PCH REGISTER TO AH BUS
`GATES CONSTANT ONE TO AH BUS
`FIRST ONE OF TWO CYCLE MEM. ACCESS
`INDICATES A MEMORY ACCESS
`INDICATES A MEMORY WRITE
`
`UPDATES STATUS REGISTER BITS
`SELECTS SHIFT/ALU CARRY FUNCTIONS
`SELECTS ALU FUNCTION
`LOGICAL (VS. ARITHMETIC) ALU OP'S
`
`5
`
`28
`27-24
`23-20
`19
`18-0
`
`#-LST
`#SHIFTCNTL(3-0)
`#ALUCNTL(3-0)
`#ABL
`Reserved
`
`NOTE: In multiple bit fields bit 0 is the LSB.
`
`COMPASS EXH. 1010 - Page 9 of 43
`
`

`

`All 160 words of the CROM are required to implement the standard instruction set of the TMS7000. Because of this,
`adding other microcoded functions to the TMS7000 requires that some of the standard instructions be deleted to allow
`space for the new instructions.
`
`The TMS7000 Standard Instruction Set has been divided into two instruction groups designated core and non-core
`instructions. Non-core instructions are those instructions which Texas Instruments will allow to be removed in order to
`implement other microcoded functions. Core instructions may not be removed and are provided with any TMS7000
`whether further microcoding has been implemented or not. Core and Non-core instructions are described in the TMS7000
`Microcode Development Guide, (Part Number MP 458).
`
`A symbolic microprogram assembler, MICASM, is available to aid microprogram generation. MICASM accepts mnemonic
`names for bit fields in a microinstruction word, and builds the appropriate bit pattern. The names of each bit field in the
`TMS7000 microinstruction word are given in Figure 2-1. They are distinguished from other signal names by preceeding
`them with a T.
`
`For single bit fields, if the MICASM statement contains the name of the bit, it is asserted in the assembled instruction. For
`high-true signals, the bit is set to 1; for low-true signals (such as #-O> ST), the bit is set to 0. For multiple-bit fields,
`MICASM accepts any one of a set of possible names, where each name corresponds to a bit pattern for the multi-bit field.
`A sample of a MICASM statement is shown in Figure 2-1.
`
`.ORG ADDO (cid:9)
`Z> AH, (cid:9)
`MAL> AL, (cid:9)
`MD> P, (cid:9)
`T> N, (cid:9)
`PADDN, ZCI, LST, (cid:9)
`MW, (cid:9)
`JUNC(NEXT); (cid:9)
`
`'ADD Dual Operand Function
`'AH =0 for Page 0 access
`'AL= destination register #
`'Source operand to P bus
`'Destination operand to N bus
`'Add them, load status register
`'Write the result to destination
`'Jump to next microinstruction
`
`FIGURE 2-1 — SAMPLE OF A MICASM STATEMENT
`
`The .ORG line establishes the address of the microinstruction in the Control ROM. The remaining lines contain symbols
`which set bits in the current microinstruction word. The last line indicates the next microinstruction that is to be executed.
`
`2.2 (cid:9)
`
`MICROINSTRUCTION CYCLE TIMING
`
`Each microinstruction cycle has four overlapping clock phases; H1, H2, H3, and H4. H1 and H3 are non-overlapping, and
`H2 and H4 are non-overlapping. Microinstruction cycles begin on the rising edge of H1. Two versions of clock generator
`circuitry are available for the TMS7000. The first version uses the external crystal frequency directly to generate H1-H4.
`The second version divides the crystal frequency by two before generating the internal clock phases. Figure 2-2 shows the
`timing relationships of the four internal clock phases H1-H4 and the signal from the crystal oscillator.
`
`H1 -H4, the four internal clock phases, are used as data transfer signals throughout the architecture. In particular, the cur-
`rent microinstruction is gated out of the Control ROM during H1. Microinstruction bits required during later phases (H2,
`H3, H4) are appropriately sampled by the hardware.
`
`The internal implementation of the TMS7000 uses MOS dynamic ratioless logic which allows the chip to operate with
`lower power requirements than with other types of MOS logic. Signal lines considered to be valid during phase HX (e.g.
`H1) are precharged during the non-overlapping phase of HX (e.g. H3). For this reason, timing diagrams in this document
`will indicate signal values only during the phase in which they are valid, with a don't care indication during the phase in
`which they are precharged.
`
`6
`
`COMPASS EXH. 1010 - Page 10 of 43
`
`

`

`XTAL*
`
`H1
`
`H2
`
`1-13
`
`H4
`
`CYCLE i
`
`CYCLEi+I
`
`*NOTE: This waveform represents the crystal oscillator output divided
`by two if that version of the clock generator circuitry is used.
`
`FIGURE 2-2 — MICROINSTRUCTION CYCLE PHASES
`
`2.3 (cid:9)
`
`MEMORY CYCLE TIMING
`
`Memory references to the on-chip Register File (RF) require one microinstruction cycle, and are called short memory
`cycles. All other references, i.e. to on-chip ROM, extended memory, or the Peripheral File, require two microinstruction
`cycles, and are called long memory cycles. Extended memory must be able to respond in this time period, since no wait
`states are provided in the TMS7000.
`
`2.3.1 (cid:9)
`
`Short Memory References.
`
`The timing for a read or write to the on-chip Register File is shown in Figure 2-3.
`
`For a Register File read during cycle i, the microinstruction loaded at the initiation of cycle i asserts #MEM high and
`#MEMCNT low. #MEM is asserted at all times when a memory reference is active, and #MEMCNT is asserted high only
`during the first cycle of two-cycle lie. long) memory cycles. #WR is set low for read operations and high for write opera-
`tions. Microinstruction i also specifies the contents of the the address bus, placing a > 00 on the AH (Address High) Bus
`and the register number on the AL (Address Low) Bus. During H2, the MD Bus is precharged and the RAM is accessed.
`For the duration of H4, the RAM output data on write operations and the RAM input data on read operations is on the MD
`Bus.
`
`Because H4 of cycle i overlaps H1 of cycle i +1, the data read on cycle i may be loaded into registers T or IR at the end of
`cycle i or gated onto the P or N Buses at the beginning of cycle i +1. This characteristic of the MD Bus can be very useful in
`optimizing microcode performance.
`
`Initial members of the TMS7000 Family implement only 128 bytes of the 256-byte Register File; attempts to write to
`addresses in non-existent on-chip memory will be ignored. Attempts to read non-existent memory will produce > 00.
`
`7
`
`COMPASS EXH. 1010 - Page 11 of 43
`
`(cid:9)
`

`

`ON-CHIP RAM MEMORY CYCLE TIMING
`
`+ 1
`
`1+2
`
`Hi
`
`H2
`
`H3
`
`H4
`
`ALL SHORT REFS:
`
`#MEM
`
`#MEMCNT
`
`AL BUS
`
`AH BUS
`
`READS:
`
`#WR
`
`••••
`41-14-REGISTER NUMBER (0 255)
`
`is--ADDRESS HIGH = >00
`
`MD BUS
`
`••••
`
`XV(
`
`trul READ DATA AVAILABLE
`
`WRITES:
`
`#WR
`
`MD BUS
`
`•••••
`
`(cid:9) WRITE DATA SPECIFIED
`
`FIGURE 2-3 - ON-CHIP RAM MEMORY CYCLE TIMING
`
`8
`
`COMPASS EXH. 1010 - Page 12 of 43
`
`

`

`2.3.2 Long Memory References.
`
`The timing for all long memory references is shown in Figure 2-4.
`
`i +1 (cid:9)
`
`1+2
`
`H2
`
`H3
`
`H4
`
`ALL LONG MEM REFS:
`
`#MEM
`
`#MEMCNT
`
`AL 3US
`
`AH BUS
`
`READ:
`
`#WR
`
`#MD BUS
`
`WRITE:
`#WR
`
`#MD BUS
`
`READ DATA AVAILABLE
`AT END OF CYCLE 1+1
`
`
`OFF CHIP ONLY (cid:9)
`ON CHIP ONLY
`WRITE DATA ASSERTED
`
`FIGURE 2-4 - LONG MEMORY CYCLE TIMING
`
`COMPASS EXH. 1010 - Page 13 of 43
`
`

`

`The memory control signals #MEMCNT, #MEM, and #WR are specified in the microinstruction directly. Figure 2-4 shows
`these signals valid during a full microinstruction cycle because, once specified for a cycle, their state will not change during
`that cycle.
`
`For all long memory references, #MEM must be asserted high for two consecutive cycles. #MEMCNT should be 1 for the
`first cycle, and 0 for the second cycle. #MEMCNT is asserted by specifying the MCNT symbol in the MICASM statements
`for the microinstruction. Various combinations of the #MEM and #WR microinstruction bits are specified by other
`MICASM symbols, as explained in paragraph 2.4. The 16-bit address to be accessed must be gated onto the AH and AL
`Buses during the first cycle. The Peripheral/Memory Controller latches the memory address, so the address need not be
`asserted during the second cycle. It should be noted that this feature can be used to great advantage in microcode
`sequences since this allows the AH and AL Buses to be used for other functions during the second microinstruction cycle.
`In this manner, microcode functions may be overlapped which can result in shorter, faster executing microcode.
`
`For read cycles, #WR is set to 0 for both cycles. The result of a read appears on the MD Bus in phase H4 of the second
`cycle. It may either be loaded into the T or IR Registers at the end of the second cycle or loaded into the P or N Bus at the
`beginning of the third cycle.
`
`For write cycles, #WR is set to 1 for both cycles. When the writes destination is an on-chip address, the write data must be
`valid during H4 of the second microinstruction cycle; when the writes destination is an off-chip address, the write data is
`required to be valid during H4 of the first microinstruction cycle. The data used in an off-chip write is latched by the PMC
`during the first cycle, and therefore need not be valid during the second cycle, and conversely the data in an on-chip write
`need not be valid during the first cycle. This can be used advantageously in certain microcoding situations. If desired,
`however, data may be asserted during both cycles.
`
`2.3.3 (cid:9)
`
`Interrupt Vector Reads.
`
`When an interrupt is received by the Peripheral/Memory Controller, the PMC asserts IACT on the Control Bus to the CPU,
`provided that STINT is a 1. The state of IACT may be tested by the CPU using an INT dispatch (see paragraph 4.2.51. If an
`interrupt is active, the CPU may then read an interrupt vector supplied by the PMC on the MD Bus, indicating which inter-
`rupt has occurred. The interrupt vector read requires two cycles, as shown in the timing diagram in Figure 2-5.
`
`CYCLE
`i +1 (cid:9)
`
`1+2
`
`Hi
`
`H4
`
`#MEMCNT
`
`#MEM
`
`#WR
`
`AL,AH BUS
`
`MD BUS
`
`VECTOR SUPPLIED
`
`FIGURE 2-5 — INTERRUPT VECTOR READS
`
`10
`
`COMPASS EXH. 1010 - Page 14 of 43
`
`

`

`Notice that #MEM and #WR must be low for both cycles of the interrupt vector read. As with a long memory read, the vec-
`tor is not available until the end of the second microinstruction cycle. An interrupt vector read may be coded in MICASM
`using the statements described in Table 2-2.
`
`The value of the vector supplied by the PMC for each interrupt is shown in Figure 2-6. There is a distinction between the in-
`terrupt vector supplied by the PMC and the trap vector address at which the interrupt subroutine entry point address is
`stored.
`
`Interrupt (cid:9)
`Level (cid:9)
`
`0 (Reset) (cid:9)
`1 (cid:9)
`2 (cid:9)
`3 (cid:9)
`
`Vector (cid:9)
`Supplied (cid:9)
`
`'› FE (cid:9)
`> FD (cid:9)
`> FC (cid:9)
`
`Trap Vector
`Address
`
`> FFFE
`> FFFC
`> FFFA
`> FFF8
`
`FIGURE 2-6 — INTERRUPT VECTOR REFERENCES
`
`The vector supplied by the PMC is the same as the TRAPn opcode for the TMS7000 Standard Instruction Set. In order to
`call the interrupt handler, the microcode generates the trap vector address from the vector supplied, and reads memory at
`that location to get the address of the interrupt handler subroutine. It should be noted that the interrupt trap vector
`addresses shown in Figure 2-6 are those implemented in the currently supplied TMS7000 Standard Instruction Set
`Microcode. Different trap vector addresses may be implemented if additional microcode is written to handle modified
`interrupt servicing.
`
`2.4 (cid:9)
`
`MEMORY CONTROL SIGNALS
`
`The three memory control signals output by the CPU and interpreted by the Peripheral/Memory Controller are:
`
`O (cid:9)
`
`•
`
`•
`
`#MEMCNT (Memory Continue) — asserted on the first cycle of a two-cycle long memory reference.
`
`#MEM (Memory) — asserted if the microinstruction references memory of any kind (RAM, ROM, extended,
`peripheral).
`
`#WR (Write) — 1 if a write is being performed, 0 if a read.
`
`The interpretation of various combinations of these signals is described in Table 2-2.
`
`The MICASM symbol or symbols listed in Table 2-2 must be used to specify the appropriate combination of memory con-
`trol signals. The #MEMCNT Microinstruction Bit is set independently by the MICASM symbol MCNT. The various com-
`binations of #MEM and #WR Microinstruction Bits are set by specifying the MICASM symbols 0> MD, MR, and MW.
`0> MD may be specified when no memory access is desired, but the ALU Output (0) Bus contents are to be gated onto
`the Memory Data (MD) Bus. OTMD, the signal which enables the 0 Bus to drive the MD Bus, is generated by the PMC and
`is defined as OTMD #WR .OR. #MEMCNT. The 0> MD MICASM statement has been defined only to assert OTMD dur-
`ing non-memory cycles by generating a unique combination of #WR and #MEMCNT which does not occur during actual
`memory cycles. (0> MD should not be coded during memory accesses). Note, however that the combination of memory
`controls produced by 0> MD is also the default and will be produced by MICASM if no memory controls are coded in a
`particular microinstruction cycle.
`
`MR is specified for a memory read operation, and MW for a memory write. For long memory cycles, which require two
`microinstructions, MCNT is specified in the first microinstruction only. MR or MW must be specified in both microinstruc-
`tions.
`
`11
`
`COMPASS EXH. 1010 - Page 15 of 43
`
`

`

`TABLE 2-2 — MEMORY CONTROLS
`
`#MEMCNT
`(previous)
`
`#MEMCNT
`(current)
`
`#MEM
`
`#WR
`
`Function
`
`OTMD
`
`0
`0
`0
`0
`1
`1
`1
`1
`0
`0
`0
`0
`1
`
`0
`0
`0
`0
`0
`0
`0
`0
`1
`1
`1
`1
`1
`
`0
`0
`1
`1
`0
`0
`1
`1
`0
`0
`1
`1
`x
`
`0
`1
`0
`1
`0
`1
`0
`1
`0
`1
`0
`1
`x
`
`- No Mem Reference -
`Gate 0 Bus to MD Bus
`Short Memory Read
`Short Memory Write
`2nd State Int. Vector
`* Illegal *
`2nd State Long Read
`2nd State Long Write
`1st State Int. Vector
`* Illegal *
`1st State Long Read
`1st State Long Write
`* Illegal *
`
`0
`1
`0
`1
`0
`1
`0
`1
`1
`1
`1
`1
`1
`
`MICASM
`Symbol
`
`-See Note 1-
`0> MD-See Note 2
`MR
`MW
`INTVEC
`
`MR
`MW
`MONT, INTVEC
`
`MCNT, MR
`MCNT, MW
`
`NOTES: 1. MICASM is not capable of generating this combination of memory controls directly.
`
`2. This combination of memory control signals is also the default combination, produced by MICASM when no memory control is specified.
`
`12
`
`COMPASS EXH. 1010 - Page 16 of 43
`
`

`

`SECTION 3
`
`TMS7000 CPU INTERNAL ORGANIZATION
`
`3.1 (cid:9)
`
`ORGANIZATION OF THE TIVIS7000 CPU
`
`Section 3 describes the internal organization of the TMS7000 CPU. A block diagram is shown in Figure 3-1. Each of the
`internal registers and buses are 8 bits wide. The internal CPU Buses are used to transfer information between registers and
`to devices external to the CPU. Normally a bus will be used to transfer data between two particular locations during a
`microinstruction cycle. (Buses are precharged at various times during each microinstruction and therefore cannot be used
`to store data). These types of transfers of information are explained in the following descriptions of the various buses and
`registers within the CPU. In most cases, a bus will usually have only one source or destination; however, it may be
`desirable to have either multiple sources or destinations for a bus.
`
`The case of multiple destinations of a bus is a simple extension of a single bus destination; a bus's contents are merely
`gated to several places simultaneously. This can be accomplished by simply including the MICASM statements for each
`destination, ie., MD> N and MD> P both coded in the same microinstruction cycle.
`
`Multiple sources for a bus is more complex. Logically this may be coded in MICASM in a straightforward manner, just as
`multiple bus destinations are, however the result is quite different. The contents of a bus when multiple sources are
`specified is the logical OR of the two sources. This may be used advantageously in saving microcode in some situations
`with a single restriction: the TMS7000 Emulator cannot be used to debug the microcode. It should be emphasized that this
`technique should be used only when absolutely necessary and the Emulator may not be used to check the microcode,
`which can make a design very difficult to debug.
`
`3.2 (cid:9)
`
`P BUS
`
`The P Bus is one of the inputs to the Arithmetic Logic Unit, or ALU. It is called P for positive because it always contains the
`positive or left-hand operand; in subtract operations, the ALU always computes P-N and in add operations, P+ N is com-
`puted. The P Bus is loaded from the MD Bus, the AL Bus, the PCH Register, the PCL Register or with the constant > 00 or
`> 01. Any of the AL Bus sources may be placed on the P Bus by gating them onto the AL Bus and asserting the #PAL
`microinstruction bit, connecting the P Bus to the AL Bus. A P Bus source must be coded in each microinstruction cycle.
`All of the possible P Bus sources are shown in Figure 3-2.
`
`The hex representation in Figure 3-2 indicates the bits in a microinstruction that are affected when the MICASM symbol
`shown is specified for the P Bus source. Note that if a microinstruction requires no source on the P Bus, the MICASM
`symbol DC> P must be specified to indicate a don't care condition on the bus.
`
`The P Bus is loaded at the beginning of a microinstruction cycle, on phase H1.
`
`13
`
`COMPASS EXH. 1010 - Page 17 of 43
`
`

`

`0(7-0)
`
`- OTMD (TRANSFER GATE
`J.,rea FROM MEM. CONTROL)
`
`=LSI
`11-13)
`
`FOTST(H3) (cid:9)
`
`YACH3
`
`FIADTTIH4) (cid:9)
`
`#MDTIR (H3)
`
`4
`
` EZ
`TO ENTRY POINT
`
`07
`
`FEZ
`SOUT.
`GOUT
`
`STINT TO
`—DINT. LOG.
`---11.STSB TO I
`--8.-STC ENTRY
`--18.STE POINT
`STATUS 2 ET
`C1
`
`STOP
`
`BCD
`
`T REG
`
`IR
`
`IR(7-0)
`
`IR (7,2,1,0)
`TO ENTRY
`POINT
`
`NO
`LATCH
`
`(cid:9)p
`
`r. STC
`
`STOP
`
`.... T(7) TO
`ENTRY T.
`
`I-FTTN(H1)
`
`IRTN(H1)
`
`MDTN(H1)] I-FMDTP(H1)
`
`H
`
`T
`
`A(7-0)
`
`ALU
`
`ESTTN(H1)
`
`8 (cid:9)
`
`N(7-0)
`
`8
`
`8 (cid:9)
`/4
` #ACH(3-0)
`02---#ABL
`
`P(7-0)
`
`A1-117-0)
`
`R CH
`H3
`
`PRECH
`H3
`
`TTAH(H1)
`
`8
`
`PRECH
`H3
`
`AH(7 0)
`
`AL(7-0)
`
`N(7-0)
`
`P17-0)
`
`8
`
`MD (7-0)
`
`FMEM,FMEMCNT,FVVR
`
`(AB