Filed on behalf of: PNC Bank, N.A.
`
`
`
`JPMorgan Chase & Co.
`
`
`
`JP Morgan Chase Bank, N.A.
`
`By: Lionel M. Lavenue
`Timothy J. May
`FINNEGAN, HENDERSON, FARABOW,
` GARRETT & DUNNER, LLP
`901 New York Avenue, NW
`Washington, DC 20001-4413
`Telephone: 202-408-4000
`Facsimile: 202-408-4400
`E-mail: lionel.lavenue@finnegan.com
`
`timothy.may@finnegan.com
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`PNC Bank, N.A., JP Morgan Chase & Co., and JP Morgan Chase Bank, N.A.,
`Petitioner
`
`v.
`
`Maxim Integrated Products, Inc.,
`Patent Owner
`
`
`Patent No. 6,105,013
`
`
`
`DECLARATION OF HENRY N. DREIFUS
`
`Page 1 of 95
`
`PNC-JP MORGAN EXHIBIT 1008
`
`

`
`TABLE OF CONTENTS
`
`I. 
`
`Introduction ...................................................................................................... 1 
`
`II. 
`
`Qualifications ................................................................................................... 2 
`
`III.  Materials Reviewed ......................................................................................... 4 
`
`IV.  Overview of the ’013 Patent ............................................................................ 5 
`
`V. 
`
`Person of Ordinary Skill in the Art .................................................................. 8 
`
`VI.  Claim Construction .......................................................................................... 9 
`
`VII.  Certain References Disclose and/or Render Obvious All Elements of
`Claims 1-6, 8-12, 14, and 15 of the ’013 Patent .............................................. 9 
`
`A.  Hawkes Discloses All Elements of Claims 1-3, 6, 8, 9, 11, 12,
`14, and 15 of the ’013 Patent ............................................................... 10 
`
`1.  Microcontroller Core ................................................................ 12 
`
`2.  Math Coprocessor // Modular Exponentiation Accelerator
`Circuit ........................................................................................ 12 
`
`3.  Memory Circuitry // Memory Circuit ....................................... 13 
`
`4. 
`
`5. 
`
`6. 
`
`Input/Output Circuit .................................................................. 14 
`
`Real Time Clock // Clock Circuit ............................................. 15 
`
`Energy Circuit ........................................................................... 15 
`
`Hawkes Renders Claims 1-3, 6, 8, 9, 11, 12, 14, and 15 of
`the ’013 Patent Obvious ...................................................................... 16 
`
`Hawkes in Combination With Cooper Renders Claims 4 and 10
`of the ’013 Patent Obvious .................................................................. 16 
`
`B. 
`
`C. 
`
`D.  Hawkes in Combination With Hardware Hacker Renders Claim
`5 of the ’013 Patent Obvious ............................................................... 18 
`
`
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`i
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`

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`E. 
`
`Chorley Discloses All Elements of Claims 1-3, 6, 9, 11, 12, 14,
`and 15 of the ’013 Patent ..................................................................... 19 
`
`F. 
`
`G. 
`
`H. 
`
`I. 
`
`1.  Microcontroller Core ................................................................ 20 
`
`2.  Math Coprocessor // Modular Exponentiation Accelerator
`Circuit ........................................................................................ 21 
`
`3.  Memory Circuitry // Memory Circuit ....................................... 22 
`
`4. 
`
`5. 
`
`6. 
`
`Input/Output Circuit .................................................................. 23 
`
`Real Time Clock // Clock Circuit ............................................. 23 
`
`Energy Circuit ........................................................................... 25 
`
`Chorley in Combination With Hawkes Renders Claims 1-3, 6, 8,
`9, 11, 12, 14, and 15 of the ’013 Patent Obvious ................................ 25 
`
`Chorley in Combination With Cooper or in combination with
`Hawkes and Cooper Renders Claims 4 and 10 of the ’013
`Patent Obvious .................................................................................... 27 
`
`Chorley in Combination With Hardware Hacker or in
`combination with Hawkes and Hardware Hacker Renders
`Claim 5 of the ’013 Patent Obvious .................................................... 28 
`
`Blandford Discloses All Elements of Claims 1-4, 6, 9, 10, 12,
`and 15 of the ’013 Patent ..................................................................... 29 
`
`1.  Microcontroller Core ................................................................ 31 
`
`2.  Math Coprocessor // Modular Exponentiation Accelerator
`Circuit ........................................................................................ 32 
`
`3.  Memory Circuitry // Memory Circuit ....................................... 32 
`
`4. 
`
`5. 
`
`6. 
`
`Input/Output Circuit .................................................................. 33 
`
`Real Time Clock // Clock Circuit ............................................. 33 
`
`Energy Circuit ........................................................................... 34 
`
`
`
`ii
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`Page 3 of 95
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`

`
`J. 
`
`Blandford in Combination With Hardware Hacker Renders
`Claim 5 of the ’013 Patent Obvious .................................................... 35 
`
`VIII.  Conclusion ..................................................................................................... 36 
`
`
`
`iii
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`Page 4 of 95
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`
`
`I.
`
`I, Henry N. Dreifus, declare as follows:
`
`Introduction
`
`1.
`
`I have been retained by PNC Bank, N.A., JP Morgan Chase & Co.,
`
`and JP Morgan Chase Bank, N.A. (collectively, “Petitioner”) as an independent
`
`expert consultant in this proceeding before the United States Patent and Trademark
`
`Office. Although I am being compensated at my rate of $350.00 per hour for the
`
`time I spend on this matter, no part of my compensation depends on the outcome
`
`of this proceeding, and I have no other interest in this proceeding.
`
`2.
`
`I understand that this proceeding involves U.S. Patent No. 6,105,013
`
`(“the ’013 patent”) (attached as Ex. 1001 to the petition). The application for
`
`the ’013 patent was filed on March 10, 1998, as U.S. Patent Application
`
`No. 09/041,190, which is based on U.S. Provisional Patent Application No.
`
`60/004,510, filed September 29, 1995, and the patent issued on August 15, 2000.
`
`3.
`
`I have been asked to consider whether certain references disclose or
`
`render obvious the claims of the ’013 patent.
`
`4.
`
`I have been advised that a patent claim may be invalid as obvious if
`
`the differences between the subject matter patented and the prior art are such that
`
`the subject matter as a whole would have been obvious at the time the invention
`
`was made to a person having ordinary skill in the art. I have also been advised that
`
`several factual inquiries underlie a determination of obviousness. These inquiries
`
`
`
`1
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`Page 5 of 95
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`

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`include the scope and content of the prior art, the level of ordinary skill in the field
`
`of the invention, the differences between the claimed invention and the prior art,
`
`and any objective evidence of non-obviousness.
`
`5.
`
`I have been advised that objective evidence of non-obviousness,
`
`known as “secondary considerations of non-obviousness,” may include
`
`commercial success, satisfaction of a long-felt but unsolved need, failure of others,
`
`copying, skepticism or disbelief before the invention, and unexpected results. I am
`
`not aware of any such objective evidence of non-obviousness of the subject matter
`
`claimed in the ’013 patent at this time.
`
`6.
`
`In addition, I have been advised that the law requires a “common
`
`sense” approach of examining whether the claimed invention is obvious to a
`
`person skilled in the art. For example, I have been advised that combining familiar
`
`elements according to known methods is likely to be obvious when it does no more
`
`than yield predictable results.
`
`7. My opinions are set forth below.
`
`II. Qualifications
`
`8.
`
`I am the Founder and Managing Director of Dreifus Associates,
`
`Limited (DAL), an Identity technology and Personnel Assurance solutions
`
`development and integration organization established in 1991. My
`
`accomplishments include holding a key patent on advanced smart cards and
`
`
`
`2
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`Page 6 of 95
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`

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`portable electronic transaction technology. I have more than 25 years of experience
`
`in the advanced card solutions field including extensive project work on strategic
`
`engagements developing systems applying multiple types of card technologies
`
`ranging from magnetic, optical and intelligent (smart card) for financial, security,
`
`consumer marketing and information applications. I have served as a recognized
`
`worldwide advisor in the card technology industry and provide vision for the
`
`application of enabling technologies to solve business problems. I was also a
`
`founding director of the Smart Card Industry Association and served as a delegate
`
`to the International Standards Organization (ISO) and the American National
`
`Standards Institute (ANSI) developing worldwide standards for the smart
`
`(integrated circuit) cards.
`
`9. My project assignments in smart card based solutions include
`
`providing consulting and advisory work to various elements of the financial
`
`transaction and identification solutions supply chain ranging from the card
`
`manufacturers and system component manufacturers to system operators. This has
`
`included work for American Express, MasterCard International, Rand McNally
`
`Corporation, Visa, Arthur Blank & Company, United States Department of
`
`Defense, AT&T and others.
`
`10. My current project assignments include supporting the development
`
`of a needs assessment and detailed design for an international interoperable
`
`
`
`3
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`Page 7 of 95
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`

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`citizen’s identification capability to allow for multiple countries participating in an
`
`economic union to identify and provide services to citizens across the countries to
`
`include border crossing, social security, healthcare, driving, voting and other
`
`services.
`
`11. My curriculum vitae, which includes a more detailed summary of my
`
`background and experience, is attached as Appendix A.
`
`III. Materials Reviewed
`
`12.
`
`In forming my opinions, I have reviewed the ’013 Patent, the
`
`prosecution history of the ’013 patent, and the following documents:
`
` In re Maxim Integrated Prods., Inc., Case No. 2:12-mc-00244, MDL
`
`No. 2354 (W.D. Pa.), Docket No. 691, Special Master’s Report and
`
`Recommendation Re: Claim Construction (Oct. 9, 2013) (attached as
`
`Ex. 1009 to Petitioner’s filing);
`
` In re Maxim Integrated Prods., Inc., Case No. 2:12-mc-00244, MDL
`
`No. 2354 (W.D. Pa.), Docket No. 693, Correction to Special Master’s
`
`Report and Recommendation Re: Claim Construction (Oct. 15, 2013)
`
`(attached as Ex. 1010 to Petitioner’s filing);
`
` P. L. Hawkes, D. W. Davies, and W. L. Price, Integrated Circuit Cards,
`
`Tags and Tokens, New Technology and Applications (1990)
`
`(“Hawkes,” attached as Ex. 1011 to Petitioner’s filing);
`
`
`
`4
`
`Page 8 of 95
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`

`
` International Publication No. WO 93/11540 by Cooper et al. (“Cooper,”
`
`attached as Ex. 1012 to Petitioner’s filing);
`
` Don Lancaster, Hardware Hacker, July, 1993 (“Hardware Hacker,”
`
`attached as Ex. 1013 to Petitioner’s filing);
`
` B. J. Chorley and W. L. Price, An Intelligent Token for Secure
`
`Transactions, Security and Protection in Information Systems:
`
`Proceedings of the Fourth IFIP TC 11 International Conference on
`
`Computer Security, IFIP/Sec ‘86 (1989) (“Chorley,” attached as Ex.
`
`1014 to Petitioner’s filing);
`
` International Publication No. WO 92/12485 by Robert Blandford
`
`(“Blandford,” attached as Ex. 1015 to Petitioner’s filing); and
`
` U.S. Patent No. 4,575,621 (attached as Ex. 1007 to Petitioner’s filing).
`
`IV. Overview of the ’013 Patent
`
`13. The ’013 patent purportedly relates to a “module” used for “monetary”
`
`or “digital cash” transactions. Ex. 1001 at 1:24-29, 1:48-67, and 7:62-12:34. As
`
`noted by the patent, conventional electronic hardware already existed for this
`
`purpose. Ex. 1001 at 1:43-45. In fact, I developed and filed a patent application for
`
`such hardware more than a decade before submission of the provisional application
`
`that lead to the ’013 patent. My application issued as U.S. Patent No. 4,575,621
`
`(Ex. 1007).
`
`
`
`5
`
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`

`
`14. Figure 1 of ’013 patent, reproduced below, is a block-diagram of
`
`the ’013 patent’s module (module 10).
`
`
`
`15. As illustrated in Figure 1, module 10 includes one or more integrated
`
`circuits and has a microprocessor 12, a math coprocessor (or modular
`
`exponentiation accelerator) 18, memory circuitry 20 (including ROM 22 and
`
`NVRAM 24), input/output circuitry 26, a real time clock 14, and an energy circuit
`
`34. Ex. 1001 at 2:34-42, 3:5-9, and 3:21-30. These components are no different
`
`from the components used in many of the modules that I worked with in the 1980s.
`
`In fact, it was routine for modules to include a microprocessor for performing
`
`control functions and driving overall operation of the module; a math coprocessor
`
`for performing mathematical calculations at high speed for encryption and
`
`
`
`6
`
`Page 10 of 95
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`decryption of information; memory circuitry for recording transactions,
`
`maintaining balance and key information, and storing applications; input/output
`
`circuitry for communicating with other devices; a real time clock for generating
`
`time stamps to secure and account for transactions; and an energy circuit for power
`
`other components.
`
`16. The ’013 patent provides some examples of how its module could be
`
`used. For example, the ’013 patent explains how the module can be used as a
`
`digital cash dispenser, how the module can be replenished with cash, and how the
`
`module can transfer cash to another module. Ex. 1001 at 7:63-12:34. However,
`
`these general uses were also well known back in the 1980s, and many of the
`
`modules that I worked with at that time provided for them.
`
`17. The ’013 patent includes sixteen claims, of which only claims 1 and 9
`
`are independent. For example, claim 1 recites a microcontroller based secure
`
`transaction integrated circuit comprising “a microcontroller core,” “a math
`
`coprocessor,” “memory circuitry,” “an input/output circuit,” and “a real time
`
`clock.” In full, claim 1 recites:
`
`A microcontroller based secure transaction
`1.
`integrated circuit comprising:
`a microcontroller core;
`a math coprocessor connected to said
`microcontroller core, said math coprocessor being for
`
`
`
`7
`
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`handling complex mathematics of encryption and
`decryption;
`memory circuitry which can be programmed by
`a service provider to enable said microcontroller based
`secure transaction integrated circuit to perform
`predetermined functions on behalf of the service
`provider and for the benefit of an end user, said
`memory circuitry being connected to said
`microcontroller core;
`
`an input/output circuit, connected to said
`microcontroller core, for exchanging information with
`a device external to said microcontroller based secure
`transaction integrated circuit; and
`a real time clock, connected to said
`microcontroller core, for providing a time
`measurement for time stamping a predetermined
`function.
`Person of Ordinary Skill in the Art
`
`V.
`
`18.
`
`In my opinion, a person of ordinary skill in the art would be a person
`
`with a Bachelor of Science degree in electrical engineering or computer
`
`engineering with at least two years of practical or post-graduate work in the area of
`
`secure financial transactions and integrated circuits. I have employed individuals
`
`who regularly perform smart card solution design and development work with such
`
`skills.
`
`
`
`8
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`VI. Claim Construction
`
`19.
`
`I have been advised that the first step of assessing the validity of a
`
`patent claim is to interpret or construe the meaning of the claim.
`
`20.
`
`I have been advised that in post-grant review proceedings before the
`
`U.S. Patent and Trademark Office, a patent claim receives the broadest reasonable
`
`construction in light of the specification of the patent in which it appears. I have
`
`also been advised that, at the same time, claim terms are given their ordinary and
`
`accustomed meaning as would be understood by one of ordinary skill in the art. I
`
`have been informed that the construction of a patent claim applied during this
`
`proceeding may differ from that in a district court proceeding.
`
`21.
`
`I have reviewed the constructions presented by Maxim and
`
`recommended by the Special Master. The adoption of either of these constructions,
`
`or any other proper construction under the broadest reasonable construction, would
`
`not change my opinions set forth below.
`
`VII. Certain References Disclose and/or Render Obvious All Elements of
`Claims 1-6, 8-12, 14, and 15 of the ’013 Patent
`
`22.
`
`In my opinion, Hawkes discloses and/or renders obvious all elements
`
`of claims 1-3, 6, 8, 9, 11, 12, 14, and 15; Hawkes in combination with Cooper
`
`renders claims 4 and 10 obvious; Hawkes in combination with Hardware Hacker
`
`renders claim 5 obvious; Chorley discloses all elements of claims 1-3, 6, 9, 11, 12,
`
`14, and 15; Chorley in combination with Hawkes renders claims 1-3, 6, 8, 9, 11, 12,
`
`
`
`9
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`14, and 15 obvious; Chorley in combination with Cooper or in combination with
`
`Hawkes and Cooper renders claims 4 and 10 obvious; Chorley in combination with
`
`Hardware Hacker or in combination with Hawkes and Hardware Hacker renders
`
`claim 5 obvious; Blandford discloses all elements of claims 1-4, 6, 9, 10, 12, and
`
`15; and Blandford in combination Hardware Hacker renders claim 5 obvious.
`
`A. Hawkes Discloses All Elements of Claims 1-3, 6, 8, 9, 11, 12, 14,
`and 15 of the ’013 Patent
`
`23. For the reasons described below and in the claim charts attached as
`
`Appendix A to this declaration, it is my opinion that Hawkes discloses each and
`
`every element of claims 1-3, 6, 8, 9, 11, 12, 14, and 15 of the ’013 patent.
`
`24. Hawkes was published in 1990. I have been informed that Hawkes is
`
`prior art to the ’013 patent under 35 U.S.C. § 102(a).
`
`25. Hawkes is a book edited by P.L. Hawkes, D. W. Davies and W. L.
`
`Price, which describes efforts underway in smart cards in 1990 including a number
`
`of notable implementations and project developments. Hawkes introduces the
`
`concepts and framework for the design and development of a secure module for
`
`financial and other types of services for secure protected information exchange.
`
`Part of the book is devoted to an initiative undertaken by the UK National Physical
`
`Laboratory (NPL) along with other stakeholders sponsored by the Tokens and
`
`Transactions Control Consortium (TTCC), which developed an intelligent active
`
`secure token called the “NPL” or “Talisman” token. Ex. 1011 at chapter 6.
`
`
`
`10
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`
`26.
`
`In my opinion, the NPL or Talisman token is “a microcontroller based
`
`secure transaction integrated circuit.” Hawkes confirms this in its explanation of
`
`the design of the token at page 7: “The Talisman token incorporates encryption
`
`means for generating a cryptographic version of messages sent from the token to
`
`remote computers or other tokens such that the message cannot be read by any but
`
`the intended recipient and he can authenticate that the message must have come
`
`from that token and no other.” Ex. 1011 at 7. Hawkes provides further
`
`confirmation in its explanation of the design of the token at page 84: “The basic
`
`token design therefore includes the ability to calculate digital signatures using a
`
`stored secret key. Since the ability to calculate signatures is a fundamental
`
`requirement in the device, it is convenient to apply this ability to calculating
`
`signatures on transaction messages authorised by the token holder. Transaction
`
`messages signed in this way can be checked anywhere in the transaction
`
`processing system where a reliable copy of the corresponding public key is
`
`available.” Ex. 1011 at 84; see also id. at 89. Figure 6.3, reproduced below,
`
`illustrates the token.
`
`
`
`11
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`
`
`1. Microcontroller Core
`
`27.
`
`In my opinion, the token of Hawkes includes “a microcontroller core,”
`
`which Hawkes calls a “control processor” (referring to Figure 6.3). Hawkes also
`
`discloses a few example control processors that were commercially available
`
`including an Intel 8085 and the Texas Instruments TMS7000 series 8-bit
`
`microprocessors. Ex. 1011 at 87. These devices were implemented in at least one
`
`version of the token. Id.
`
`2. Math Coprocessor // Modular Exponentiation Accelerator
`Circuit
`
`28.
`
`It is also my opinion that the token of Hawkes includes “a math
`
`coprocessor connected to said microcontroller core, said math coprocessor being
`
`
`
`12
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`
`for handling complex mathematics of encryption and decryption,” and “a modular
`
`exponentiation accelerator circuit, in communication with said microcontroller
`
`core, for performing encryption and decryption calculations.” Hawkes calls its
`
`math coprocessor/modular exponentiation circuit an “RSA processor” (referring to
`
`Figure 6.3), and explains on page 86: “This device, the TMS32010, is a 16-bit
`
`microprocessor with an instruction execution time of 200 ns. The instruction set
`
`includes a signed 16-bit multiply executed in one cycle. Although not ideal
`
`(overflow and the sign bit caused problems) this processor was programmed to
`
`perform the RSA calculations. The new design continues to use this processor.”
`
`Hawkes also states, “The Talisman token incorporates encryption means for
`
`generating a cryptographic version of messages sent from the token to remote
`
`computers or other tokens such that the message cannot be read by any but the
`
`intended recipient and he can authenticate that the message must have come from
`
`that token and no other.” Ex. 1011 at 7.
`
`3. Memory Circuitry // Memory Circuit
`
`29.
`
`In my opinion, the token of Hawkes also includes “memory circuitry
`
`which can be programmed by a service provider to enable said microcontroller
`
`based secure transaction integrated circuit to perform predetermined functions on
`
`behalf of the service provider and for the benefit of an end user, said memory
`
`circuitry being connected to said microcontroller core,” and “a memory circuit, in
`
`
`
`13
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`communication with said microcontroller core, for storing a transaction program.”
`
`Hawkes calls its memory circuitry/circuit “data memory” and “program memory”
`
`(referring to Figure 6.3), and explains that although “32 K bytes of program
`
`memory are available, most applications to date have used only half of this
`
`amount.” Ex. 1011 at 87. Hawkes also states, “Therefore it is likely that these
`
`tokens will be specialised to certain types of application, such as banking. Within
`
`this general area, provided there are agreements on protocols and message formats,
`
`the range of possible transactions could be large. For these transactions, a number
`
`of banks and financial institutions could collaborate with a single token held by the
`
`user. The digital signature principle overcomes the security problems of this
`
`arrangement.” Ex. 1011 at 161.
`
`4.
`
`Input/Output Circuit
`
`30.
`
`It is also my opinion that the token of Hawkes includes “an
`
`input/output circuit, connected to said microcontroller core, for exchanging
`
`information with a device external to said microcontroller based secure transaction
`
`integrated circuit,” and “an input/output circuit, in communication with said
`
`microcontroller core, for receiving and transmitting data information with another
`
`electronic device.” Hawkes calls its input/output circuit a “Serial I/O” (referring to
`
`Figure 6.3). I interpret “I/O” to mean input/output. Hawkes describes the Serial I/O
`
`on page 87 as follows: “Communication between the token and the outside world
`
`
`
`14
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`
`is by way of a three-wire serial interface.” The interface is used in an
`
`authentication process (see figure 6.1 on page 85) in which a random challenge is
`
`sent from a terminal to the token.
`
`5.
`
`Real Time Clock // Clock Circuit
`
`31.
`
`In my opinion, the token of Hawkes also includes “a real time clock,
`
`connected to said microcontroller core, for providing a time measurement for time
`
`stamping a predetermined function,” and “a clock circuit for measuring time and
`
`providing time stamp information responsive to functions being performed by said
`
`microcontroller core.” Hawkes calls its clock/clock circuit a “clock” (referring to
`
`Figure 6.3), and explains on page 87: “The clock maintains information about the
`
`date and time of day, this is used in some applications to date stamp messages.”
`
`Hawkes also states, “To avoid replays of transactions, it is necessary to include a
`
`time and date field in the message.” Ex. 1011 at 85.
`
`6.
`
`Energy Circuit
`
`32.
`
`It is also my opinion that the token of Hawkes includes “an energy
`
`circuit connected to said memory circuitry,” which Hawkes calls a “battery.” For
`
`example, Hawkes refers to “battery backed RAM” and indicates that certain
`
`functions could run “under battery operation.” Ex. 1011 at 87-88.
`
`
`
`15
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`
`33. For the foregoing reasons and as laid out in the claim charts attached
`
`as Appendix B to this declaration, it is my opinion that Hawkes discloses each and
`
`every element of claims 1-3, 6, 8, 9, 11, 12, 14, and 15 of the ’013 patent.
`
`B. Hawkes Renders Claims 1-3, 6, 8, 9, 11, 12, 14, and 15 of the ’013
`Patent Obvious
`
`34. As described above and shown in the claim charts attached as
`
`Appendix B, Hawkes discloses all of the elements of claims 1-3, 6, 8, 9, 11, 12, 14,
`
`and 15. However, to the extent the preamble of either claim 1 or claim 9 is
`
`interpreted to require that all claim elements be part of a single integrated circuit
`
`(as opposed to a combination of multiple integrated or discrete circuits) and to the
`
`extent it is found that Hawkes does not explicitly disclose such a single integrated
`
`circuit, it would have at least been obvious to one of ordinary skill in the art to
`
`combine the circuits of Hawkes into a single integrated circuit. For example, as
`
`Hawkes specifically contemplated, “it will be feasible to miniaturise the intelligent
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`token still further.” Ex. 1011 at 90. Hawkes also explained that miniaturization
`
`could be achieved by combining circuits. Ex. 1011 at 89. And it would have been
`
`routine for one of ordinary skill in the art to do so.
`
`C. Hawkes in Combination With Cooper Renders Claims 4 and 10 of
`the ’013 Patent Obvious
`
`35. For the reasons described below, it is my opinion that Hawkes in
`
`combination with Cooper renders claims 4 and 10 of the ’013 patent obvious.
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`36. Cooper was published on June 10, 1993. I have been informed that
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`Cooper is prior art to the ’013 patent under 35 U.S.C. § 102(a).
`
`37. Claim 4 depends from claim 3 and requires that “said memory
`
`circuitry is non-volatile RAM.” Claim 10 depends from claim 9 and similarly
`
`requires that “said memory circuit is a nonvolatile RAM.” As described above and
`
`shown in the claim charts attached as Appendix B, Hawkes discloses or renders
`
`obvious all of the elements of claims 3 and 9
`
`38. Hawkes also discloses that “32 K bytes of program memory are
`
`available.” Ex. 1011 at 87. In addition, Hawkes discloses that “[t]he exact form of
`
`memory used in these devices varies widely from UV or electrically
`
`reprogrammable memory devices to battery backed RAM (random access
`
`memory).” Ex. 1011 at 3. Battery backed RAM is a form of persistent storage and
`
`is desirable for many security applications, including inventions I developed in the
`
`1980s for secure portable electronic transaction devices. The use of battery backed
`
`RAM provides a way to rapidly erase any sensitive information, such as encryption
`
`keys in the event of tampering.
`
`39. To the extent it is found that Hawkes does not explicitly disclose the
`
`specific type of memory circuit or circuitry which can be programmed by the
`
`service provider, it would have at least been obvious to one of ordinary skill in the
`
`art to use non-volatile RAM as the program memory. Indeed, such RAM devices
`
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`were well-known in the art. See, e.g., Cooper, Ex. 1012, at Abstract. It would have
`
`been routine for one of ordinary skill in the art to use them, and they would have
`
`provided well-known advantages (e.g., reducing the power needed from the energy
`
`circuit). These advantages were well known in the art at the time of the alleged
`
`invention.
`
`D. Hawkes in Combination With Hardware Hacker Renders Claim 5
`of the ’013 Patent Obvious
`
`40. For the reasons described below, it is my opinion that Hawkes in
`
`combination with Hardware Hacker renders claim 5 of the ’013 patent obvious.
`
`41. Hardware Hacker was published in July, 1993. I have been informed
`
`that Hardware Hacker is prior art to the ’013 patent under 35 U.S.C. § 102(a).
`
`42. Claim 5 depends from claim 1 and requires that “said microcontroller
`
`based secure transaction integrated circuit is programmed in a script programming
`
`language.” As described above and shown in the claim charts attached as Appendix
`
`B, Hawkes discloses or renders obvious all of the elements of claim 1. Hawkes also
`
`discloses that “a high-level language can be used for the application software.” Ex.
`
`1011 at 87. To the extent it is found that Hawkes does not explicitly disclose the
`
`specific type of programming language used, it would have at least been obvious to
`
`one of ordinary skill in the art to use one of the many well-known script
`
`programming languages. For example, Hardware Hacker discusses two script
`
`programming languages, BASIC and PostScript. Ex. 1013 at 66.1-66.2. Using such
`
`
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`programming languages would allow for faster development of application
`
`software by providing abstraction of the underlying environment, thereby
`
`eliminating the need for software developers to explicitly identify and control each
`
`and every aspect of the software’s functionality down to specific locations (e.g.,
`
`specific memory cells) as would be necessary if programming in a low level (or
`
`machine level) language without the benefit of abstraction. These advantages of
`
`script programming languages were well known in the art at the time of the alleged
`
`invention. Moreover, it would have been routine for one of ordinary skill in the art
`
`to use such languages to program the functionality of the Hawkes token.
`
`E.
`
`Chorley Discloses All Elements of Claims 1-3, 6, 9, 11, 12, 14, and
`15 of the ’013 Patent
`
`43. For the reasons described below and in the claim charts attached as
`
`Appendix C to this declaration, it is my opinion that Chorley discloses each and
`
`every element of claims 1-3, 6, 9, 11, 12, 14, and 15 of the ’013 patent.
`
`44. Chorley was published at least as early as 1989. I have been informed
`
`that Chorley is prior art to the ’013 patent under 35 U.S.C. § 102(a).
`
`45. Chorley is an article by B J Chorley and W L Price, which describes
`
`the design of an intelligent token developed by the National Physical Laboratory in
`
`the UK, the same token discussed by Hawkes.
`
`46.
`
`In my opinion, the intelligent token is “a microcontroller based secure
`
`transaction integrated circuit.” Chorley confirms this on page 391: “Our purpose in
`
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`presenting this paper is to examine some aspects of the process of verifying the
`
`identity of authorised users and also the integrity of the transactions carried out on
`
`their behalf. We shall then develop a specification for an intelligent token that can
`
`participate effectively in achieving identity verification and transaction integrity.”
`
`Figure 1 on page 394, reproduced below, illustrates the token.
`
`
`
`1. Microcontroller Core
`
`47.
`
`In my opinion, the token of Chorley includes “a microcontroller core,”
`
`which Chorley calls an “Intel 8085 microprocessor” of the control module of
`
`Figure 1. For example, page 394 of Chorley states, “The token consists of two
`
`main parts (figure 1), the [Texas Instruments] TMS32010 and associated ROM and
`
`RAM storage, and a control module built around an Intel 8085 microprocessor; in
`
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`the control module we have, in addition to ROM and RAM storage, time of day
`
`clock, input/output interface, display and keyboard. The two parts of the unit are
`
`linked via a bus buffer.”
`
`2. Math Coprocessor // Modular Exponentiation Accelerator
`Circuit
`
`48.
`
`It is al