A. E. FITZGERALD, SC.D.
`Late Vice President for Academic Affairs
`and Dean of the Faculty
`Northeastern University
`
`DAVID E. HIGGINBOTHAM, S.M.
`Late Professor and Chief
`Electrical Engineering Section
`United States Coast Guard Academy
`
`ARVIN GRABEL, SC.D.
`Professor of Electrical Engineering
`Northeastern University
`
`BASIC
`ELECTRICAL
`ENGINEERING
`
`CIRCUITS
`ELECTRONICS
`MACHINES
`CONTROLS
`
`Fifth Edition
`
`McGRAW-HILL BOOK COMPANY
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`Lockwood Exhibit 2024
`eBay v. Lockwood
`CBM2014-00026
`
`

`

`BASIC
`ELECTRICAL
`ENGINEERING
`
`Copyright© 1981, 1975, 1967, 1957 by McGraw-Hill, Inc.
`All rights reserved .
`Copyright 1945 by McGraw-Hill , Inc.
`All rights reserved .
`Copyright renewed 1973 by A. E. Fitzgerald.
`Printed in the United States of America.
`No part of this publication may be reproduced ,
`stored in a retrieval system , or transmitted ,
`in any form or by any means ,
`electronic, mechanical, photocopying ,
`recording, or otherwise,
`without the prior written permission of the publisher.
`
`34567890 HDHD 898 76 543
`
`This book was set in Times Roman by Progressive Typographers.
`The editors were Frank J . Cerra and J . W. Maisel ;
`the designer was Nicholas Krenitsky;
`the production supervisor was Dominick Petrellese.
`New drawings were done by J & R Services , Inc.
`
`Library of Congress Cataloging in Publication Data
`
`Fitzgerald , Arthur Eugene , date
`Basic electrical engineering .
`
`(McGraw-Hill series in electrical engineering Net-
`works and systems)
`Includes index.
`1. Electric engineering . 2. Electronics.
`I. Higginbotham , David E., joint author.
`II . Grabel ,
`Arvin , joint author.
`Ill. Title.
`IV. Series .
`TK145.F53 1981
`621.3
`80-19420
`ISBN 0-07-021154-X
`ISBN 0-07-021155-8 (solutions manual)
`
`

`

`12-6 SEMICONDUCTOR MEMORIES
`
`663
`
`M-input
`lines
`
`.
`.
`.
`
`2M lines
`
`.
`.
`.
`
`M to 2M
`lines
`decoder
`
`Line
`selector
`inputs
`
`2M XL
`Matrix array
`
`. . .
`
`L- lines
`
`L toN line selector
`
`II . . .
`
`N-output bits
`
`FIGURE 12-22 Two-dimensional addressing.
`
`selectors act as a Y-dimension address decoder in that they select N lines of
`the matrix. The decoding process allows for L/N different combinations to
`appear at the output. Therefore, each of the 2M addresses (X-dimension) de(cid:173)
`fine L /N different N-bit words. For example, a 64 x 64 array which can
`store 4,096 bits (called a 4-kb ROM) can be organized as show n in Fig. 12-23 .
`The six input lines define the 64 rows and the eight 8: 1 line selectors provide
`an 8-bit output word. The logic actuating the line selectors can select any
`one of 8 different 8-bit output words for a given input address. The total
`number of words stored is then 64 x 8 = 512. To store 512 8-bit words using
`one-dimensional addressing requires 9 input lines (29 ) and, therefore, in(cid:173)
`creased complexity in the decoder.
`In addition to storing instructions, ROMs are useful elements in auto(cid:173)
`matic test equipment. By storing the values of sin x, for specific values of x,
`the ROM can be used as a function generator to provide a variety of test
`signals to a device undergoing test. Comparison of measured results with ex(cid:173)
`pected results (also stored in memory) determines whether the device in
`question meets design specifications .
`A PROM is a field-programmable read-only m emory which is con(cid:173)
`structed with all possible memory values present. Each, outcome is connected
`to a fused link which can be opened by injecting a current into the memory
`cell . Once the fused link is opened, the program is set and the action of a
`PROM is that of a standard ROM. The advantage is that the user can pro(cid:173)
`gram each PROM to fit a specific application and still retain the advantage of
`using several of the same components in a system. EPROMs are Erasable
`PROMs in which special construction allows for the link to be opened or
`reclosed by means of ultraviolet radiation. Consequently, the program c~m
`
`

`

`664 DIGITAL COMPUTATION
`
`6 input
`lines
`
`64 lines
`
`.
`. .
`
`6 to 64
`line
`decoder
`
`"'
`:.0
`
`"' "' Q) -o "'0 <
`
`3-line
`selector
`inputs
`
`64 X 64
`matrix
`
`r
`
`~
`
`r-
`r-
`r-
`
`"'
`
`. .
`.
`
`~
`
`. .
`.
`
`8-bit outputs
`
`"' Eight
`
`8:1 line
`selectors
`
`FIGURE 12-23 A 64 x 64 bit array with two-dimensional addressing.
`
`be altered after it is entered. However, the process for changing a program
`is slow (20 to 30 min) so that program alterations cannot be made during
`operation.
`The random-access memory (RAM) , a basic read-write memory , is also
`organized in a matrix array. As illustrated in Fig . I2-24, two-dimensional ad(cid:173)
`dressing is used for the 4-kb RAM whose outputs are 4,096 one-bit words.
`To insert data into the RAM the write-logic is enabled and the read is inhib(cid:173)
`ited . The reverse is true to read a bit out of the memory by means of the
`sense amplifier. To store 4,096 eight-bit words, eight arrays of the form
`shown in Fig. I2-24 are used, each of which is addressed in parallel. Each
`array, however, has provision for individual data-in and data-out signals.
`The addressing of a RAM allows a bit to be entered or retrieved at any
`location in the memory; i.e. , it is randomly accessed. The data stored can be
`electrically changed; however, RAMs are volatile memories.
`The circuits shown in Fig. I2-25 are 1-bit static and dynamic MOSFET
`memory cells. The static memory cell in Fig. I2-25a employs a pair of
`cross-coupled INVERTERs with active loads (see Sees. II-8 and JI-9). As
`the INVERTER outputs are complementary both logical 0 and I can be en(cid:173)
`tered or retrieved. The transistors labelled Q I are used for X-dimension
`addressing; Y-dimension addressing and the read-write circuitry is not
`
`