Exhibit 1006
`
`.
`Umted States Patent
`
`[19]
`
`lllIIlllIlIIlllllIIlll||l|l||||l|||l||||l||||l||||||Illllllllllllllllllllll
`USOOS446757A
`[11] Patent Number:
`
`5,446,757
`
`
`
` Chang [45] Date of Patent: Aug. 29, 1995
`
`
`
`[54] CODE-DIVISION-MULTIPLE-ACCESS-SYS-
`TEM BASED ON M-ARY PULSE-POSITION
`MODULATED DIRECT-SEQUENCE
`
`[76]
`
`Inventor:
`
`Chen-Y1 Chang, 1001 Ta Hsueh
`Road, Hsmchu,
`[21] App]. No.: 77,347
`.
`Jun. 14, 1993
`[22] Flle‘l:
`.
`51
`Int. Cl.6 .......................... H03K 7 04 H04B 1/00
`iszi US. Cl. ....................... 37/5/5219; 375/200
`
`[53] Field of Search ...................................... 375/23 1
`’
`[56]
`References Cited
`U.S. PATENT DOCUMENTS
`
`8/1993 091“”-
`5:235’615
`
`5’329’546 7/1994 Lee "
`
`5,329,547 7/ 1994 Ling .....................
`Primary Examiner—Edward L. Coles, Sr.
`Assistant Examiner—Allan A. Esposo
`
`375/205
`375/205
`375/206
`
`Attorney, Agent, or Firm—~Ladas & Parry
`[57]
`ABSTRACT
`A BPSK—MPP-DS—CDMA system is devised using a
`pulse position modulated direct sequence technique.
`Under the same bandwidth, same energy used for one
`decision, and same bit error rate conditions, if the num-
`ber of users is less than the period NCp of the pseudoran—
`dom sequence signal PNpi(t) used in the BPSK—MPP-
`DS-CDMA system, the multiple access capacities of the
`.
`binary (54:2): ternary 04:3): quaternary (M=4)’ and
`1’6an “=3 BPSK'MPP'DS'CDMA ”Stems 3°-
`cording to the present invention are respectively at least
`2, 5.34, 13.28, and 26.4 times greater than that of the
`conventional BPSK-DS-CDMA systems. On 1115 other
`hand, if the number of users attains Ncp, the multiple
`access capacity can not increase any more, however,
`the bit error rate of the system will be reduced. Further-
`more, (M—1)/M transmitting energy is saved.
`
`13 Claims, 19 Drawing Sheets
`
`
`
`Absolute
`296
`value
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`
`_
`
`Liberty Mutual
`
`Exhibit 1006
`
`Page 000001
`
`Page 000001
`
`

`

`US. Patent
`
`Aug. 29, 1995
`
`Sheet 1 of 19
`
`5,446,757
`
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`Page 000002
`
`Page 000002
`
`

`

`US. Patent
`
`Aug. 29, 1995
`
`Sheet 2 of '19
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`5,446,757
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`US. Patent
`
`Aug. 29, 1995
`
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`5,446,757
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`US. Patent
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`Aug.
`
`29
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`US. Patent
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`Aug. 29, 1995
`
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`US. Patent
`
`Aug. 29, 1995
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`US. Patent
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`Aug. 29, 1995
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`US. Patent
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`Aug. 29, 1995
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`US. Patent
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`Aug. 29, 1995
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`US. Patent
`
`Aug. 29, 1995
`
`Sheet 10 of 19
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`5,446,757
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`US. Patent
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`Aug. 29, 1995
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`US. Patent
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`Aug. 29, 1995
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`US. Patent
`
`Aug. 29, 1995
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`US. Patent
`
`Aug. 29, 1995'
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`Sheet 14 of 19
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`US. Patent
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`Aug. 29, 1995
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`US. Patent
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`Aug. 29, 1995
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`US. Patent
`
`Aug. 29, 1995'
`
`Sheet 17 of 19
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`5,446,757
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`

`US. Patent
`
`Aug. 29, 1995
`
`Sheet 18 of 19
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`5,446,757
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`US. Patent
`
`Aug. 29, 1995
`
`Sheet 19 of 19
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`5,446,757
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`

`

`1
`
`5,446,757
`
`CODE-DIVISION-MULTIPLE-ACCESS-SYSTEM
`BASED ON M-ARY PULSE-POSITION
`MODULATED DIRECT-SEQUENCE
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates in general to a method
`of data transmission and reception, and more specifi—
`cally, to a method of data transmission and reception
`using code-division-multiple-access
`(CDMA)
`tech-
`nique.
`2. Description of Prior Art
`The spread-spectrum technique is a technique devel-
`oped since about the mid-1950’s. A detailed description
`of the conventional spread-spectrum systems can be
`found in a tutorial entitled “Theory of Spread Spectrum
`Communications—A Tutorial” authored by Raymond
`L. Pickholtz et al. and published on IEEE Trans. Com-
`mun., Vol. COM-30, pp. 855-884, May 1982.
`The conventional BPSK (Binary-Phase-Shift-Key-
`ing) direct sequence spread spectrum communication
`system is shown in FIG.
`lA—lB. A multiple access
`communication system that employs spread spectrum
`technique is technically termed as a code division multi-
`ple access (CDMA) system The configuration of a
`basic CDMA system is shown in FIG. 2. A more detail
`description of the conventional BPSK-DS-SS (or
`BPSK-DS-CDMA) system of FIG. 1 will be given in
`the paragraphs under the header “Performance Evalua-
`tions.”
`The CDMA technique was developed mainly for
`capacity reasons. Ever since the analog cellular system
`started to face its capacity limitation in 1987, research
`efforts have been conducted on improving the capacity
`of digital cellular systems. In digital systems, there are
`three basic multiple access schemes: frequency division
`multiple access (FDMA), time division multiple access
`(TDMA), and code division multiple access (CDMA).
`In theory, it does not matter whether the channel is
`divided into frequency bands, time slots, or codes; the
`capacities provided from these three multiple access
`schemes are the same. However, in cellular systems, we
`might find that one scheme may be better than the
`other.
`A list of technical references pertinent to the subject
`matter of the present invention is given below:
`[1] “Overview of Cellular CDMA”, by William C. Y.
`Lee, IEEE Trans. Veh. Tech, Vol. 40, No. 2, pp.
`291—302, May 1991.
`[2] “On the Capacity of a Cellular CDMA System”,
`by A. J. Viterbi, L. A. Weaver, and C. E. Wheatley III,
`IEEE Trans. Veh. Tech., Vol. 40, No. 2, pp. 303-312,
`May 1991.
`[3]“A Statistical Analysis of On-off Patterns in 16
`Conversations”, by P. T. Brady, Bell Syst. Tech. J.,
`Vol. 47, pp. 73—91, Jan. 1968.
`[4]“Coherent Spread Spectrum Systems”, by J. K.
`Holmes, John Wiley and Sons, New York, pp. 388—389,
`1982.
`[5] “Error Probability of Asynchronous Spread Spec-
`trum Multiple Access Communications Systems”, by K.
`Yao,
`IEEE Trans. Commum. Vol. COM-25, pp.
`803-807, 1977.
`[6] “Direct-Sequence Spread Spectrum Multiple-
`Access Communications with Random Signature Se-
`quences: Large Deviations Analysis”, by .T. S. Sa-
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`65
`
`2
`dowsky and R. K. Bahr, IEEE Trans. Inform. Theory
`Vol. 37, No. 3, pp. 514-527, May 1991.
`[7] “Digital Communications and Spread Spectrum
`Systems”, by R. E. Ziemer and R. L. Peterson, Macmil-
`lan, New York, Ch. 11, 1985.
`[8] “Spread Spectrum Multiple Access Communica-
`tions, Multi-User communication Systems”, by M. B.
`Pursley, edited by G. Longo, Springer-Verlag, N.Y. pp.
`139—199, 1981.
`[9]
`“Performance Evaluation for Phase-Coded
`Spread-Spectrum Multiple-Access Communication—
`Part 11: Code Sequence Analysis”, by M. B. Pursley and
`D. V. Sarwate, IEEE Trans. Commun., Vol. Com-25,
`No. 8, pp. 800-803, August 1977.
`Remarkable results have been derived in the pertinent
`reference [2], “On the Capacity of a Cellular CDMA
`System” by A. J. Viterbi et al. This technical paper
`shows that the net improvement in the capacity of
`CDMA systems is four to six times better than that of a
`digital TDMA or FDMA system, and nearly 20 times
`better than that of current analog FM/FDMA system.
`Therefore, the CDMA scheme may become a major
`system in future communication systems.
`The reason for the improvement in the multiple ac-
`cess capacity of the CDMA system mentioned above is
`that the capacity of the CDMA system is inversely
`proportional to cross-correlation noise, which is influ-
`enced or can be reduced by: (1) voice activity with a
`duty factor of approximately 2; and (2) spatial isolation
`through use of multi—beamed or multi-sectored anten-
`nas. Therefore if we can find another factor which can
`reduce the cross-correlation noise, the multiple access
`capacity will increase correspondingly.
`SUMMARY OF THE INVENTION
`
`A primary object of the present invention is to pro-
`vide a CDMA system by which the multiple access
`capacity is increased and the transmitting energy is
`decreased compared to the conventional BPSK-DS—
`CDMA system.
`In accordance with the above objects, a code division
`multiple access (CDMA) system based on M-ary pulse
`position modulated direct sequence is provided. This
`system is called a BPSK-MPP-DS-CDMA (Binary-
`Phase-Shift-Keyed M-ary Pulse-Position-Modulated-
`Direct-Sequence) system. The data source in this sys-
`tem sends out a sequence of data bits with bit duration
`T. According to the present invention the system first
`converts the serial binary data stream into M parallel bit
`sequences. These M parallel bit sequences can thus be
`considered as a sequence of M-bit vectors with each bit
`having a duration of MT. A number Ncp, which is the
`period of a pseudorandom process PNp(t), is selected to
`divide each MT duration into NC, intervals with every
`interval having a duration Tcp, where TCP=MT/Ncp.
`Each interval TCP is further divided into 21'4—1 pulse
`positions, each pulse position having a duration Ts,
`Ts=TcP/2M-1. Each M-bit vector is converted into a
`corresonding block of Nap duty pulses in every interval
`MT, with each duty pulse set in accordance with a
`predetermined mapping table to appear in one of the
`2M—1 pulse positions and with a certain polarity. This
`duty pulse train is then modulated with a sample PNpKt)
`of the pseudorandom process PNp(t). The modulated
`signal is modulated further by a carrier signal and then
`is transmitted over the channel of the communication
`system.
`
`Page 000021
`
`Page 000021
`
`

`

`5,446,757
`
`3
`In the receiving end of the communication system,
`the received signal is demodulated synchronously by
`the carrier signal and the pseudorandom sequence sig-
`nal PNPi(t) to recover each duty pulse block during a
`duration MT. The pulse position and the polarity of the
`Nap pulses in each received duty pulse block are deter-
`mined and are used to find the bit pattern represented
`by each received duty pulse block by using the prede-
`termined mapping table in a reverse manner. In this
`way, a vector of M parallel data bits are recovered
`during this duration MT.
`Under the condition that the energy used for one
`decision (this energy will be defined in the paragraphs
`under the header “Performance Evaluations”) in all
`concerned systems
`is equal,
`the BPSK-MPP-DS-
`CDMA system according to the present invention has
`three improved characteristics over the conventional
`BPSK-DS-CDMA system. These improved character-
`istics include reduction of cross-correlation noise, an
`increase in multiple access capacity, and reduction of
`transmitting energy.
`'
`The cross-correlation noise is reduced by a factor of
`4 if the system is based on M=2; 12 if the system is
`based on M=3, 32 if the system is based on M=4, and
`80 if the system is based on M: 5. If the multiple access
`capacity is not limited by the period N4, of the pseudo-
`random sequence signal PNpi(t), then under the same
`bandwidth and same bit error rate constraints, the mul-
`tiple access capacity is improved by a factor at least of
`2 if the system is based on M=2; 5.34 if the system is
`based on M=3; 13.28 if the system is based on M=4;
`and 26.4 if the system is based on M=5. Conversely, if
`the multiple access capacity is limited by Ncp, that is
`after the number of users attain Ncp, the extra reduction
`in cross-correlation noise can reduce the bit error rate
`of the system.
`For a general M-ary system, the tramsmitting energy
`is only l/M of that in the conventional system, i.e.,
`(M—l)/M of the transmitting-energy is saved. The
`proofs of these results will be given in the performance
`evaluation of the prefered embodiment section.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention can be more fully understood
`by reading the subsequent detailed description of the
`preferred embodiments thereof with references made to
`the accompanying drawings, wherein:
`For the Conventional BPSK-DS-SS System:
`FIG. 1A shows the block diagram of a transmitter for
`the conventional BPSK direct sequence spread spec-
`trum system;
`FIG. 1B shows the block diagram of a receiver for
`the conventional BPSK direct sequence spread spec-
`trum system;
`FIG. 2 shows a basic CDMA communication system
`model;
`For the BPSK-BPP—DS—CDMA System:
`FIG. 3A shows the block diagram of a BPSK-BPP-
`DS—CDMA transmitter devised in accordance with the
`present invention;
`FIG. 3B shows the block diagram of a BPSK-BPP-
`DS-CDMA receiver devised in accordance with the
`present invention;
`FIGS. 4A—4D are four waveform patterns, showing
`the encrypted duty pulse trains generated respectively
`in response to the bit patterns of four different Z-bit
`vectors;
`
`4
`FIG. 5A shows the waveform of an example of a
`train of encrypted duty pulses;
`FIG. 5B shows an example of a pseudorandom se-
`quence signal used to modulate the pulse train of FIG.
`5A;
`FIGS. 6A-6B show the waveforms of two control
`pulse trains used respectively to control the ON/OFF
`mode of a pair of switches in the receiver of FIG. 3B;
`For the BPSK-TPP-DS-CDMA System:
`FIG. 7A shows the block diagram of a BPSK-TPP-
`DS-CDMA transmitter devised in accordance with the
`present invention;
`FIG. 7B shows the block diagram of a BPSK-TPP-
`DS—CDMA receiver devised in accordance with the
`present invention;
`FIGS. 8A—8H are eight waveform diagrams, show-
`ing the encrypted duty pulse trains generated respec-
`tively in response to the bit patterns of eight different
`3-bit vectors;
`FIG. 9A shows the waveform of an example of a
`train of encrypted duty pulses;
`FIG. 9B shows an example of a pseudorandom se-
`quence signal used to modulate the pulse train of FIG.
`9A;
`FIGS. lOA-IOD show the timing diagrams of four
`control pulse trains used respectively to control the
`ON/OFF mode of an array of four switches in the
`receiver of FIG. 73;
`FIG. 11 shows the block diagram of a modified
`BPSK-TPP-DS-CDMA receiver devised in accor-
`dance with the present invention;
`FIGS. 12A—12F show the waveforms of six control
`pulse trains used respectively to control the ON/OFF
`mode of the switches Sn, S12, 521, $22, $23, and $24 in
`the receiver of FIG. 11;
`For the BPSK-MPP-DS-CDMA System:
`FIG. 13A shows the block diagram of a generalized
`BPSK-MPP-DS-CDMA transmitter devised in accor-
`dance with the present invention;
`FIG. 13B shows the block diagram of a generalized
`BPSK-MPP-DS-CDMA receiver devised in accor-
`dance with the present invention; and
`FIGS. 14A—14B are diagrams used to depict how
`pulse positions are formed in a generalized M-ary sys-
`tem;
`_
`FIG. 15 shows the block diagram of a modified
`BPSK-MPP-DS-CDMA receiver devised in accor—
`dance with the present invention;
`For Performance Evaluations:
`FIGS.
`ISA—16B show a set of typical cross—cor-
`related waveforms of PNcij(t—6)PNc1i(t) for M=3.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`The present invention relates to a spread spectrum
`transmission and reception system based on an M-ary
`pulse position modulated direct sequence. In the follow-
`ing detailed descriptions, examples will be given for the
`cases of M=2 and M=3. Finally, a generalized BPSK-
`MPP-DS-CDMA system is described.
`EXAMPLE 1
`
`65
`
`A BPSK-BPP-DS-CDMA System (M=2)
`Referring to FIGS. 3A—3B, there show a BPSK-
`BPP-DS-CDMA (binary-phase
`shift-keyed binary—
`pulse-position modulated direct-sequence code-divi-
`sion-multiple-access) system devised in accordance
`
`Page 000022
`
`Page 000022
`
`

`

`5
`with the present invention. The transmitter portion of
`the system is shown in FIG. 3A and the receiver portion
`of the system is shown in FIG. 3B.
`The transmitter portion of the system, which is used
`to transmit binary signals from a data source 200 to a 5
`communication channel,
`includes a serial-to-parallel
`converter 210, a BPP—DS modulator 220, and a carrier
`modulator 230. The BPP-DS modulator 220 consists of
`a duty pulse encryptor 221 and a pulse modulator 222.
`In practice, a data bit “1” is transformed into a posi- 10
`tive square pulse with a duration of T and a data bit
`“—1” is transformed into a negative square pulse also
`with a duration of T at the output of the data source
`200. When a data bit stream BS=(bo, b1, b2: .
`.
`. , b,._1.
`.
`. ) is sent out from the data source 200 with a bit dura-
`tion of T and is to be transmitted over the communica-
`tion channel, the data bit stream BS is first converted by
`the serial-to-parallel converter 210 into two parallel bit
`streams BS1 and B82, BS1=(bo, b2, b4, . .
`. , by, . . . ) and
`BSz=(b1, b3, b5, .
`. . 1321+], .
`.
`. ). However, the duration
`of each bit in B81 and BS2 is 2T. Consequently, the 2—bit
`serial-to-parallel converter 210 sends out a sequence of
`2-bit vectors (1)21, b21+1), l =0,1,2,, .
`.
`. , to the BPP-DS
`modulator 220. Each thus formed 2-bit vector has a bit
`
`15
`
`20
`
`pattern which may be one of the four possible bit pat- 25
`terns as listed in the following Table-Al:
`TABLE Al
`
`(by, 132/41)
`(1. 1)
`(l, —l)
`(—1.1)
`(—1, —1>
`
`30
`
`45
`
`In the BPP-DS modulator 220, each Z-bit vector is 35
`processed firstly by the duty-pulseencryptor 221 and
`then modulated in the pulse modulator 222 with a pseu-
`dorandom sequence signal PNp‘It). In the present inven-
`tion, a number N01,, the period of the pseudorandom
`sequence signal PNpi(t), is used to divide the bit dura-
`tion 2T into Ncp equal intervals with each interval thus
`having a duration of 2T/Ncp. The duration 2T/Ncp is
`called the chip Tcp of the pseudorandom sequence signal
`PNpi(t). Each chip Top is divided into two pulse posi-
`tions (in general the number of pulse positions divided is
`equal to ZM—1 for M—ary system). The duration of each
`pulse position is T;, T5=Tcp/2. The two pulse positions
`within each Tcpare defined as “PP1” and “PPz”, respec—
`tively.
`The duty pulse encryptor 221 includes a built-in one-
`to-one mapping table defining the generating of a duty
`pulse train in response to the bit pattern of a 2-bit vector
`(b21b21+ 1). The preferred embodiment of the present
`invention incorporates a mapping table having the fol-
`lowing mapping relationships:
`(a) if the input 2-bit vector is (1, l), the duty pulse
`encryptor 221 sends out a package of N51, consecutive
`positive square pulses during the interval 2T with each
`square pulse appearing at the pulse position defined as
`“PPI”;
`(b) if the input 2-bit vector is (1,—1), the duty pulse
`encryptor 221 sends out a package of NC}; consecutive
`positive square pulses during the interval 2T with each
`square pulse appearing at the pulse position defined as
`“PPZ”;
`(c) if the input 2-bit vector is (—1, 1), the duty pulse
`encryptor 221 sends out a package of NC}, consecutive
`negative square pulses during the interval 2T with each
`
`50
`
`55
`
`60
`
`65
`
`5,446,757
`
`6
`square pulse appearing at the pulse position defined as
`“PPZ”; and
`(d) if the input 2-bit vector is (— l, - 1), the duty pulse
`encryptor 221 sends out a package of NCp consecutive
`negative square pulses during the period 2T with each
`square pulse appearing at the pulse position defined as
`(«PF1'” .
`The foregoing mapping relationships are summarized
`in the following Table-A2. They can also be schemati-
`cally visualized respectively from the diagrams of
`FIGS. 4A—4D.
`
`Bit Pattern
`(by, b21+1)
`(1, 1)
`(1, —1)
`(—1, 1)
`(— 1, - 1)
`
`TABLE A2
`
`encgypted Duty Pulse
`Pulse Position
`Polarity
`PPI
`+1
`PP;
`+1
`PF;
`—1
`PP1
`- l
`
`The square pulse in each chip TCp is termed as a “duty
`pulse.” Only one duty pulse will be present in each chip
`Tcp. For example, if the leading eight bits in the bit
`stream BS are (l, —1, —-l,
`-—-1, —1, l, l, I), then the
`duty pulse encryptor 221 will send out a corresponding
`signal x1(t) as illustrated in FIG. 5A. The thus formed
`signal n(t) is subsequently modulated by the pseudoran-
`dom sequence signal PNP‘It). The timing relationship
`between x1(t) and PNpi(t) can be seen from FIGS.
`5A-SB. The pseudorandom sequence signal PNp'It)
`contains Ncp consecutive pseudorandom bits with each
`bit having a duration of Tcp. The signal n(t) at the
`output of pulse modulator 222 is
`
`x2(t)=XI(t)PNp‘(t).
`
`(1)
`
`which is subsequently modulated at the carrier modula-
`tor 230 by a sinusoidal signal C(t)=\/fi sin(coot) to
`obtain a modulated signal x3(t) and thereby transmitted
`through the communication channel to its destination.
`Referring back to FIG. 3B, the transmitted signal is
`picked up by the receiver portion of the system located
`at the receiving end of the channel. For noise free situa-
`tion, the received signal is y1(t)=Ax3(t—r,-), where “A”
`is the amplitude of y1(t), and r; is the transmission delay
`of X3(t). The signal y1(t) is demodulated by multiplying
`it with a sinusoidal signal C(t—$;)=\/2 sin won—ii),
`where 7“,- is the estimate of 1;. Since the purpose of this
`description is only to demonstrate the operation of the
`system, A=l and 5",: n=0 can be assumed without the
`loss of generality. The demodulated signal y2(t) is then
`multiplied by a local pseudorandom sequence signal
`PNP‘Zt—rg), which should be in synchronization with
`the received PNpi(t—-7",-). The waveform of the signal
`y3(t) would be identical to x1(t) in FIG. 3A if no noise
`interference were present in the channel. However, no
`noise interference isonly an ideal condition and in prac-
`tice the signal y3(t) may be expressed as:
`
`yafl)=X1(t)+I(t)+n(t)y
`
`(2)
`
`where I(t) is the cross-correlation noise, and n(t) is the
`white noise.
`A pair of switches 81 and $2, with ON/OFF mode
`thereof being controlled respectively by a first pulse
`train CP1(t) and a second pulse train CP2(t), are con-
`nected in parallel to the output of the pulse-demodula-
`tor 232. The waveforms of the two pulse trains CP1(t)
`
`Page 000023
`
`Page 000023
`
`

`

`7
`and CP2(t) are shown in FIGS. 6A—6B. Each of the two
`pulse trains CP1(t) and CP2(t) is a periodic pulse train
`having pulse duration T5 and period exactly equal to
`Tap, where T3=Tcp/2. The appearance of one square
`pulse in the pulse train CP1(t) will actuate the switch 81 5
`to be turned ON; and the appearing of one square pulse
`in the pulse train CP2(t) will actuate the switch 32 to be
`turned ON. A pair of matched filters 241 and 242
`(which are integrate-and-dump circuits for the present
`invention) are connected respectively to the switches
`81 and 52 so that
`the signals passing through the
`switches S1 and $2, denoted by y,1(t) and y;2(t), are
`processed by the matched filters 241, 242 and sampled
`by a pair of samplers 251, 252. The outputs of the sam-
`plers 251, and 252 are denoted by zl(k) and 22(k), which
`are respectively given by:
`
`10
`
`15
`
`1
`2100 = 'T—
`
`22(k= T
`
`k1}
`
`(k - 1)T:
`(k + 0T:
`k7}
`
`y:1(t)dt
`
`MUM
`
`(3)
`
`(4)
`
`20
`
`, Ncp
`.
`.
`where k=1,2, .
`A pair of summers 261, 262 are used respectively to
`sum up the two outputs 21(k), 22(k) for k= 1,2, .
`. . , Ncp.
`The output signals of the two summers 261, 262 are
`referred to as “statistics” and are denoted by A1, 1:1, 2,
`which are respectively given by:
`
`25
`
`30
`
`Ncp
`A1 = kg: 2100
`M,
`A2 = k: 1 £200
`
`(5)
`
`(6) 35
`
`is the
`Define a statistic A: |A11 —|A2|, where |Az|
`absolute value of A1,]: 1,2. Further define two decision
`bits <11 and d2, where d1 is used to indicate the pulse
`position of each received duty pulse during each Tcp,
`and d215 used to indicate the polarities of duty pulse
`train.
`The following Table-A3 can be used to determined
`the values of d1 and d2 in accordance with received duty 45
`pulse:
` TABLE A3
`Received Duty Pulse
`Decision Bits
`Pulse Position
`Polarity
`(d1, d2)
`PPI
`+1
`(1, 1)
`PP;
`+1
`(— l. 1)
`”’2
`—1
`(—1, —1)
`PP] (l, — 1) —1
`
`
`
`50
`
`55
`
`The decision bit d1 can be determined by the following
`two criteria:
`(1) if A20, then d1=1, and
`(2) if A<0, then d1=— 1.
`These two criteria can be implemented by a comparator 50
`291, which compares the magnitude of the signal A with
`a zero reference voltage. Accordingly,
`if A20, the comparator 291 generates a logic high
`voltage representing a bit “1”; and
`if A<0, the comparator 291 generates a logic low 55
`voltage representing a bit “—- 1”.
`The subsequent step is to determine the decision bit
`d2, i.e., the polarity of the duty pulse train within 2T.
`
`5,446,757
`
`8
`This can be implemented by the arrangement of a sec-
`ond comparator 292 connected via two switches S3 and
`S4 respectively to the output of the two summers 261,
`262. The decision bit d1, which has been already deter-
`mined at this time, is used to control the ON/OFF of
`the two switches S3, S4 in such a way that if d1=1, the
`switch S3 is triggered ON and the switch S4 is triggered
`OFF, thereby causing only the signal A1 to be passed to
`the second comparator 292; and if d1= — l, the switch
`83 is triggered OFF and the switch S4 is triggered ON,
`thereby causing only the signal A2 to be passed to the
`second comparator 292.
`The second comparator 292 compares the input sig-
`nal with a zero reference voltage. If the magnitude of
`the input signal is positive, an output bit “1” is gener-
`ated; and if the magnitude of the input signal is negative,
`an output bit “'— 1” is generated. The output bit of the
`second comparator 292 is taken as the decision bit d2.
`Based on the two decision bits (d1,d2), the bit pattern
`represented by the received Nc duty pulses, denoted
`here'in the receiver portion as
`21, bz+ 1) can be deter-
`mined In accordance with the foregoing two prede—
`fined Table-AZ and Table-A3, a table listing logic rela-
`tionships between (by, b21+1) and (d1, d2) can be ob-
`tained as Table-A4 shown below:
`
` TABLE A4
`
`Decision Bits
`Deciphered Bit Pattern
`(d1, d2)
`(321. 1321+ 1)
`(1, 1)
`(1. 1)
`(—l, 1)
`(1, —1)
`(—1, —1)
`(—1. 1)
`(1, —1)
`(-1, —1)
`
`A logic circuit 295 is devised to implement the logic
`relationships of Table-A4, taking (d1,d2) as the input
`and (b21,b21+1) as the output The design of the logic
`circuit 295'1s an obvious practice to those who skilledin
`the art of logic circuit designs, so that detailed circuit
`diagram thereof will not be illustrated and described.
`Two data bits are thus obtained in parallel, which can
`be subsequently converted to serial bit stream by a par-
`allel-to-serial converter 296. The receiving end thus can
`fetch from the output of the parallel-to-sen'al converter
`296 a serial bit stream which represents the information
`sent by the data source 200.
`EXAMPLE 2
`
`A BPSK—TPP-DS-CDMA System (M=3)
`Referring to FIGS. 7A-7B, there show a BPSK-
`TPP-DS-CDMA (TPP stands for “ternary pulse posi-
`tion”) digital communication system. The transmitter
`portion of the system is shown in FIG. 7A, and the
`receiver portion of the system is shown in FIG. 7B. In
`the subsequent descriptions for the system of FIGS.
`7A—7B, constituting components that are structurally
`and functionally the'same as those used in the system of
`FIGS. 3A—3B will not be described in detail again.
`In FIG. 7A, the data bit stream BS is converted by a
`3-bit serial-to-parallel converter 310 into three parallel
`bit streams BS}, B52, and and B53,
`
`BSI=Cbo, b3, b6, .
`
`.
`
`. ,b31.-~ -)
`
`B52=(bi, 194,137, -
`
`- -
`
`, b31+1. -
`
`- -)
`
`(7)
`
`(8)
`
`Page 000024
`
`Page 000024
`
`

`

`BSa=(b2, b5, b3, .
`
`.
`
`.
`
`9
`, b31+2, . . .)
`
`5,446,757
`(9)
`
`10
`3T, with each duty pulse appearing at the pulse position
`defined as PP; and
`(h) if the 3-bit vector is (— 1, —l, — 1), the duty pulse
`encryptor 321 is triggered to send out a package of NC},
`consecutive negative duty pulses during the bit duration
`3T, with each duty pulse appearing at the pulse position
`defined as PPl.
`The foregoing mapping relationships are summarized
`in the following Table-B2, or they can be schematically
`visualized respectively from the diagrams of FIGS.
`8A—8H.
`
`However, the duration of each bit in B81, B52, and BS3
`is now changed to 3T. Consequently, the 3-bit serial-to-
`parallel converter 310 sends out a sequence of 3-bit
`vectors (by, b31+1, b31+z),l=0,l_,2,, . . . , to the TPP—DS
`modulator 320. Each thus formed 3—bit vector has a bit
`pattern which may be one of the eight possible bit pat-
`terns as listed in the following Table-B1:
`TABLE Bl
`(bsl. b31+1, b31+2)
`(1, 1, 1)
`(1, 1. —1)
`(1, —1. l)
`(1. —1, -1)
`(—1, 1, 1)
`(—1, l, -1)
`(—1, —1, l)
`(—l, —l, --D
`
`Referring to FIGS. 8A—8H, a number Nap, the period of
`the pseudoramdom sequence signal PNpi(t) shown in
`FIGS. 7A—7B, is selected to divide the duration 3T into
`NC}, equal intervals. Each interval has a duration of
`3T/Nq, which is referred to as the chip T5,, of the pseu-
`dorandom sequence signal PNP‘G). Each Tap is divided
`further by four (in general this number is equal to 251— 1)
`into four pulse positions with each pulse position having
`a duration of T;, where T5=Tcp/4. The four pulse posi-
`tions are defined respectively as PP1,PP2,PP3, and PP4.
`A mapping table, which defines the generating of a
`duty pulse train at the output of “Duty Pulse Encryptor
`321” in response to the bit pattern of the 3-bit vector at
`the output of 3-bit S-P converter 310 is predetermined
`to have the following mapping relationships:
`(a) if the 3-bit vector is (1, 1, 1), the duty pulse en-
`cryptor 321 is triggered to send out a package of Nap
`consecutive positive square pulses (these square pulses
`will be hereinafter referred to as “duty pulses”) during
`t