Exhibit IOOS
`
`l|||||||||||||||||||||llllllllll|||l||||||||||||||||l||||||||||||l||||||||l
`usoosmvsm
`
`[191
`United States Patent
`Aug. 29, 1995
`[45] Date of Patent:
`Chang
`
`[11] Patent Number:
`
`5,446,757
`
`[54] OODE-DIVISIONnMULTIPLE-ACCESS-SYS-
`"FEM BASED ON M—ARY PURE-POSITION
`MODULATED DIRECT-SEQUENCE
`
`[76]
`
`Inventor:
`
`Chen-Yi Chang, 1001 Ta Hsueh
`Road, Hsinchu,
`
`{21} Appl. No.: 71,347
`
`[22] Filed:
`
`Jun. 14, 1993
`
`Int. (31.6
`[51]
`H03K 7/04; H043 1/00
`
`[52] US. Cl.
`375x239; IFS/200
`[58] Field of Search
`375/23, 1
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,235,615
`5,329,546
`5,329,547
`
`375x205
`8/1993 Omura
`..
`7X1994- Lee
` 3752’206
`1(19'94 Ling
`
`Primary ExamineMEdward L. Coles, Sr.
`Assistant Examiner—Allan A. Esposo
`
`Attorney, Agent. or Firm—Lades & Parry
`
`ABSTRACT
`[5?]
`A BPSK-MPP-DS-CDMA system is devised using a
`pulse position modulated direct sequence technique.
`Under the same bandwidth, same energy used for one
`decision, and same bit error rate conditions, if the num-
`ber of users is less than the period Nap of the pseudoran-
`dam sequence signal PNflt) used in the BPSK~MPP-
`DS-CDMA system. the multiple access capacities of the
`that)! (Dbl), ternary 01:3}, quaternary 04:4), and
`pentary (M=5) BPSK-MPP-DS-CDMA systems ac,
`cording to the present invention are respectively at least
`2, 5.34, 13.28, and 26.4 times greater than that of the
`conventional BPSK-DS-CDMA systems. On the other
`hand, if the number of users attains Neg, the multiple
`access capacity can not merease an}.r more, however,
`the bit error rate of the system will be reduced. Further-
`more. (M— l)/M transmitting energy is saved.
`
`13 Claims, 19 Drawing Sheets
`
`
`
`Liberty Mutual
`Exhibit 1008
`
`Page 000001
`
`

`

`US. Patent
`
`Aug. 29, 1995
`
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`Page 000002
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`

`

`US. Patent
`
`Aug. 29, 1995
`
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`5,446,757
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`Aug. 29, 1995
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`US. Patent
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`Aug. 29, 1995
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`Aug. 29, 1995
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`US. Patent
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`Aug. 29, 1995
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`Aug. 29, 1995‘
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`Aug. 29, 1995
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`US. Patent
`
`Aug. 29, 1995
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`Sheet 19 of 19
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`5,446,757
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`

`

`1
`
`5,446,757
`
`CODE-DIVISIONwMULTIPLE-ACCESS-SYSTEM
`BASED ON M-ARY PUISE-POSI'HON
`MODULATED DIRECT-SEQUENCE
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates in general to a method
`of data transmission and reception, and more specifi—
`cally, to a method of data transmission and reception
`using code-division-multiple-access
`(CDMA)
`tech-
`nique.
`2. Description of Prior Art
`The Spread-spectrum technique is a technique devel-
`oped since about the mid-£9503. A detailed description
`of the conventional spread-spectrum systems can be
`found in a tutorial entitled “Theory of Spread Spectrum
`Communications—"A Tutorial” authored by Raymond
`L. Pickholtz et a1. and published on IEEE Trans. Com-
`mun., Vol. COM-30, pp. 855-884, May 1982.
`The conventional BPSK (Binary-Phase-Shifi-Key-
`ing) direct sequence spread spectrum communication
`system is shown in FIG.
`lA—IB. A multiple access
`communication system that employs spread spectrum
`technique is technically termed as a code division multi-
`ple access (CDMA) system. The configuration of a
`basic CDMA system is shown in FIG. 2. A more detail
`description of the conventional BPSK-DS-SS (or
`BPSK-DS-CDMA) system of FIG. 1 will be given in
`the paragraphs under the header “Performance Evalua-
`tions.”
`The CDMA technique was developed mainly for
`capacity reasons. Ever since the analog cellular system
`started to face its capacity limitation in 1987, research
`efforts have been conducted on improving the capacity
`of digital cellular systems. In digital systems, there are
`three basic multiple access schema: frequency division
`multiple access (FDMA), time division multiple access
`(TDMA), and code division multiple access (CDMA).
`In theory, it does not matter whether the channel is
`divided into frequency bands, time slots, or codes; the
`capacities provided from these three multiple access
`schemes are the same. However, in cellular systems, we
`might find that one scheme may be better than the
`other.
`A list of technical references pertinent to the subject
`matter of the present invention is given below:
`[1] “Overview of Cellular CDMA”, by William C. Y.
`Lee, IEEE Trans. Veh. Tech, Vol. 40, No. 2, pp.
`291-302, May 1991.
`[2] “0n the Capacity of 3 Cellular CDMA System”,
`by A. J. Viterbi, L. A. Weaver, and C. E. Wheatley 111,
`IEEE Trans. Veh. Tech, Vol. 40, No. 2, pp. 303-312,
`May 1991.
`[3]“A Statistical Analysis of Ont-off Patterns in 16
`Conversations”, by P. T. Brady, Bel] Syst. Tech. 1.,
`Vol. 47, pp. 73—91, Jan. 1968.
`[4]“Coherent Spread Spectrum Systems”, by .T. K.
`Holmes, John Wiley and Sons, New York, pp. 388—339,
`1982.
`[5] “Error Probability of Asynchronous Spread Spec-
`trum Multiple Access Communications Systems”, by K.
`Yao,
`IEEE Trans. Commum. Vol. COM-25, pp.
`803—307, 1977.
`[6] “Direct-Sequence Spread Spectrum Multiple-
`Aooess Communications with Random Signature Se-
`quences: Large Deviations Analysis”, by J. S. Sa-
`
`10
`
`15
`
`35
`
`45
`
`55
`
`2
`dowsky and R. K. Baht", IEEE Trans. Inform. Theory
`Vol. 37, No. 3, pp. 514-527, May 1991.
`[7} “Digital Communications and Spread Spectrum
`Systems”, by R. E. Ziemer and R. 1.. Peterson, Macmil-
`lan, New York, Ch. 11, 1985.
`{8] “Spread Spectrum Multiple Access Communica-
`tions, Maid-User communication Systems”, by M. B.
`Parsley, edited by G. Longo, Spfinger—Verlag. NY. pp.
`139-199, 1981.
`[9]
`“Performance Evaluation for PhaseCoded
`Spread-Spectrum Multiple-Access Communication—
`Part II: Code Sequence Analysis”, by M. B. Parsley and
`D. V. Sarwate, IEEE Trans. Commurt, Vol. Com-25,
`No. 3, pp. 800-803, August 19??.
`Remarkable results have been derived in the pertinent
`reference [2], “0n the Capacity of 3 Cellular CDMA
`System” by A. J. Viterbi et at. This technical paper
`shows that the net improvement in the capacity of
`CDMA systems is four to six times better than that of a
`digital 'I'DMA or FDMA system, and nearly 20 times
`better than that of current analog FMIFDMA system.
`Therefore, the CDMA scheme may become a major
`system in future communication systems
`The reason for the improvement in the multiple ac-
`cess capacity of the CDMA system mentioned above is
`that the capacity of the CDMA system is inversely
`proportional to cross-correlation noise, which is influ-
`enced or can be reduced by: (1) voice activity with a
`duty factor of approximately 3; and (2) spatial isolation
`through use of meld-beamed or multi-sectored anten-
`nas. Therefore if we can find another factor which can
`reduce the cross—correlation noise, the multiple access
`capacity will increase correSpondingly.
`SUMMARY OF THE INVENTION
`
`A primary object of the present invention is to pro-
`Vidc a CDMA system by which the multiple access
`capacity is increased and the transmitting energy is
`decreased compared to the conventional BPSK-DS-
`CDMA system.
`In accordance with the above objects, a. code division
`multiple access (CDMA) system based on M-ary pulse
`position modulated direct sequence is provided. This
`system is called a BPSK-MPP—DS-CDMA (Binary-
`Pbase-Shift-Keyed M-ary Pulse-Positiou—Modulated-
`Direct-Sequence} system. The data source in this sys-
`tem sends out a sequence of data bits with bit duration
`T. According to the present invention the system first
`converts the serial binary data stream into M parallel bit
`sequences. These M parallel bit sequences can thus be
`considered as a. sequence of M—bit vectors with each bit
`having a duration of MT. A number Nap, which is the
`period of a pseudorandom process PNAt), is selected to
`divide each MT duration into Na, intervals with every
`interval having a duration Tcp, where T¢p=MTIqu
`Each interval T4, is further divided into 2“—1 pulse
`positions, each pulse position having a duration T5,
`T5=Tcpl2M—l. Each M-bit vector is converted into a
`corresonding block of NW duty pulses in every interval
`MT, with each duty pulse set in accordance with a
`predetermined mapping table to appear in one of the
`234—1 pulse positions and with a certain polarity. This
`duty pulse train is then modulated with a sample PNP'It)
`of the pseudorandom process PNP(t). The modulated
`signal is modulated further by a carrier signal and then
`is transmitted over the channel of the connnunication
`system.
`
`Page 000021
`
`

`

`3
`In the receiving end of the communication system,
`the received signal is demodulated synchronously by
`the carrier signal and the pseudorandom sequence sig-
`nal PNpifi) to recover each duty pulse block during a
`duration MT. The pulse position and the polarity of the
`N5], pulses in each received duty pulse block are deter-
`mined and are used to find the bit pattern represented
`by each received duty pulse block by using the prede-
`termined mapping table in a. reverse manner. In this
`way, a vector of M parallel data bits are recovered
`during this duration MT.
`Under the condition that the energy used for one
`decision (this energy will be defined in the paragraphs
`under the header “Performance Evaluations”) in all
`concerned systems
`is equal,
`the BPSK-MPP—DS—
`CDMA system according to the present invention has
`three improved characteristics over the conventional
`BPSK—DS-CDMA system. These improved character-
`istics include reduction of cross-correlation noise, an
`increase in multiple access capacity, and reduction of
`transmitting energy.
`'
`The cross-correlation noise is reduced by a factor of
`4 if the system is based on M=2; 12 if the system is
`based on M=3, 32 if the system is based on M=4, and
`80 if the system is based on M=S. If the multiple access
`capacity is not limited by the period N99 of the pseudo-
`random sequence signal PNPKt), then under the same
`bandwidth and same bit error rate constraints, the mul-
`tiple access capacity is improved by a factor at least of
`2 if the system is based on M=2; 5.34 if the system is
`based on M=3; 13.28 if the system is based on M24;
`and 26.4 if the system is based on M=5. Conversely, if
`the multiple access capacity is limited by qu, that is
`after the number of users attain th, the extra reduction
`in cross-correlation noise can reduce the bit error rate
`of the system.
`For a general M-ary system, the tramsmitting energy
`is only UM of that in the conventional system, i.e.,
`(M— DIM of the transmitting ‘energy is saved. The
`proofs of these results will be given in the performance
`evaluation of the prefered embodiment section.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention can be more fully understood
`by reading the subsequent detailed description of the
`preferred embodiments thereof with references made to
`the accompanying drawings, wherein:
`For the Conventional BPSK—DS-SS System:
`FIG. 1A shows the block diagram ofa transmitter for
`the conventional BPSK direct sequence spread Spec-
`trum system;
`FIG. 13 shows the block diagram of a receiver for
`the conventional BPSK direct sequence spread spec-
`trum system;
`FIG. 2 shows a basic CDMA communication system
`model;
`For the BPSK—BPP—DS—CDMA System:
`FIG. 3A shove the block diagram of a BPSK-BPP—
`DS-CDMA transmitter devised in accordance with the
`present invention;
`FIG. SB shows the block diagram of a BPSK-BPP—
`DS—CDMA receiver devised in accordance with the
`present invention;
`FIGS. ILA—41) are four waveform patterns, showing
`the encrypted duty pulse trains generated reapectively
`in response to the bit patterns of four different 2-bit
`vectors;
`
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`
`4
`FIG. 5A shows the waveform of an example of a
`train of encrypted duty pulses;
`FIG. SB shows an example of a pseudorandom se-
`quence signal used to modulate the pulse train of FIG.
`5A;
`FIGS. 6A-6B show the waveforms of two control
`pulse trains used respectively to control the {IN/OFF
`mode of a pair of switches in the receiver of FIG. 313;
`For the BPSK-TPP-DS-CDMA System:
`FIG. 7A shows the block diagram of a BPSK—TPP—
`DS-CDMA transmitter devised in accordance with the
`present invention;
`FIG. 78 shows the block diagram of a BPSK-TPP—
`DS-CDMA receiver devised in accordance with the
`present invention;
`FIGS. BA-SH are eight waveform diagrams, show-
`ing the encrypted duty pulse trains generated reaper:-
`tively in response to the bit patterns of eight different
`3—bit. vectors;
`FIG. 9A shows the waveform of an example of a
`train of encrypted duty pulses;
`FIG. 9B shows an example of a pseudorandom se—
`quence signal used to modulate the pulse train of FIG.
`9A;
`FIGS. lOA—IOD show the timing diagrams of four
`control pulse trains used respectively to control the
`ON/OFF mode of an array of four switches in the
`receiver of FIG. TB;
`FIG. 11 shows the block diagram of a modified
`BPSK-TPP—DS-CDMA receiver devised in accor-
`dance with the present invention;
`FIGS. 12A—12F Show the waveforms of six control
`pulse trains used respeCtively to control the ON/OFF
`mode of the switches 811, 513, 831, 832, 523, and 524 in
`the receiver of FIG. 11;
`For the BPSK—MPP-DS-CDMA System:
`FIG. 13A shows the block diagram of a generalized
`BPSK—MPP—DS-CDMA transmitter devised in accor-
`dance with thc present invention;
`FIG. 13B shows the block diagram of a generalized
`BPSK-MZPP-DS-CDMA receiver devised in accor-
`dance with the present invention; and
`FIGS. 14A—14B are diagrams used to depict how
`pulse positions are formed in a generalized M-ary sys-
`tern;
`FIG. 15 shows the block diagram of a modified
`BPSK-MPP-DSCDMA receiver devised in accor—
`dance with the present invention;
`For Performance Evaluations:
`FIGS. 16A—JGB show a set of typical cross-cor-
`related mveforms of PNcij(t—6)PNc1‘It) for M=3.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`The present invention relate; to a spread spectrum
`transmission and reception system based on an Mary
`pulse position modulated direct sequence. In the follow—
`ing detailed descriptions, exmnples will be given for the
`cases of M=2 and M=3. Finally, a generalized BPSK—
`MPP-DS-CDMA system is described.
`EXAMPLE 1
`
`A BPSK-BPP-DS-CDMA System (M=2)
`Referring to FIGS. 3A—SB, there show a BPSK—
`BPP-DS—CDMA (binary—phase
`shift-keyed binary-
`pulse—position modulated direct-sequence code-divi-
`sion-multiple-access) system devised in accordance
`
`Page 000022
`
`

`

`5,446,757
`
`5
`with the prmnt invention. The transmitter portion of
`the system is shown in FIG. 3A and the receiver portion
`of the system is shown in FIG. 3B.
`The transmitter portion of the system, which is used
`to transmit binary signals from a data source 200 to a 5
`communication channel,
`includes a serial-to-parallel
`converter 210, a BPP-DS modulator 220, and a carrier
`modulator 230. The BPP—DS modulator 220 consists of
`a duty pulse encryptor 221 and a pulse modulator 222.
`In practice, a data bit “1" is transformed into a posi- 10
`tive square pulse with a duration of T and a data bit
`“—1” is transformed into a negative square pulse also
`with a duration of T at the output of the data source
`200. When a data bit stream BS=(bo. b1, b1, . . . , bn_1.
`.
`. ) is sent out from the data source 200 with a bit dura— '5
`tion ofT and is to be transmitted over the communica-
`tion channel, the data bit stream BS is first converted by
`the serial-to-parallel converter 210 into two parallel bit
`streamsBSlandB52,BSJ=(bo, bub-t, ...,bzl.---)311d
`BSz=(b], b3, b5, . . . b2“. 1,
`.
`. . }. However, the duration 20
`of each bit in BS: and 382 is 2T. Consequently, the 2-bit
`serial-to-parallel converter 210 sends out a sequence of
`2-bit vectors (bu, b2;+ 1), ] =0,1,2,, . .
`. , to the BPP-DS
`modulator 220. Each thus formed 2-bit vector has a bit
`
`6
`square pulse appearing at the pulse position defined as
`“PPz”; and
`(d) if the input 2-bit vector is (— l, — l), the duty pulse
`encryptor 221 sends out a package of Nap consecutive
`negative square pulses during the period 2T with each
`square pulse appearing at the pulse position defined as
`“PPI.” .
`The foregoing mapping relationships are summarized
`in the following Table-A2. They can also be schemati-
`cally visualized respectively from the diagrams of
`FIGS. 4A4D.
`
`Bit Pattern
`(132:. sz'+ a}
`(l. 1)
`(I. —1)
`(— 1’ 1}
`(— l. ul)
`
`TABLE A2
`encrypged Duty Pulse
`Pulse Position
`Polarity
`PP;
`+1
`PP;
`+1
`PP;
`— l
`PP}
`-l
`
`The square pulse in each chip Top is termed as a “duty
`pulse.” Only one duty pulse will be present in firth chip
`T”. For example, if the leading eight hits in the bit
`stream BS are (l. —l, —1, --l, —l, 1,1, 1), then the
`duty pulse encryptor 221 will send out a. corresponding
`signal x1(t) as illustrated in FIG. 5A. The thus formed
`signal aid.) is subsequently modulated by the pseudoran-
`dom sequence signal PNflt). The timing relationship
`between x;(t) and PNP'It) can be seen from FIGS.
`SA—SB. The pseudorandom sequence signal PNPI'G)
`contains Ne}, consecutive pseudorandom bits with each
`bit having a duration of Tag. The signal and) at the
`output of pulse modulator 222 is
`
`:29) =XltllPNpiU)»
`
`(l)
`
`which is subsequently modulated at the carrier modula-
`tor 230 by a sinusoidal signal qua/E sin(oot) to
`obtain a modulated signal X3(t) and thereby transmitted
`through the communication channel to its destination.
`Referring back to FIG. 3B, the transmitted signal is
`picked up by the receiver portion of the system located
`at the receiving end of the channel. For noise flee situa-
`tion, the received signal is y 1(t) =A.xa(t—'n), where “A"
`is the amplitude of y1(t), and riis the transmission delay
`of 1:30.). The signal y1(t) is demodulated by multiplying
`it with a sinusoidal signal C(z—sgzv’i sin (unfit—"r3,
`where 9,- is the estimate of 17. Since the purpose ofthis
`description is only to demonstrate the operation of the
`system. A=l and i1=rr=0 can be assumed without the
`loss of generality. The demodulated signal y2(t) is then
`multiplied by a local pseudorandom sequence signal
`Ppr{t—rg). which should be in synchronization with
`the received PNFiIZt—i'fl. The waveform of the signal
`y3(t) would be identical to 2:16) in FIG. 3A if no noise
`interference were present in the channel. However, no
`noise interference isonly an ideal candidon and in prac-
`tice the signal y3(t) may be expressed as:
`
`n(0=X1(13+f(!)+fl(f).
`
`(2)
`
`where 1(t) is the cross-correlation noise, and n(t) is the
`white noise.
`A pair of switches S: and 52, with ON/OFF mode
`thereof being controlled respectively by a first pulse
`train CP1(t} and a second pulse train CP3(tJ, are con-
`nected in parallel to the output of the pulse-demodula-
`tor 232. The waveforms of the two pulse trains CP1(t)
`
`Page 000023
`
`pattern which may be one of the four possible bit pat- 25
`terns as listed in the following Table-A1:
`TABLE Al
`
`(lot. by“)
`(1; 1)
`(1. —1}
`(—1. 1)
`(-1. - 1)
`
`30
`
`In the BPP—DS modulator 220, each 2-bit vector is as
`processed firstly by the duty-pulsa-encryptor 221 and
`then modulated in the pulse modulator 222 with a pseu—
`dorandom sequence signal PNflt). In the present inven-
`tion, a number Nap, the period of the pseudorandom
`sequence signal PNp'It). is used to divide the bit dura- 40
`tion 2T into Nap equal intervals with each interval thus
`having a duration of 2T/Ncp. The duration 21‘!qu is
`called the chip Tc}, of the pseudorandom sequence signal
`PNFEQ). Each chip T99 is divided into two pulse posi-
`tions (in general the number of pulse positions divided is 45
`equal to 2”“ for M-ary system). The duration of each
`pulse position is Ts, T;=T¢p/2. The two pulse positions
`within each Tc? are defined as “PPI” and “PH”, respec«
`tively.
`The duty pulse encryptor 221 includes a built-in one- 50
`tocne mapping table defining the generating of a duty
`puls: train in reaponse to the bit pattern of a 2-bit vector
`(132.621.;— 1). The preferred embodiment of the present
`invention incorporates a mapping table having the fol-
`lowing mapping relationships:
`(n) if the input 2-bit vector is (l, I), the duty pulse
`encryptor 22! sends out a package of NC; consecutive
`positive square pulses during the interval 2T with each
`square pulse appearing at the pulse position defined as
`"PP1";
`(b) if the input 2-bit vector is (1,——1), the duty pulse
`encryptor 221 sends out a package of Nag consecutive
`positive square pulses during the interval 21" with each
`square pulse appearing at the pulse position defined as
`“PPg”;
`(c) if the input 2-bit vector is (— 1, 1), the duty pulse
`encryptor 221 sends out a paclmge of NC, consecutive
`negative square pulses during the interval 2T with each
`
`55
`
`to
`
`65
`
`

`

`7
`and CP2(t) are shown in FIGS. 6A—6B. Each of the two
`pulse trains CPujt) and (21320) is a periodic pulse train
`having pulse duration T, and period exactly equal to
`Top, where Tszgp/z The appearance of one square
`pulse in the pulse train CP1(t) will actuate the switch S]
`to be turned 0N; and the appearing of one square pulse
`in the pulse train CP2(t) will actuate the switch 8; to be
`turned ON. A pair of matched filters 241 and 242
`(which are integrate-and-dump circuits for the present
`invention) are connected respectively to the switches
`31 and 52 so that
`the signals passing through the
`switches 51 and $2, denoted by yxl(t) and yyflt), are
`processed by the matched filters 241, 242 and sampled
`by a pair of samplers 251, 252. The outputs of the sam-
`plers 251, and 252 are denoted by zfik) and 220:), which
`are respectively given by:
`
`1
`210‘) = T
`
`His
`(k - 1)}?
`
`ysiirld't
`
`x2“)
`
`= -
`I I0: + 1):;
`1"
`RT:
`
`m
`
`(£de
`
`{3)
`
`(4)
`
`, Nap
`.
`.
`where k=1,2, .
`A pair of summers 261, 262 are used respectively to
`sum up the two outputs 2100, 32(k) for k: 1,2, .
`.
`. , N”.
`The output signals of the two summers 261, 262 are
`referred to as “statistics” and are denoted by Ar, 1:], 2,
`which are respectively given by:
`Non
`A1 = kit 210‘)
`
`(5)
`
`5,446,757
`
`8
`This can be implemented by the arrangement of a sec-
`ond comparator 292 connected via two switches 33 and
`54 respectively to the output of the two summers 261,
`262. The decision bit d1, which has been already deter—
`mined at this time, is used to control the ON/OFF of
`the two switches 83, S4 in such a way that if d: = 1, the
`switch 53 is triggered 0N and the switch 84 is triggered
`OFF, thereby causing only the signal A; to be passed to
`the second comparator 292; and if d1: -— l, the switch
`83 is triggered OFF and the switch S4 is triggered ON,
`thereby causing only the signal A; to be passed to the
`second comparator 292.
`The second comparator 292 compares the input sig-
`nal with a zero reference voltage. If the magnitude of
`the input signal is positive, an output bit “1” is gener—
`ated; and if the magnitude of the input signal is negative,
`an output bit “4- l" is generated. The output bit of the
`second comparator 292 is taken as the decision bit d2.
`Based on the two decision bits (611432), the bit pattern
`represented by the received N: duty pulses, denoted
`here in the receiver portion as
`2:, b1+ 1), can be deter-
`mined. In accordance with the foregoing two prede-
`fined Table-AZ and Table-A3, a table listing logic rela-
`tionships between (Bag, by“) and (d1, d2) can be ob-
`tained as Table-A4 shown below:
`
`TABLE A4
`Decision Bits
`Deciphered Bit Patten-i
`(d1. d2)
`(52:. 32a 1)
`(I. l)
`(1. 1)
`(—1, l)
`(1. -13
`(—1. 1)
`(—1, —1J
`(—1. —l)
`(1. -l)
`
`5
`
`10
`
`is
`
`25
`
`30
`
`A—
`It
`7.0;:
`klZE'Il
`2
`
`(6}
`
`35
`
`is the
`Define a statistic A=|All—|A2|, where |Ag|
`absolute value of A;,1= 1,2. Further define two decision
`bits (11 and d2, where d: is used to indicate the pulse
`position of each received duty pulse during each Tap,
`and d; is used to indicate the polarities of duty pulse
`traJJ’l.
`
`The following Table—A3 can be used to determined
`the values old} and d: in accordance with received duty
`pulse:
` TABLE A3
`Received Duty Pulse
`Decision Bits
`Pulse Position
`Polarity
`(ch. dz)
`PP.
`+1
`(1- 1)
`FF:
`+1
`(wl. 1}
`PP:
`-1
`(— 1. — 1)
`_1PP] (1, —1}
`
`
`
`The decision bit :11 can be determined by the following
`two criteria:
`(1) if A30, then d1=l, and
`(2) ifA<0, then d1=—1.
`These two criteria can be implemented by a comparator
`291, which compares the magnitude of the signal A with
`a zero reference voltage. Accordingly,
`if A20, the comparator 291 generates a logic high
`voltage representing a bit “1”; and
`if A<O, the comparator 291 generates a logic low
`voltage representing a bit “— I".
`The subsequent step is to determine the decision bit
`d2, i.e., the polarity of the duty pulse train within 21‘.
`
`40
`
`45
`
`55
`
`60
`
`65
`
`A logic circuit 295 is devised to implmnent the logic
`relationships of Table-A4, taking (d1,d2) as the input
`and {Swamp as the output. The design of the logic
`circuit 295 is an obvious practice to those who skilled in
`the art of logic circuit designs, so that detailed circuit
`diagram thereof will not be illustrated and described.
`Two data bits are thus obtained in parallel, which can
`be subsequently converted to serial bit stream by a par-
`allel-to-serial converter 296. The receiving end thus can
`fetch from the output of the parallel-to-serial converter
`296 a serial bit stream which represents the information
`sent by the data source 200.
`EXAMPLE 2
`
`A BPSK—TPP—DS—CDMA System (M=3}
`Referring to FIGS. 7A—7B, there show a BPSK-
`TPP-DS-CDMA (1?? stands for “ternary pulse posi-
`tion") digital communication system. The transmitter
`portion of the system is shown in FIG. 7A, and the
`receiver portion of the system is shown in FIG. 7B. In
`the subsequent descriptions for the system of FIGS.
`“LA-7B, constituting components that are structurally
`and functionally the'same as those used in the system of
`FIGS. 3A~SB will not be described in detail again.
`In FIG. 7A, the data. bit stream BS is converted by a.
`3-bit serial-to-parallel converter 310 into three parallel
`bit streams B81, 382, and and B53,
`
`BSI=Mbs,bfi....,b31,...)
`
`352=(bi.b.t.b1,-u.b3!+1w--)
`
`U]
`
`(3)
`
`Page 000024
`
`

`

`353462. hi. he. .
`
`-
`
`9
`. .b3i+2. -
`
`- .)
`
`5,446,757
`
`(9)
`
`10
`3T, with each duty pulse appearing at the pulse position
`defined as PP;; and
`(h) if the 3-bit vector is (— 1, —l, — l}, the duty pulse
`encryptor 321 is triggered to send out a package of Ncp
`consecutive negative duty pulses during the bit duration
`3T, with each duty pulse appearing at the pulse position
`defined as PP1.
`The foregoing mapping relationships are summarized
`in the following Table-32, or they can be schematically
`visualized reSpectively from the diagrams of FIGS.
`sA—BH.
`
`TABLE 32
`
`MP
`
`—— 1
`
`—— I
`
`Bit Pattern
`(his hm i. bit-+1)
`(1. 1, 1)
`(1, 1. —1)
`(1, —1. 1)
`(I. —l, —1)
`(—l. 1. 1)
`(—1. 1, —1)
`{—1, —1, 1)
`(~I. —1. ~1)
`
`ulse Position
`PP]
`PP:
`PP;
`PP;
`”’4
`PP:
`PP:
`PP}
`
`Table-B2 only shows a preferred example of the map-
`ping relationships. Each bit pattern can be in fact as-
`signed by a one-to-one mapping relationship to any of
`the eight possible duty—pulse—train patterns within each
`duration 3T. Therefore, there can be arranged a total of
`8!:40320 mapping tables so that it would be difficult
`for eavesdmppers to decipher the encrypted duty
`pulses.
`If the leading twelve bits in the bit stream BS is 1— 1 1,
`—1—1—1, 1—1—1, 111, thentheduty pulse encryptor
`321 will send out a corresponding signal x1(t) of duty
`pulse train as illustrated in FIG. 9A. The thus formed
`duty pulse train x1(t) is then modulated in the pulse
`modulator 322 with a pseudorandom sequence signal
`myth) which has period Na, and chip 1",, The timing
`relationship between x1(t) and PNP‘G) can be seen from
`FIGS.
`9A—93.
`The
`resultant
`signal
`x20).
`m(t)=x1(t}PNpi(t), is then modulated further by a sinu-
`soidal signal C(t)= V3P/35intwat) and the modulated
`signal x3(t) is transmitted through the communication
`channel to its destination.
`Referring back to FIG. 713, the receiver of the system
`includes an array of four switches S1, 32, 53, 34., which
`are coupled respectively in subsequence with an array
`of four matched filters 34], 342, 343, 344, an array of
`four satuplers 351, 352, 353, 354, and an array of four
`summers 361, 362, 363, 364. The ONXOFF modes of the
`four switches S1, 32, 83, 54 are respectively controlled
`by
`four
`control
`pulse
`sequences
`CP1(t),CP2(t),CP3(t),€IPa(t)
`having waveforms illus-
`trated in FIGS. 10A-10D. The appearance of each
`square pulse in the four control sequences is used to
`trigger ON the associated switch such that:
`during the duration of pulse position
`S] =ON and Sg=S§=Sa=OFF;
`during the duration of pulse position
`Sz=ON and 81:83=&=0FF;
`during the duration of pulse position
`$3=ON and S1=Sana=OFF;
`during the duration of pulse position
`S4=ON and SI,=Sz=Sa=OFF.
`The signals passing the switches Si, 82, $3, or 3:.
`denoted respectively by YnCt). yea}, y53flt}, yyujt), are
`processed by the matched filters 341, 342, 343, 344 in
`
`P132,
`
`PP},
`
`P134,
`
`PE, only
`
`Page 000025
`
`However, the duration of each bit in 1381, 882, and B83
`is now changed to 3T. Consequently, the 3-bit serial-to-
`paralle] converter 310 sends out a sequence of 13-bit 5
`vectors {b3}, b3f+1, b3;+1),1 =0, 1,2,, . . . , to the TPP-DS
`modulator 320. Each thus formed S-bit vector has a bit
`pattern which may be one of the eight possible bit pat-
`terns as listed in the following Table-B1:
`TABLE Bl
`(has b.u+ I: b3r+2l
`(1. l. 1)
`(l, l. —1)
`(I, —1. l}
`(1. —