Case 3:13-cv-00579-MO Document 302 Filed 03/06/14 Page 1 of 3
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`UNITED STATES DISTRICT COURT
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`DISTRICT OF OREGON
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`PORTLAND DIVISION
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`Case No. 3:10-cv-954-MO (lead)
`Case No. 3:12-cv-1500-MO
`Case No. 3:13-cv-579-MO
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`OPINION AND ORDER
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`MENTOR GRAPHICS CORPORATION,
`an Oregon Corporation,
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`
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`Plaintiff/Counter-defendant,
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`v.
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`
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`EVE-USA, INC., a Delaware corporation; and
`SYNOPSYS EMULATION AND
`VERIFICATION S.A., formed under the laws
`of France,
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`
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`
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`Defendants/Counter-claimants.
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`SYNOPSYS, INC., a Delaware corporation;
`EVE-USA, INC., a Delaware corporation; and
`SYNOPSYS EMULATION AND
`VERIFICATION S.A., formed under the laws
`of France,
`
`
`
`Plaintiffs/Counter-defendants
`
`v.
`
`
`
`
`
`
`MENTOR GRAPHICS CORPORATION,
`an Oregon corporation,
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`
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`Defendant/Counter-claimant.
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`1 – OPINION AND ORDER
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`

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`Case 3:13-cv-00579-MO Document 302 Filed 03/06/14 Page 2 of 3
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`MOSMAN, J.,
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`On February 24, 2014, I held a claim construction hearing in the above-entitled patent
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`actions. At issue were claim terms appearing in U.S. Patent Nos. 7,069,526 (“’526 patent”),
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`6,240,376 (“’376 patent”), 5,649,176 (“’176 patent”), 6,009,531 (“’531 patent), and 6,947,882
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`(“’882 patent”). In this Order, I announce my constructions of the following terms:
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`Claim Term
`’526 Patent
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`design visibility
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`design patching
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`design control
`instrumentation
`circuitry
`aspect
`integrated circuit
`product
`’376 Patent
`gate-level netlist
`gate-level design
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`instrumentation signal
`simulating a gate-level
`design
`sensitivity list
`process
`generating logic
`’176 and ’531 Patents
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`logic system
`configurable logic
`system
`
`environment
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`Construction
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`“monitoring the entire or partial state of the DUT at, and relative to,
`predetermined events”
`“altering the behavior of the DUT to a predetermined particular
`desired state at predetermined events”
`“methods to specify the events that control design visibility and design
`patching”
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`“additional circuitry to facilitate debugging”
`“portion”
`“one or more manufactured or configured chips that implement a
`design in the target technology”
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`“a list of gates and their inputs, outputs, and interconnects”
`“a list of gates and their inputs, outputs, and interconnects”
`“output signal added or preserved during logic synthesis that indicates
`whether a corresponding RTL source code statement is active”
`“modeling the operation of a gate level design using software and/or
`hardware”
`“a list of signals to which a process is responsive”
`“a description of the behavior of some portion of a circuit design”
`“generating gates”
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`“a system including one or more configurable logic devices into which
`the circuit design under test is configured”
`“a system including one or more configurable logic devices into which
`the circuit design under test is configured”
`“a real or simulated system or circuit, external to the configurable
`logic system, in which the circuit design under test is intended to
`operate”
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`2 – OPINION AND ORDER
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`

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`Case 3:13-cv-00579-MO Document 302 Filed 03/06/14 Page 3 of 3
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`environmental timing
`signal
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`internal clock signal
`’882 Patent
`reconfigurable logic
`device
`first plurality of
`reconfigurable logic
`devices
`second plurality of
`reconfigurable logic
`devices
`third plurality of
`reconfigurable logic
`devices
`interconnect device
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`time multiplexed
`interconnection
`“independent”
`clocking
`circuit design
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`emulation system
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`emulator
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`“a timing signal, originating from the environment and received by the
`logic system, with a frequency that is lower than the internal clock
`frequency”
`“a signal existing within the configurable logic system and invisible to
`the environment that provides a time base for scheduling the operation
`of the resynthesized circuit”
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`“chip that includes a plurality of reconfigurable logic elements and
`input/output circuitry”
`“two or more reconfigurable logic devices, none of which are included
`in the second plurality of reconfigurable logic devices or the third
`plurality of reconfigurable logic devices”
`“two or more reconfigurable logic devices, none of which are included
`in the first plurality of reconfigurable logic devices or the third
`plurality of reconfigurable logic devices”
`“two or more reconfigurable logic devices, none of which are included
`in the first plurality of reconfigurable logic devices or the second
`plurality of reconfigurable logic devices”
`This term no longer appears in any patent claim at issue.
`“structure capable of receiving data from each reconfigurable logic
`device in one plurality and transmitting the data to each reconfigurable
`logic device in another plurality”
`“wherein there is no required timing relationship between clock
`edges”1
`“a design for an integrated circuit”
`“a system capable of reproducing the operation of a circuit design
`through steps including mapping the circuit design onto hardware”
`“a system capable of reproducing the operation of a circuit design
`through steps including mapping the circuit design onto hardware”
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`IT IS SO ORDERED.
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`DATED this 6th day of March, 2014.
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`
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`/s/ Michael W. Mosman
`MICHAEL W. MOSMAN
`United States District Judge
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`1 I remain uncertain as to whether the construction of this term should include further language referring specifically
`to the structures recited in claims 1 and 5 of the ’882 patent. I invite the parties to submit any comments on this
`question by way of an email to my courtroom deputy clerk before the end of business on Friday, March 14, 2014.
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`3 – OPINION AND ORDER