APPENDIX A
`APPENDIX A
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`

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`8300541
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`TOALLTOWHOMTHESE’ PRESENTS) SHALL, COME:
`UNITED STATES DEPARTMENT OF COMMERCE
`
`United States Patent and Trademark Office
`
`October 3, 2022
`
`THIS IS TO CERTIFY THAT ANNEXEDIS A TRUE COPY FROM THE
`RECORDS OF THIS OFFICE OF THE FILE WRAPPER AND CONTENTS
`
`k
`| e
`
`APPLICATION NUMBER:16/991,107
`
`FILING DATE: November 17, 2004
`
`PATENT NUMBER:7,396,760
`
`ISSUE DATE: July 8, 2008
`
`
`
`
`By Authority of the
`UnderSecretary of Commerce for Intellectual Property
`and Director of the United States Patent and Trademark Office
`
`Mahon ’
`
`Certifying Offic
`
`
`
`
`
`
`rf
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`es
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`

`

`v
`
`sea) .
`
`ATTORNEY DOCKETN®: 04-0800
`S EXPRESS MAIL LABEL N2: EV 515 455 948 US
`-
`-o
`o ”
`ORIGINAL PATENT APPLICATION TRANSMITTAL LETTER
`
`COMMISSIONER FOR PATENTS
`P.O. BOX 1450
`ALEXANDRIA,VA 22313-1450
`
`Transmitted herewith forfiling is the patent applicationof:
`
`INVENTORS:
`Kunal N. Taravade
`15539 SE Knapp Drive
`Portland, OR 97236
`Citizen of United States
`
`Neal Callan
`455 Furnace Street
`Lake Oswego, OR 97034
`Citizen of United States
`
`Paul Filseth
`230 Jensen Springs Road
`Los Gatos, CA 95033
`Citizen of United States
`
`PATENT
`
`Oo
`als
`aor
`a
`>
`zS
`qr
`
`N
`
`Title: Method and System for Reducing Inter-Layer Capacitance in Integrated Circuits
`
`CERTIFICATION UNDER37 C.F.R. §1.10
`
`[herebycertify that this Original Application Transmittal and the documents referred to as enclosed
`therein are being deposited with the United States Postal Service on this date, November 17, 2004 in
`an envelopeas "Express Mail Post Office to Addressee", Mailing Label N° EV 515 455 948 US,with
`sufficient postage, addressed to: Commissionerfor Patents, P.O. Box 1450, Alexandria, VA 22313-
`1450.
`
`
`N)
`
`At
`
`ReNea D. Berggren
`
`
`
`DATED: November 17, 2004
`
`1.
`
`Type of Application
`
`This is an Original Application.
`
`2.
`
`Benefit of Prior U.S. Application(s) (35 U.S.C. §)
`
`USSN
`
`Filing Date
`
`Inventor(s)
`
`Status
`
`

`

`3.
`
`Papers Enclosed That Are Required for Filing Date under 37 C.F.R. §1.53(b) (Regular)
`or 37 C.F.R. §1.153 (Design) Application
`
`Ten (10) Pages of Specification;
`Seven (7) Pages of Claims,
`
`One(1) Page of Abstract; and
`
`Five (5) Sheets of Drawing Figures.
`
`Additional Papers Enclosed
`
`Information Disclosure Statementis attached.
`
`Declaration or Oath
`Thesigned Declarationand Powerof Attorneyis attached.
`
`Inventorship Statement
`The inventorship forall the claimsin this application are the same.
`
`Language
`
`English.
`
`Assignment
`The signed Assignmentis attached. The Recordation Form Cover Sheet is enclosed.
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`Certified Copy
`
`Noneare required.
`
`10.‘
`
`Fee Calculation (37 C.F.R. §1.16)
`
`BASIC FEE
`
`EXCESS CLAIM FEE
`
`TOTAL OVER TWENTY
`
`INDEPENDENT OVER THREE
`
`25
`
`3
`
`-20
`
`=
`
`30°
`
`MULTIPLE DEPENDENT
`ASSIGNMENT RECORDATION FEE
`TOTAL FILING FEES
`
`0
`
`0
`
`$300.00
`$0.00
`$40.00 $40.00 _
`$920.00
`
`$790.00
`
`$90.00
`
`$0.00
`
`5 X $18.00
`
`$88.00
`
`

`

`11.
`
`Small Entity Statement(s)
`
`12.
`
`13.
`
`Nonerequired.
`Request for International - Type Search (37 C.F.R. §1.104(d))
`Nonerequired.
`
`Authorization to Charge Fees
`The Commissioner is hereby authorized to charge the filing fees of $920.00 to Deposit
`Account N° 12-2252. Please charge any underpayments related to this filing or credit any
`excess to Deposit Account N® 12-2252. A copy of thigransmittal is enclosed for accounting
`purposes only.
`
`Pleasedirect all correspondence andtelephonecalls to:
`
`CUSTOMERNo.24319
`TIMOTHY CROLL
`LEGAL DEPARTMENT- IP
`LSI LoGiIc CORPORATION
`M/S D-106
`1621 BARBER LANE
`MILpITas, CA 95035
`
`DATED:
`
`November17, 2004.
`
`Respectfully submitted,
`Kunal N. Taravadeetal.,
`LSI Logic Corporation,
`
`
`
`Sunah K. Lee
`Reg. N? 53,198
`
`SUITER * WEST PC LLO
`14301 FNB PARKWAY,SUITE 220
`OMAHA,NE 68154-5299
`(402) 496-0300 (TELEPHONE)
`(402) 496-0333 (TELECOPIER)
`
`This Transmittal Ends With This Page.
`
`

`

`PATENT
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`APPLICATION FOR PATENT
`
`ON
`
`METHOD AND SYSTEM FOR REDUCINGINTER-LAYER CAPACITANCE IN
`INTEGRATED CIRCUITS
`
`BY
`
`Kunal Taravade
`15539 SE Knapp Drive
`Portland, OR 97236
`Citizen of USA
`
`Neal Callan
`455 Furnace Street
`Lake Oswego, OR 97034
`Citizen of USA
`
`Paul Filseth
`230 Jensen Springs Road
`Los Gatos, CA 95033
`Citizen of USA
`
`
`CERTIFICATE OF MAILING BY “EXPRESS MAIL”
`
`“Express Mail” Mailing Label Number EV 515 455 948 US
`
`
`Date of Deposit: November 17, 2004
`I hereby certify that this correspondence is being deposited with the United States Postal Service “Express
`Mail Post Office to Addressee”service under 37 C.F.R. § 1.10 on the date indicated above andis addressed
`
`
`totheCammi ADi atents, P.O. Box 1450,Alexandria,VA22313-1450.
`
`
`On
` Re
`ea D. Berggren
`
`

`

`METHOD AND SYSTEM FOR REDUCING INTER-LAYER CAPACITANCEIN
`INTEGRATED CIRCUITS
`
`FIELD OF THE INVENTION
`invention generally relates to the field of integrated circuit
`{0001] The present
`fabrication, and particularly to a method for reducing inter-layer capacitance through
`dummyfill methodology.
`
`BACKGROUND OF THE INVENTION
`In any integrated circuit, there is an inevitable capacitance that is introduced from
`(0002]
`electromagnetic interaction between electrical conductors, such as interconnect layers
`(metals). There are two components of such capacitance, a bulk (area) component and a
`fringe (peripheral) component. The bulk componentis proportional to the overlap area of
`interconnect layers and the fringe component dependson the separation and the perimeter
`of adjacent interconnect layers. Referring now to FIG. 1, the bulk capacitance 102 and
`the fringe capacitance 104 between Metal 1 and Metal 2 of an exemplary integrated
`circuit 100 are shown. The bulk capacitance generated due to the overlap of signal
`carrying lines on Metal 1 and Metal 2 may not be easily avoided since the placement of
`signal carrying lines is dictated by circuit functionality. However, the bulk capacitance
`introduced dueto the overlap of non- signal carry lines may be reduced by changing the
`placementof non-signalcarry lines.
`
`{0003} An example of non-signal carry lines includes “dummy”fills which are utilized to
`even the topography and pattern density across the chip, prevent etch, or the like.
`“Dummy”fills refer to additional features to an integrated chip layout. In a typical
`integrated chip layout, there are unused areas onalayerafter the signal, power and clock
`segments have been routed. These unusedareas can be large enoughsuchthat additional
`features (metals) should be added to satisfy minimum metal coverage requirements for
`manufacturing. The "dummy" fills may be added to the unused areas such that
`subsequentlayers on the integrated circuit are substantially planar.
`
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`(0004) For example, a dummy fills methodology is utilized in chemical mechanical
`polishing or planarization (CMP) process. Often, the planer profile resulting from the
`CMPprocess is dependent on the pattern density of the underlying layer. The density
`may vary and thus result in CMP planer profile variation. Such CMP planer profile
`variation may be reduced by employing the dummy fills methodology. In particular,
`dummyfills (dummyfeatures) are inserted into a wafer prior to the CMPprocessso asto
`make the pattern density more uniform in IC chips. Uniform feature density improves
`wafer-processing uniformity for certain operations such as CMP. Dummy fills are
`typically placed according to conventional dummyfills methodologies that locate dummy
`fills where space is available. However, the conventional dummyfills methodologies
`allow a large planer profile variation. Some sophisticated dummyfills methodologies are
`utilized to reduce the large planerprofile variation by selectively inserting dummyfills to
`achieve an effective density to within a predeterminedrange.
`
`{0005} While most dummy fills methodologies have focused on uniform feature density,
`the problems created by the inserted dummyfills such as adverse effects on the electric
`field, unwanted bulk capacitance, and the like have not been addressed. Further, the
`existing dummyfill methodologies treat each layer independently whichresults in a large
`overlap over dummyfill areas on successive layers. Referring now to FIG. 2, the overlaps
`206 between Metal 1 dummyfill area 202 and Metal 2 dummyfill area 204 are shown.If
`the overlaps 206 are large, the unwanted bulk capacitance may be increased, thereby
`slowing down signals in the circuit and adversely affecting timing.
`
`{0006} Therefore, it would be desirable to provide a method and system of intelligent
`dummyfill placementto reduceinter-layer capacitance caused by overlaps of dummyfill
`area on successive layers. It would be also desirable to provide a method and system for
`
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`treating each consecutive pair of layers together whenthe intelligent dummyfilling
`placementis performed.
`
`SUMMARYOF THE INVENTION
`
`[0007] Accordingly, the present invention provides a method and system for reducing
`inter-layer capacitance utilizing an intelligent dummyfilling placement in integrated
`
`circuits.
`
`Ina first aspect of the present invention, a system for locating dummyfill features
`[0008]
`in an integrated circuit fabrication process is provided. The system may comprise an
`input for obtaining circuit
`layout information which provides initial signal
`lines on
`layers of the integrated circuit. The system maytreat each successive pair of layers (a
`first layer and a second layer) together. The system may comprise a means for defining
`dummyfill features including small squares within the dummyfill space. The dummyfill
`spaces are suitable to have dummyfill features inserted. The dummy fill spaces may
`include areas where dummypatterns are intended to be placed onthefirst layer and the
`secondlayer. Then, the system mayassign alternating dummyfill features to each layer
`in order to avoid overlaps between dummyfill features on each layer.
`
`In a second aspect of the present invention, a method of placing dummyfill
`(0009)
`patterns to minimizeinter-layer capacitance in an integrated circuit fabrication processis
`provided. The integrated circuit may include many interconnect layers (metals). The
`method may treat each consecutive pair of layers (a first layer and a second layer)
`together. Layout information of the integrated circuit may be obtained to determine an
`initial dummy fill space for a first layer and a second layer. Whether there are overlaps
`betweentheinitial dummyfill space on the first layer and the initial dummyfill space on
`the second dummyfill space may be determined. If the overlaps are found and avoidable
`by re-arranging dummyfill patterns, a first dummyfill pattern and a second dummyfill
`pattern maybe re-arranged to minimizethe overlaps.
`
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`[0010] Additionally, the first dummy fill pattern may be placed to form a checkerboard
`pattem. If the first layer is already arranged in the form of a checkerboard pattern, the
`first dummy fill pattern may not be re-arranged. Then, the second dummyfill pattern
`maybe placed to form a checkerboard pattern so as to be offset from the first dummy fill
`pattern. In this manner, each of the dummy fill features on the first layer may not be
`placed directly above dummy fill features on the second layer. Consequently,
`the
`unwanted bulk capacitance introduce by the dummyfill may be reduced and thus the
`inter-layer capacitance is minimized.
`
`is to be understood that both the foregoing general description and the
`It
`(o011]
`following detailed description are exemplary and explanatory only and are notrestrictive
`of the invention as claimed. The accompanying drawings, which are incorporated in and
`constitute a part of the specification,
`illustrate an embodiment of the invention and
`together with the general description, serve to explain the principles ofthe invention.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`[0012] The numerous advantages ofthe present invention may be better understood by
`those skilled in the art by reference to the accompanying figures in which:
`FIG.
`1
`is an illustration of fringe and bulk capacitance components in an
`exemplary integrated circuit having Metal 1 and Metal 2 layers;
`FIG.2 is an illustration of layout image showing overlaps of dummy fill areas of
`
`Metal 1 and Metal 2 layers in FIG.1;
`FIG.3 is a flow diagram illustrating a method implementedin accordance with an
`exemplary embodiment of the present invention wherein two consecutive layers are
`treated;
`
`FIG. 4 is a top view of a layer showing a checkerboard pattern formed by the
`method described in FIG.3;
`
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`FIG. 5 is a top view of two layers showing an alternative pattern with which the
`present invention can be embodied; and
`FIG.5 is a cross-sectional view of two layers showing offset dummy fill features
`inserted by the method described in FIG.3.
`
`DETAILED DESCRIPTION OF THE INVENTION
`[0013] Reference will now be made in detail to the presently preferred embodiments of
`the invention, examples of whichareillustrated in the accompanying drawings.
`
`(0014) Referring generally now to FIGS. 3 through 5, exemplary embodiments of the
`present invention are shown.
`
`[0015] The present invention is directed to a method and system ofintelligent dummy
`filling placement to reduce inter-layer capacitance caused by overlaps of dummy fills on
`successive layers. Generally, dummyfill refers to the addition of features to a layout for
`the purpose of raising the density of specific regions on the layout of the integrated
`circuit. The method and system treats each consecutive pair of layers together so as to
`minimize the overlaps of dummyfills between each layer. In particular, dummy fill
`features on each layer may beplaced in a checkerboard pattern to avoid overlaps. As
`such, the present invention may eliminate large overlap areas of the dummy fills on
`consecutive layers by utilizing intelligent dummy fill placement.
`In the following
`description, numerousspecific descriptions are set forth in order to provide a thorough
`understanding of the present invention.It should be appreciated by those skilled in the art
`that the present invention may be practiced without someorall of these specific details.
`In some instances, well known process operations have not been described in detail in-
`order to prevent obscurity of the present invention.
`
`{0016] Referring now to FIG. 3, a flow diagram 300 illustrating a method implemented
`in accordance with an exemplary embodimentofthe present invention wherein a dummy
`
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`

`fill process is performed on each layer of an integrated circuit is shown. Generally, an
`integrated circuit fabrication process involves a series of layering processes in which
`metallization, dielectrics, and other materials
`are applied to the
`surface of a
`semiconductor wafer to form a layered interconnected structure (an interconnectlayer).
`The integrated circuits generally include inter-layered circuits comprising a plurality of
`metal
`lines across multiple layers that are interconnected by metal-filled vias. The
`method begins in step 302 in which a first layer and a second layer are selected for
`dummyfill process. The first layer and the second layer are a consecutive pair of layers
`
`of the IC.
`
`(0017) Generally, dummy fills are utilized to improve planer profile uniformity by
`helping to level
`the feature density across the layout during an integrated circuit
`fabrication process. For example, dummy fills are utilized in chemical mechanical
`polishing or planarization (CMP)process. Often, the planer profile resulting from the
`CMPprocessis dependent on the pattern density ofthe underlying layer. The dependency
`may vary and thus offset the CMPplaner profile variation. Such variation may be
`reduced by employing the dummy fills methodology. In particular, dummyfills (dummy
`features) are inserted into a wafer prior to the CMPprocess so as to make the pattern
`density more uniform in IC chips. Uniform feature density improves wafer-processing
`uniformity for certain operations such as CMP.Placement of the dummyfills is typically
`made according to conventional dummy fill methodologies that locate the uniform-
`densities dummy where spaceis available. However, the inserted dummy fills may create
`problemssuch as adverse effects on the electric field, unwanted bulk capacitance, and the
`
`like.
`
`In Step 304, the original (initial) dummyfill spaces of the first layer and the
`[0018]
`second layer may be obtained based on layout information. The layout information may
`be provided by a user, an IC fabrication process system, a CAD tool, or the like. The
`original dummyfill space may snclude areas where dummyfill patterns are intended to be
`
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`

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`placed on layers. Then, in Step 306, whether there is any overlap betweenthe original
`dummyfill space ofthe first layer and the original dummyfill space of the second layer
`may be determined. The overlaps of dummy fill areas between the first layer and the
`second layer are undesirable since the unwanted bulk capacitance maybe introduced by
`the overlaps. Thus, in step 308, whether the overlap can be avoided by re-arrangement of
`dummy features may be checked. Then, dummyfill patterns on the first layer and the
`second layer may be re-arranged to minimize the overlaps in Step 310.
`In a particular
`embodimentof the present invention, a grid (composed of small squares) may be defined
`within the dummyfill spaces. The method may assign alternating squares (dummy fill
`features) in the grid to each layer.
`In this manner, dummy fill features on the first layer
`are not placed directly above the ones on the secondlayer but offset from each other.It is
`to be noted that the dummy fill features may be placed to form various predefined
`patterns designed to prevent overlaps on adjacent layers. Referring now to FIG. 4, an
`exemplary top view of a layer showing a checkerboard pattern formed by the present
`invention is shown. As shown in FIG. 4, dummyfill features placed in a checkerboard
`pattern may avoid overlap, thereby reducing the bulk capacitance component of the total
`capacitance. Preferably,
`the dummy fill features are placed to form a checkerboard
`pattern. Referring now to FIG. 5, an exemplary top view of two layers showing a
`different pattern with which the present invention can be embodied is shown.
`
`[0019] Referring backto FIG.3, if there is no overlap found, the method may proceed to
`check whether all interconnect layers in the IC have been treated in Step 312. If all
`interconnect layers have been treated, the method may finish the dummy fill pattern
`placementin step 314.If all interconnect layers have not beentreated, the method may
`proceed to step 302 byselecting the next pair of consecutive layers.
`
`{0020} Additionally, the method may check whetherthefirst layer is already arranged in
`the form of a checkerboard.Ifthe first layer includes dummyfill pattern in the form of a
`checkerboard, the dummyfill pattern on first layer may not be re-arranged. The dummy
`
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`

`

`fill pattern on the second layer may be re-arranged to form a checked board pattern by
`offsetting against the dummyfill pattern on the first layer.
`
`j0021] One ofskill in the art will appreciate that there are various ways to check the form
`of the dummyfill pattern. In a particular embodiment, numbers may be assigned to
`dummy features in order to check whether the dummyfill pattern is already in the form
`of a checkerboard pattern. For example, a dummy feature may have a row number, a
`column number, and a layer number. The dummy fill pattern may be checked by
`implementation of a simple Boolean check as follows: Pattern checking number = row
`number + column number + layer number. Each dummy feature may have a pattern
`checking number. The numbering schemefor the simple Boolean check may be assigned
`such that the pattern checking number is always odd for given row number, column
`number and layer number. As such, the dummy fill features on the first layer and the
`second layer are placed on alternating row and column combinations. Additionally, the
`simple Boolean check may be utilized to determine whether to re-arrange dummy
`features on the layer.
`
`In FIG. 6, a cross-sectional view 600 of two layers showing offset dummy fill
`[0022]
`features inserted by the present invention is shown. The first dummy features 602, 604 is
`arranged to offset the second dummy features 606-610. The checkerboard style layout of
`the dummyfill pattern prevents situations in which dummy patterns on successive layers
`overlap, thereby increasing parasitic capacitance of the circuit by adding bulk (area)
`capacitance of the chip in proportion to the overlap area of the dummy patterns on
`consecutive layers. By offsetting the dummypatterns in a checkerboard fashion,the large
`bulk capacitance component may be eliminated. As a result, the total capacitance for an
`integrated circuit may be reduced.
`
`[0023] Generally, the total capacitance for an integrated circuit composed of interconnect
`layers (metals) may be given by:
`
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`

`C totaL = C putk t+ C FRINGE
`where C puLk = Bulk intra-layer capacitance (bulk capacitance of metal lines on the same
`layer) + Bulk inter-layer Capacitance (bulk capacitance ofmetal lines on adjacent layers)
`
`and
`C rrnce= Fringe intra-layer capacitance (fringe capacitance of metallines on the same
`layer) + Fringe inter-layer Capacitance (fringe capacitance of metal lines on adjacent
`layers).
`
`In a particular embodimentof the present invention, the above-described method
`[0024]
`and system may be implemented through various commercially available polygon
`manipulation languages. An example of
`the
`commercially
`available polygon
`manipulation languages may include, but are not limited to, Mentor Graphics® Calibre®,
`Synopsys® Hercules® or the like.
`
`It should be noted that the method and system of the present invention may be
`{0025}
`utilized for wafer processing operations such as CMP. However, the method and the
`system of the present
`invention may be utilized for any suitable integrated circuit
`fabrication process.
`
`In the exemplary embodiments, the methods disclosed may be implemented as
`[0026]
`sets of instructions or software readable by a device. Further, it is understood that the
`specific order or hierarchy of steps in the methods disclosed are examples of exemplary
`approaches. Based upon design preferences,it is understood that the specific order or
`hierarchy of steps in the method can be rearranged while remaining within the scope and
`spirit of the present invention. The accompanying method claims present elements ofthe
`various steps in a sample order, and are not necessarily meantto be limited to the specific
`order or hierarchy presented.
`
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`

`

`It is believed that the method and system ofthe present invention and manyofits
`{0027}
`attendant advantages will be understood by the forgoing description.
`It is also believed
`that it will be apparent that various changes may be madein the form, construction and
`arrangement ofthe components thereofwithout departing from the scope and spirit ofthe
`invention or without sacrificing all ofits material advantages. The form herein before
`described being merely an explanatory embodiment thereof.
`It is the intention of the
`following claims to encompass and include such changes.
`
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`

`

`CLAIMS
`
`1.
`
`the integrated circuit
`
`What is claimedis:
`A method for placing dummy fill patterns in an integrated circuit fabrication
`process, comprising:
`obtaining layout
`information of the integrated circuit,
`including a plurality of layers;
`obtaining a first dummyfill space forafirst layer based on the layout information,
`obtaining a second dummy fill space for a second layer, the second layer being
`placed successively to the first layer;
`determining an overlap between the first dummyfill space and the second dummy
`fill space; and
`minimizing the overlap by re-arranging a plurality offirst dummyfill features and
`a plurality of second dummyfill features,
`wherein the first dummyfill space includes non-signal carrying lines on the first
`layer and the second dummy fill space includes non-signal carrying lines on the
`
`second layer.
`
`The method as described in Claim 1, wherein the plurality of first dummy fill
`features forms a grid within the first dummy fill space.
`
`The method as described in Claim], wherein the plurality of second dummy fill
`features forms a grid within the second dummyfill space.
`
`The method as described in Claim 1, wherein the first dummy fill space is
`determined based onalocalpattern density for the first layer.
`
`The method as described in Claim 1, wherein the second dummyfill space is
`determined based ona local pattern density for the secondlayer.
`
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`

`The method as described in Claim 2, wherein the grid includesaplurality of
`
`squares.
`
`The method as described in Claim 1, the minimizing the overlap step further
`comprising:
`determining whether the plurality of first dummy fill features form a
`predefined pattern; and
`features to form the
`re-arranging the plurality of first dummy fill
`predefined pattern if the plurality of first dummy fill features are not arranged in
`the predefined pattern.
`
`The method as described in Claim 7, further comprising:
`re-arranging the plurality of second dummy fill features based on the
`plurality of first dummy features if the plurality of first dummy fill features are
`already arranged in the predefined pattern.
`
`The method as described in Claim 8, wherein the plurality of second dummy fill
`features are re-arranged so as to beoffset from the plurality of first dummy fill
`
`features.
`
`10.
`
`11.
`
`12.
`
`The method as described in Claim 7, wherein the predefined pattern is a
`checkerboard pattern.
`
`The method as described in Claim 1, wherein a total bulk capacitance is
`minimized.
`
`The method as described in Claim 11, wherein the total bulk capacitance includes
`a bulk inter-layer capacitance.
`
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`

`13.
`
`The methodas described in Claim 11, wherein the bulk inter-layer capacitanceis
`a bulk capacitance created by overlaps between the first
`layer and the second
`layer.
`
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`

`14.|A system forintelligent placement of dummyfill patterns in an integrated circuit
`fabrication process, comprising:
`information of the integrated circuit,
`means for obtaining layout
`integrated circuit including a plurality of layers;
`meansforselecting a first layer and a secondlayer,
`wherein the secondlayer is placed successively to the first layer;
`meansfor obtaining initial layouts of metal lines on thefirst layer and the
`
`the
`
`second layer,
`means for determining a first dummyfill space based onthe initial layout
`on the first layer, the first dummy fill space suitable for including a plurality of
`dummyfill features onthefirst layer;
`means for determining a second dummy fill space based on the initial
`layout on the second layer, the second dummyfill space suitable for including a
`plurality of dummyfill features on the secondlayer;
`means for determining an overlap between the first dummyfill space and
`the second dummyfill space; and
`means for minimizing the overlap by arranging the plurality of first
`dummyfill features and the plurality of second dummy fill features,
`wherein the integrated circuit includes the first layer and the secondlayer.
`
`15.|The system as described in Claim 14, the means for minimizing the overlap
`further comprising:
`meansfor determining whether a dummy fill pattern ofthe first layer is a
`checkerboard pattern; and
`means for placing the plurality of first dummyfill features to form the
`checkerboard pattern if the dummy fill pattern ofthe first layer is not arranged in
`the checkerboard pattern.
`
`LSI 04-0800
`
`14
`
`

`

`16.
`
`17.
`
`18.
`
`19.
`
`20.
`
`The system as described in Claim 14, further comprising:
`means for placing the plurality of second dummy fill features based on the
`dummyfill pattern of the first layer if the dummyfill pattern of the first layer is
`already the checkerboardpattern.
`
`The system as described in Claim 16, wherein the plurality of second dummyfill
`features are placed so as to form an alternate checkerboard pattern against the
`checkerboard pattern ofthe plurality of first dummyfill features.
`
`The system as described in Claim 16, wherein the plurality of second dummyfill
`features are placed so as to be offset from the plurality of first dummy fill
`
`features.
`
`The system as described in Claim 14, wherein a total bulk capacitance of the
`integrated circuitis minimized.
`
`A method of filling dummy patterns for pattern density equalization in an
`integratedcircuit fabrication process, comprising:
`obtaining a local density pattern of a first layer, the local density pattern
`obtained based on an initial layout design of the integrated circuit;
`determining a secondlayer, the second layer being placed successively to
`the first layer;
`obtaining a local density pattern of the second layer, the local density
`pattern obtained based ontheinitial layout design ofthe integrated circuit;
`designing a plurality of dummy fill features on the first layer and the
`second layer, the plurality of dummyfill features being suitable for increasing
`pattern density in low density spaces on thefirst layer and the secondlayer;
`determining whether there is an overlap between the plurality of dummy
`fill features on the first layer and the plurality of dummy fill features on the
`
`LSI 04-0800
`
`15 -
`
`

`

`second layer; and
`minimizing the overlap by re-arranging the plurality of dummy fill
`features on thefirst layer and the secondlayer,
`wherein a total
`inter-layer capacitance of the integrated circuit
`
`is
`
`minimized.
`
`21.
`
`The method as described in Claim 20, the minimizing the overlap step further
`comprising:
`determining whether the plurality of first dummy fill feature form a
`checkerboard pattern; and
`placing the plurality of first dummy fill features to form thecheckerboard
`pattern base through a mathematical check if the plurality of first dummy fill
`features are not a form of the checkerboardpattern,
`wherein the mathematical check is applied to numeric values of each of
`the plurality of first dummy fill features and the numeric values of each of the
`plurality of first dummy fill features are determined based on the location on the
`checkerboard pattern.
`
`22.
`
`23.
`
`24.
`
`The method as described in Claim 20,further comprising:
`features based on an
`placing the plurality of second dummy fill
`arrangement of the plurality of
`first dummy features if the plurality of first
`dummyfill features form a checkerboard pattern.
`
`The method as described in Claim 22, wherein the plurality of second dummy fill
`features are placed so as to form an alternate checkerboard pattern against the
`checkerboard pattern ofthe plurality of first dummyfill features.
`
`The methodas described in Claim 22, wherein the plurality of second dummy fill
`features are placed so as to beoffset from the plurality of first dummy fill
`
`LSI 04-0800
`
`16
`
`

`

`features.
`
`25.
`
`The method as described in Claim 20, further comprising:
`placing the plurality of second dummy fill
`checkerboard pattern base through a mathematical check,
`wherein the mathematical check is applied to numeric values of each of
`the plurality of second dummyfill features and the numeric values of each of the
`plurality of second dummy fill features are determined based on the location on
`
`to form the
`
`features
`
`the checkerboard pattern.
`
`LSI 04-0800
`
`17
`
`

`

`METHOD AND SYSTEMFOR REDUCING INTER-LAYER CAPACITANCEIN
`INTEGRATED CIRCUITS
`
`ABSTRACT
`
`[0028] The present invention is directed to a method and system of intelligent dummy
`filling placementto reduce inter-layer capacitance caused by overlaps of dummyfilling
`area on successive layers. The method and system treats each consecutive pair of layers
`together so as to minimize dummyfilling overlaps between each layer. In particular,
`dummy fill features on each layer may be placed in a checkerboard pattern to avoid
`overlaps. As such, the present invention may eliminate large overlap area of the dummy
`patterns on consecutive layers by utilizing intelligent dummyfilling placement.
`
`LSI 04-0800
`
`18
`
`

`

`04-0800
`
`1/5
`
`Bulk
`capacitance
`
`FIG._1
`
`Fringe
`capacitance
`
`104 {
`
`
`

`

`302
`
`
`
`
` Is there an overlap
`betweenthefirst and the second dummyfill space
`?
`
`306
`
`04-0800
`
`2/5
`
`300
`
`fo
`
`Select a first and a second metal
`layers for dummy fills process
`
`
`Obtain original dummyfill spaces on
`
`the first and the second metal layers
`
`304
`
`
`
`
`Yes
`
`308
`
`is the overlap avoidable
`
`Re-arrange dummyfill features
`
`
`
`Are all metallayers treated
`?
`
`Yes
`
`Finish dummyfills process
`
`314
`
`FIG._3
`
`

`

`04-0800
`
`3/5
`
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`sees
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`RSmesos
`|
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`sateen
`penereces
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`
`FIG._4
`
`
`
`

`

`04-0800
`
`415
`
`FIG._5
`
`

`

`04-0800
`
`5/5
`
`Side-view (Cross-sectional) of offset
`dumm