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`Case 1:17-cv—00868—JFB-SRF Document 20-2 Filed 09/05/17 Page 1 of 42 PageID #: 432
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`EXHIBIT B
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`EXHIBIT B
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`EXHIBIT B
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`EXHIBIT B
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`MACRONIX INTERNATIONAL CO.,
`LTD, a Taiwanese corporation,
`
`
`Plaintiff,
`
`v.
`
`SPANSION INC., a Delaware corporation,
`and SPANSION LLC, a Delaware
`corporation,
`
`
`
`
`
`
`Civil Action No.: 3:13-cv-00679-REP
`
`
`
`
`
`
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`IN THE UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF VIRGINIA
`Alexandria Division
`
`
`Defendants.
`
`
`
`
`MACRONIX INTERNATIONAL CO., LTD’S
`FIRST AMENDED COMPLAINT FOR PATENT INFRINGEMENT
`
`Plaintiff Macronix International Co., Ltd. (“Macronix”) brings this first amended
`
`complaint for patent infringement against Spansion, Inc. and Spansion LLC (collectively, the
`
`“Defendants”), and in support thereof states as follows:
`
`INTRODUCTION
`
`1. Macronix brings this action pursuant to the patent laws of the United States,
`
`including 35 U.S.C. § 271, et seq. Defendants have and continue to infringe one or more claims
`
`of U.S. Patent Nos. 5,619,052 (“the ’052 Patent”); 5,836,772 (“the ’772 Patent”); 5,998,826 (“the
`
`’826 Patent”); 6,031,757 (“the ’757 Patent”); 6,421,267 (“the ’267 Patent”); 8,341,324 (“the ’324
`
`Patent”); and 8,341,330 (“the ’330 Patent”) (collectively, the “Macronix Patents” or the “Patents-
`
`in-Suit”). True and correct copies of the Macronix Patents are attached hereto as Exhibits A
`
`through G, respectively.
`
`
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`
`THE PARTIES
`
`2. Macronix International Co., Ltd. is a corporation organized under the laws of
`
`Taiwan, having its principal place of business at No. 16, Li-Hsin Road, Science Park, Hsin-chu,
`
`Taiwan, Republic of China. Macronix is the owner of all right, title and interest to the Macronix
`
`Patents, including the right to collect damages for past infringement of the Macronix Patents.
`
`3.
`
`Upon information and belief, Spansion, Inc. is incorporated in Delaware and its
`
`headquarters are located at 915 DeGuigne Drive, Sunnyvale, CA 94085. Spansion, Inc. makes,
`
`uses, sells, offers to sell, and imports flash memory chips that infringe the Macronix Patents in
`
`this District and elsewhere.
`
`4.
`
`Upon information and belief, Spansion LLC is a wholly owned operating
`
`subsidiary company of Spansion, Inc. Spansion LLC is incorporated in Delaware and its
`
`headquarters are located at 915 DeGuigne Drive, Sunnyvale, CA 94085. Spansion LLC makes,
`
`uses, sells, offers to sell, and imports flash memory chips that infringe the Macronix Patents in
`
`this District and elsewhere.
`
`JURISDICTION AND VENUE
`
`5.
`
`This action arises under the patent laws of the United States, Title 35 of the
`
`United States Code. This Court has exclusive subject matter jurisdiction over this action under
`
`28 U.S.C. §§ 1331 and 1338(a).
`
`6.
`
`Upon information and belief, this Court has personal jurisdiction over Defendants
`
`for at least the following reasons: (i) Defendants have committed acts of willful patent
`
`infringement, and/or induced acts of patent infringement by others, in this District and elsewhere
`
`in Virginia and the United States; (ii) Defendants knowingly and intentionally place their
`
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`2
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`products, including the accused products, into the stream of commerce within this District and
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`can reasonably be expected to be hailed into court here; and (iii) Defendants have voluntarily
`
`consented to the jurisdiction of this Court with regard to patent infringement actions involving
`
`flash memory devices, including because Spansion LLC previously filed a similar action within
`
`this District and further opposed transferring that case out of this District.
`
`7.
`
`Upon information and belief, venue is proper in this District under 28 U.S.C. §§
`
`1391(b)-(c) and 1400(b) because Defendants are subject to personal jurisdiction in this District
`
`and have committed acts of infringement in this District. For instance, upon information and
`
`belief, Defendants have sold infringing products to downstream customers located in this
`
`District, including: Cornet Technology, Inc., Encore Networks, Power Monitors, Inc., Vidar
`
`Systems, and NAL Research.
`
`BACKGROUND
`
`8.
`
`Established in 1989, Macronix is a leading innovator of non-volatile memory
`
`semiconductor solutions. Led by scientists and researchers, Macronix dedicates a substantial
`
`portion of its revenue, upwards of $170 million annually, to research and development and
`
`regularly publishes and presents technical papers in major international conferences to help bring
`
`the next generation of non-volatile memory solutions to consumers all over the world.
`
`Macronix’s cutting-edge technology is used in a wide range of products.
`
`9. Macronix has made substantial investments in protecting its intellectual property.
`
`Macronix has over 5,000 patents issued to it worldwide, including over 1,700 United States
`
`patents. According to a 2011 study by the Patent Board™, among the 240 semiconductor
`
`
`
`3
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`
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`
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`companies evaluated, Macronix’s patent portfolio was ranked as the 18th worldwide and 1st in the
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`Taiwanese semiconductor industry.
`
`10. However, Macronix’s ability to provide consumers with innovative technology is
`
`dependent upon its ability to protect its innovations. To that end, Macronix’s ability to compete
`
`has been significantly compromised by the acts complained of in this Complaint.
`
`ASSERTED PATENTS
`
`11. Macronix is the owner of all rights, title, and interest in the Macronix Patents,
`
`including the right to bring this suit for injunctive relief and damages.
`
`12. The ’052 Patent, titled “Interpoly Dielectric Structure in EEPROM Device,” was
`
`duly and legally issued by the United States Patent and Trademark Office on April 8, 1997.
`
`13. The ’772 Patent, titled “Interpoly Dielectric Process” was duly and legally issued
`
`by the United States Patent and Trademark Office on Nov. 17, 1998.
`
`14. The ’826 Patent, titled “Triple Well Floating Gate Memory and Operating Method
`
`with Isolated Channel Program, Preprogram and Erase Processes” was duly and legally issued by
`
`the United States Patent and Trademark Office on Dec. 7, 1999.
`
`15. The ’757 Patent, titled “Write Protected, Non-Volatile Memory Device with User
`
`Programmable Sector Lock Capability” was duly and legally issued by the United States Patent
`
`and Trademark Office on Feb. 29, 2000.
`
`16. The ’267 Patent, titled “Memory Array Architecture” was duly and legally issued
`
`by the United States Patent and Trademark Office on Jul. 16, 2002.
`
`
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`4
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`17. The ’324 Patent, titled “Serial Peripheral Interface and Method for Data
`
`Transmission” was duly and legally issued by the United States Patent and Trademark Office on
`
`Dec. 25, 2012.
`
`18. The ’330 Patent, titled “Method and System for Enhanced Read Performance in
`
`Serial Peripheral Interface” was duly and legally issued by the United States Patent and
`
`Trademark Office on Dec. 25, 2012.
`
`COUNT I
`
`(INFRINGEMENT OF THE ’052 PATENT)
`
`19. Plaintiff realleges and incorporates herein by reference the allegations in
`
`paragraphs 1 – 18 above as if fully set forth herein.
`
`20. Upon information and belief, the Defendants have infringed, and continue to
`
`infringe, the ’052 Patent by making, using, offering for sale, and/or selling within the United
`
`States, and/or importing into the United States, products that practice the inventions claimed in
`
`the ’052 Patent, including, but not limited to their S34ML01G1, S34ML02G1, S34ML04G1,
`
`S34ML08G1, S34ML01G2, S34ML04G2, S34MS01G1, and S34MS02G1 NAND Flash
`
`Memory Products. Such infringing products infringe, literally and/or under the doctrine of
`
`equivalents, at least the following valid and enforceable claims of the ’052 patent: 1, 3-8, 10, 12-
`
`18, and 21.
`
`21. More specifically, on information and belief, the Defendants’ making, using,
`
`offering for sale, and/or selling in the United States, and/or importing into the United States of
`
`each of these NAND Flash Memory Products satisfies all elements of at least the aforementioned
`
`claims of the ’052 patent, literally and/or under the doctrine of equivalents, as follows:
`
`
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`5
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`a. Claim 1 recites “[a] dielectric insulating composite for insulating a floating
`
`gate from a control gate in a nonvolatile memory cell, the dielectric
`
`insulating composite comprising.” Regardless of whether the preamble
`
`limits the scope of claim 1, the Defendants’ products contain such a dielectric
`
`insulating composite.
`
`b. Claim 1 further recites “a bottom layer of silicon dioxide formed on said
`
`floating gate.” The Defendants’ products contain such a bottom layer of
`
`silicon dioxide.
`
`c. Claim 1 further recites “a layer of silicon nitride formed on said bottom
`
`silicon dioxide layer, said silicon nitride layer having a thickness which is
`
`less than said bottom silicon dioxide layer.” The Defendants’ products
`
`contain such a layer of silicon nitride.
`
`d. Claim 1 further recites “a top layer of silicon dioxide formed on said nitride
`
`layer, said top silicon dioxide layer having a thickness which is greater than
`
`said silicon nitride layer.” The Defendants’ products contain such a top layer
`
`of silicon dioxide.
`
`e. Claim 3 recites “[a] dielectric insulating composite according to claim 1
`
`wherein said bottom silicon dioxide layer has a thickness equal to or less than
`
`about 100 A and said top silicon dioxide layer has a thickness equal to or less
`
`than about 100 A.” The Defendants’ products contain such bottom and top
`
`silicon dioxide layers.
`
`f. Claim 4 recites “[a] dielectric insulating composite according to claim 3
`
`wherein said bottom and top silicon dioxide layers are formed by high
`
`
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`6
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`temperature chemical vapor deposition.” The Defendants’ products contain
`
`such bottom and top silicon dioxide layers.
`
`g. Claim 5 recites “[a] dielectric insulating composite according to claim 3
`
`wherein said silicon nitride layer has a thickness less than about 80 A.” The
`
`Defendants’ products contain such a silicon nitride layer.
`
`h. Claim 6 recites “[a] dielectric insulating composite according to claim 3
`
`wherein said bottom silicon dioxide layer has a thickness between about 25
`
`and 100 A, said silicon nitride layer having a thickness less than about 80 A
`
`and said top silicon dioxide layer having a thickness between about 40 and
`
`100 A.” The Defendants’ products contain such bottom silicon dioxide,
`
`silicon nitride, and top silicon dioxide layers.
`
`i. Claim 7 recites “[a] dielectric insulating composite according to claim 6
`
`wherein the capacitively measured effective oxide thickness of said dielectric
`
`insulating composite is equal to or less than about 180 A.” The Defendants’
`
`products contain such an oxide thickness.
`
`j. Claim 8 recites “[a] dielectric insulating composite according to claim 6
`
`wherein said bottom and top silicon dioxide layers are formed by high
`
`temperature chemical vapor deposition.” The Defendants’ products contain
`
`such bottom and top silicon dioxide layers.
`
`k. Claim 10 recites “[a] nonvolatile memory cell comprising.” Regardless of
`
`whether the preamble limits the scope of claim 10, the Defendants’ products
`
`contain such a nonvolatile memory cell.
`
`
`
`7
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`l. Claim 10 further recites “a) a first conductivity-type semiconductor
`
`substrate.” The Defendants’ products contain such a semiconductor
`
`substrate.
`
`m. Claim 10 further recites “b) source and drain regions formed on a surface of
`
`said substrate.” The Defendants’ products contain such source and drain
`
`regions.”
`
`n. Claim 10 further recites “c) an insulating layer formed on said source and
`
`drain regions.” The Defendants’ products contain such an insulating layer.
`
`o. Claim 10 further recites “d) a floating gate positioned on said insulating
`
`layer.” The Defendants’ products contain such a floating gate.
`
`p. Claim 10 further recites “e) a dielectric composite positioned on said floating
`
`gate, said dielectric composite including a bottom layer of silicon dioxide
`
`formed on said floating gate; a layer of silicon nitride formed on said bottom
`
`silicon dioxide layer, said silicon nitride layer having a thickness which is
`
`less than said bottom silicon dioxide layer; and a top layer of silicon dioxide
`
`formed on said nitride layer, said top silicon dioxide layer having a thickness
`
`which is greater than said silicon nitride layer.” The Defendants’ products
`
`contain such a dielectric composite.
`
`q. Claim 10 further recites “f) a control gate positioned on said dielectric
`
`composite.” The Defendants’ products contain such a control gate.
`
`r. Claim 12 recites “[a] nonvolatile memory cell according to claim 10 wherein
`
`said bottom silicon dioxide layer has a thickness equal to or less than about
`
`100 A and said top silicon dioxide layer has a thickness equal to or less than
`
`
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`8
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`about 100 A.” The Defendants’ products contain such bottom and top silicon
`
`dioxide layers.
`
`s. Claim 13 recites “[a] nonvolatile memory cell according to claim 10 wherein
`
`the capacitively measured effective oxide thickness of said dielectric
`
`insulating composite is equal to or less than about 180 A.” The Defendants’
`
`products contain such an oxide thickness.
`
`t. Claim 14 recites “[a] nonvolatile memory cell according to claim 12 wherein
`
`said bottom and top silicon dioxide layers are formed by high temperature
`
`chemical vapor deposition.” The Defendants’ products contain such bottom
`
`and top silicon dioxide layers.
`
`u. Claim 15 recites “[a] nonvolatile memory cell according to claim 10 wherein
`
`said silicon nitride layer has a thickness less than about 80 A.” The
`
`Defendants’ products contain such a silicon nitride layer.
`
`v. Claim 16 recites “[a] nonvolatile memory cell according to claim 10 wherein
`
`said bottom silicon dioxide layer has a thickness between about 25 and 100
`
`A, said silicon nitride layer having a thickness less than about 80 A and said
`
`top silicon dioxide layer having a thickness between about 40 and 100 A.”
`
`The Defendants’ products contain such bottom silicon dioxide, silicon
`
`nitride, and top silicon dioxide layers.
`
`w. Claim 17 recites “[a] nonvolatile memory cell according to claim 16 wherein
`
`the capacitively measured effective oxide thickness of said dielectric
`
`insulating composite is equal to or less than about 180 A.” The Defendants’
`
`products contain such an oxide thickness.
`
`
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`9
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`x. Claim 18 recites “[a] nonvolatile memory cell according to claim 16 wherein
`
`said bottom and top silicon dioxide layers are formed by high temperature
`
`chemical vapor deposition.” The Defendants’ products contain such bottom
`
`and top silicon dioxide layers.
`
`y. Claim 21 recites “[a] dielectric insulator for insulating a floating gate from a
`
`control gate
`
`in a nonvolatile memory cell,
`
`the dielectric
`
`insulator
`
`comprising.” Regardless of whether the preamble limits the scope of claim
`
`21, the Defendants’ products contain such a dielectric insulator.
`
`z. Claim 21 further recites “a bottom silicon dioxide layer formed on said
`
`floating gate, a layer of silicon nitride formed on said bottom silicon dioxide
`
`layer, said silicon nitride layer having a thickness which is less than said
`
`bottom silicon dioxide layer; and a top layer of silicon dioxide formed on
`
`said nitride layer, said top silicon dioxide layer having a thickness which is
`
`greater than said silicon nitride layer, the dielectric insulator having a
`
`capacitively measured effective oxide thickness equal to or less than about
`
`180 A.” The Defendants’ products contain such bottom silicon dioxide,
`
`silicon nitride, and top silicon dioxide layers.
`
`22. Upon information and belief, the Defendants’ acts of infringement herein have
`
`been made with full knowledge of Macronix’s rights in the ’052 patent. Such acts constitute
`
`willful and deliberate infringement, entitling Macronix to enhanced damages and reasonable
`
`attorneys’ fees.
`
`23. Upon information and belief, the Defendants’ infringing activities have caused
`
`and will continue to cause Macronix irreparable injury unless and until enjoined by this Court.
`
`
`
`10
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`24. As a result of the Defendants’ infringing activities, Macronix has suffered and
`
`will continue to suffer damages in an amount yet to be determined. Under 35 U.S.C. §§ 283 and
`
`284, Macronix is entitled to recover damages, as well as permanent injunctive relief against
`
`further infringing activity.
`
`COUNT II
`
`(INFRINGEMENT OF THE ’772 PATENT)
`
`25. Plaintiff realleges and incorporates herein by reference the allegations in
`
`paragraphs 1 – 18 above as if fully set forth herein.
`
`26. Upon information and belief, the Defendants have infringed, and continue to
`
`infringe the ’772 Patent by making, using, offering for sale, and/or selling within the United
`
`States, and/or importing into the United States, products that practice the inventions claimed in
`
`the ’772 Patent, including, but not limited to their S34ML01G1, S34ML02G1, S34ML04G1,
`
`S34ML08G1, S34ML01G2, S34ML04G2, S34MS01G1, and S34MS02G1 NAND Flash
`
`Memory Products. These products are not materially changed after importation, and these acts
`
`of infringement occurred during the term of the process patent. Such infringing products
`
`infringe, literally and/or under the doctrine of equivalents, at least the following valid and
`
`enforceable claims of the ’772 patent: 1, 3-6, and 9.
`
`27. More specifically, on information and belief, the Defendants’ making, using,
`
`offering for sale, and/or selling in the United States, and/or importing into the United States of
`
`each of these NAND Flash Memory Products satisfies all elements of at least the aforementioned
`
`claims of the ’772 patent, literally and/or under the doctrine of equivalents, as follows:
`
`
`
`11
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`a. Claim 1 recites “[a] process for fabricating a nonvolatile memory cell
`
`comprising.” Regardless of whether the preamble limits the scope of claim
`
`1, the Defendants’ products include nonvolatile memory cells fabricated by a
`
`process.
`
`b. Claim 1 further recites “a) forming source and drain regions on a first
`
`conductivity-type semiconductor substrate.” The Defendants’ products are
`
`fabricated by forming such source and drain regions.
`
`c. Claim 1 further recites “b) forming an insulating layer on said source and
`
`drain regions.” The Defendants’ products are fabricated by forming such an
`
`insulating layer.
`
`d. Claim 1 further recites “c) forming a floating gate positioned on said
`
`insulating layer.” The Defendants’ products are fabricated by forming such a
`
`floating gate.
`
`e. Claim 1 further recites “d) forming a dielectric composite positioned on said
`
`floating gate, said dielectric composite including a bottom layer of silicon
`
`dioxide formed on said floating gate; a layer of silicon nitride formed on said
`
`bottom silicon dioxide layer, and a top layer of silicon dioxide formed on
`
`said nitride layer, wherein said silicon nitride layer of said composite has a
`
`thickness less than about 80 A and is thinner than said top or said bottom
`
`silicon dioxide layer.” The Defendants’ products are fabricated by forming
`
`such a dielectric composite with such bottom and top layers of silicon
`
`dioxide and a layer of silicon nitride.
`
`
`
`12
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`f. Claim 1 further recites “e) forming a control gate positioned on said
`
`dielectric composite.” The Defendants’ products are fabricated by forming
`
`such a control gate.
`
`g. Claim 3 recites “[a] nonvolatile memory cell according to claim 1 wherein
`
`the capacitively measured effective oxide thickness of said dielectric
`
`insulating composite is equal to or less than about 180 A.” The Defendants’
`
`products are fabricated by forming a nonvolatile memory cell with such an
`
`oxide thickness.
`
`h. Claim 4 further recites “[a] process for fabricating a nonvolatile memory cell
`
`according to claim 1 wherein said bottom and top silicon dioxide layers are
`
`formed by high temperature chemical vapor deposition.” The Defendants’
`
`products are fabricated by forming such bottom and top silicon dioxide layers
`
`by high temperature chemical vapor deposition.
`
`i. Claim 5 further recites “[a] process for fabricating a nonvolatile memory cell
`
`according to claim 1 wherein said bottom silicon dioxide layer has a
`
`thickness between about 25 and 80 A and said top silicon dioxide layer
`
`having a thickness between about 40 and 100 A.” The Defendants’ products
`
`are fabricated by forming such bottom and top silicon dioxide layers.
`
`j. Claim 6 further recites “[a] process for fabricating a nonvolatile memory cell
`
`according to claim 5 wherein the capacitively measured effective oxide
`
`thickness of said dielectric insulating composite is equal to or less than about
`
`180 A.” The Defendants’ products are fabricated by forming a dielectric
`
`insulating composite with such an oxide thickness.
`
`
`
`13
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`k. Claim 9 recites “[a] process for fabricating a nonvolatile memory cell
`
`comprising.” Regardless of whether the preamble limits the scope of claim
`
`9, the Defendants’ products include nonvolatile memory cells fabricated by a
`
`process.
`
`l. Claim 9 further recites “a) forming source and drain regions on a first
`
`conductivity-type semiconductor substrate.” The Defendants’ products are
`
`fabricated by forming such source and drain regions.
`
`m. Claim 9 further recites “b) forming an insulating layer on said source and
`
`drain regions.” The Defendants’ products are fabricated by forming such an
`
`insulating layer.
`
`n. Claim 9 further recites “c) forming a floating gate positioned on said
`
`insulating layer.” The Defendants’ products are fabricated by forming such a
`
`floating gate.
`
`o. Claim 9 further recites “d) forming a dielectric insulator positioned on said
`
`floating gate, said dielectric insulator including a first silicon dioxide layer
`
`and a second silicon dioxide layer formed by high temperature chemical
`
`vapor deposition on said first silicon dioxide layer.” The Defendants’
`
`products are fabricated by forming such a dielectric insulator.
`
`p. Claim 9 further recites “e) forming a control gate positioned on said
`
`dielectric composite.” The Defendants’ products are fabricated by forming
`
`such a control gate.
`
`28. Upon information and belief, the Defendants’ acts of infringement herein have
`
`been made with full knowledge of Macronix’s rights in the ’772 patent. Such acts constitute
`
`
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`14
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`willful and deliberate infringement, entitling Macronix to enhanced damages and reasonable
`
`attorneys’ fees.
`
`29. Upon information and belief, the Defendants’ infringing activities have caused,
`
`and will continue to cause, Macronix irreparable injury unless and until enjoined by this Court.
`
`30. As a result of the Defendants’ infringing activities, Macronix has suffered and
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`will continue to suffer damages in an amount yet to be determined. Under 35 U.S.C. §§ 283 and
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`284, Macronix is entitled to recover damages, as well as permanent injunctive relief, against
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`further infringing activity.
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`COUNT III
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`(INFRINGEMENT OF THE ’826 PATENT)
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`31. Plaintiff realleges and incorporates herein by reference the allegations in
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`paragraphs 1 – 18 above as if fully set forth herein.
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`32. Upon information and belief, the Defendants have infringed, and continue to
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`infringe, the ’826 Patent by making, using, offering for sale, and/or selling within the United
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`States, and/or importing into the United States, products that practice the inventions claimed in
`
`the ’826 Patent, including, but not limited to their S29PL127J, S29PL064J, S29JL064J,
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`S29PL032J, S29JL032J, S29CL032J, S29AL016J, S29CL016J, S29AL008J, S29CD032J,
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`S29CD016J, S29AS016J, S29AS008J, S25FL064K, S25FL116K, S25FL132K, S25FL216K,
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`S25FL208K, and S25FL204K NOR Floating Gate Flash Memory Products. Such infringing
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`products infringe, literally and/or under the doctrine of equivalents, at least the following valid
`
`and enforceable claims of the ’826 patent: 1, 2, 5, 7, 11-13, 17, and 27-29.
`
`
`
`15
`
`
`
`
`
`Case 3:13-cv-00679-REP Document 17 Filed 11/20/13 Page 16 of 41 PageID# 163Case 1:17-cv-00868-JFB-SRF Document 20-2 Filed 09/05/17 Page 17 of 42 PageID #: 448
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`
`33. More specifically, on information and belief, the Defendants’ making, using,
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`offering for sale, and/or selling in the United States, and/or importing into the United States of
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`each of these NOR Floating Gate Flash Memory Products satisfies all elements of at least the
`
`aforementioned claims of the ’826 patent, literally and/or under the doctrine of equivalents, as
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`follows:
`
`a. Claim 1 recites “[a] floating gate memory cell in a semiconductor substrate
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`including a region having a first conductivity type, the first conductivity type
`
`being one of n-type and p-type, and wherein the substrate is coupled to an
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`external reference supply applying a ground potential and a positive supply
`
`potential, comprising.” Regardless of whether the preamble limits the scope
`
`of claim 1, the Defendants’ products contain such a floating gate memory
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`cell in a semiconductor substrate.
`
`b. Claim 1 further recites “a first well within the region of the substrate having a
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`second conductivity type, being one of n-type and p-type and different than
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`the first conductivity type.” The Defendants’ products contain such a first
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`well.
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`c. Claim 1 further recites “a second well within the first well, having the first
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`conductivity type.” The Defendants’ products contain such a second well.
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`d. Claim 1 further recites “a drain within the second well, having the second
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`conductivity type.” The Defendants’ products contain such a drain.
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`e. Claim 1 further recites “a source within the second well, having the second
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`conductivity type, and spaced away from the drain to define a channel area
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`
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`16
`
`
`
`
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`Case 3:13-cv-00679-REP Document 17 Filed 11/20/13 Page 17 of 41 PageID# 164Case 1:17-cv-00868-JFB-SRF Document 20-2 Filed 09/05/17 Page 18 of 42 PageID #: 449
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`between the drain and the source.” The Defendants’ products contain such a
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`source and channel area.
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`f. Claim 1 further recites “a floating gate structure disposed over the channel
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`area and extending substantially from the source to the drain, including a
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`floating gate and a tunnel insulator between the floating gate and the
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`substrate.” The Defendants’ products contain such a floating gate and tunnel
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`insulator.
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`g. Claim 1 further recites “a control gate structure over the floating gate,
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`including a control gate and an insulator between the floating gate and the
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`control gate.” The Defendants’ products contain such a control gate and
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`insulator.
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`h. Claim 1 further recites “circuits to induce tunneling of electrons out of the
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`floating gate into the channel area of the substrate by applying a positive
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`voltage higher than the supply potential to the second well, a positive voltage
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`to the first well, and a negative voltage to the control gate, while the region
`
`of the substrate is grounded.” The Defendants’ products contain such circuits
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`to induce such tunneling.
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`i. Claim 2 recites “[t]he floating gate memory cell of claim 1, wherein the first
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`conductivity type is p-type.” The Defendants’ products contain such a first
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`conductivity type.
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`j. Claim 5 recites “[a] floating gate memory array on a semiconductor
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`substrate, including a region having a first conductivity type, the first
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`conductivity type being one of n-type and p-type, and wherein the substrate
`
`
`
`17
`
`
`
`
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`Case 3:13-cv-00679-REP Document 17 Filed 11/20/13 Page 18 of 41 PageID# 165Case 1:17-cv-00868-JFB-SRF Document 20-2 Filed 09/05/17 Page 19 of 42 PageID #: 450
`
`
`is coupled to an external reference supply applying a ground potential and a
`
`positive supply potential comprising.” Regardless of whether the preamble
`
`limits the scope of claim 5, the Defendants’ products contain such a floating
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`gate memory array on such a semiconductor substrate.
`
`k. Claim 5 further recites “a first well within the region of the substrate having a
`
`second conductivity type, being one of n-type and p-type and different than
`
`the first conductivity type.” The Defendants’ products contain such a first
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`well.
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`l. Claim 5 further recites “a second well within the first well, having the first
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`conductivity type.” The Defendants’ products contain such a second well.
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`m. Claim 5 further recites “an array of floating gate memory cells having
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`respective drains, sources, channel areas between the respective sources and
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`drains, floating gates, and control gates over the channel areas, the sources
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`and drains being within the second well, and having the second conductivity
`
`type.” The Defendants’ products contain such an array of floating gate
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`memory cells.
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`n. Claim 5 further recites “voltage supply circuits to induce F-N tunneling of
`
`electrons out of the floating gates into the channel areas of the substrate by
`
`applying a positive voltage higher than the supply potential to the second
`
`well, a positive voltage to the first well, and a negative voltage to the control
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`gates of selected cells, while the region of the substrate is grounded.” The
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`Defendants’ products contain such voltage supply circuits to induce such F-N
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`tunneling.
`
`18
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`
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`
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`Case 3:13-cv-00679-REP Document 17 Filed 11/20/13 Page 19 of 41 PageID# 166Case 1:17-cv-00868-JFB-SRF Document 20-2 Filed 09/05/17 Page 20 of 42 PageID #: 451
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`o. Claim 7 recites “[t]he floating gate memory array of claim 5, wherein the
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`first conductivity type is p-type.” The Defendants’ products contain such a
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`first conductivity type.
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`p. Claim 11 recites “[t]he floating gate memory array of claim 5, wherein the
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`floating gates of the array of floating gate memory cells are disposed over the
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`respective channel areas and extend substantially between the respective
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`sources and drains.” The Defendants’ products
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