Case 1:16-cv-00290-MN Document 45-7 Filed 11/22/17 Page 1 of 13 PageID #: 1346
`Case 1:16-cv-00290-MN Document 45-7 Filed 11/22/17 Page 1 of 13 PageID #: 1346
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`EXHIBIT G
`EXHIBIT G
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`Case 1:16-cv-00290-MN Document 45-7 Filed 11/22/17 Page 2 of 13 PageID #: 1347
`
`(19) United States
`(12) Reissued Patent
`Yamaguchi
`
`(54) MOS IMAGE PICK-UP DEVICE AND
`CAMERA INCORPORATING THE SAME
`_
`.
`.
`(75) Inventor. Takuml Yamaguchl, Kyoto (JP)
`(73) Ass1gnee: Panasonic Corporation, Osaka (JP)
`
`g5; 91131111
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`1 e :
`
`ar. ,
`Related US. Patent Documents
`E221; sugaotgm NO _
`7 205 593
`Issued "
`‘Pr i7 2007
`'
`_
`'
`’
`NO"
`31/241359?) 02
`P'
`’
`
`'
`(51) Int. Cl.
`H01L 31/103
`
`(2006.01)
`
`US. Cl- ............................. ..
`257/374; 257/399; 257/446
`(58) Field of Classi?cation Search ................. .. 257/292
`See application ?le for complete search history.
`
`(56)
`
`References Cited
`
`U'S' PATENT DOCUMENTS
`4,295,055 A 10/ 1981 Takemoto et a1.
`4,841,369 A
`6/1989 NTShiZaWa et a1~
`5,761,125 A
`6/1998 Hlmenf)
`2
`$1 * 1%;
`gimémya
`6’255’680 Bl
`7/2001 Nalzas?igg """"""""" "
`6’407’417 B1
`6/2002 Nagata et a1
`634483104 B1 * 9/2002 Watanabe .. ................ .. 438/60
`
`438/433
`
`6,465,862 B1 4 10/2002 Harris _ _ _ _ _ _ _ _ _ _ _ _
`6,472,699 B1 * 10/ 2002 Sugiyama er a1,
`6,576,940 B2 * 6/2003 Maeda . . . . . . . . . . .
`
`_ _ _ __ 257/463
`2 57/292
`. . . .. 257/292
`
`JP
`JP
`JP
`JP
`JP
`g
`JP
`JP
`
`FOREIGN PATENT DOCUMENTS
`63-13581
`1/1988
`63-153971
`6/1988
`64-44178
`2/1939
`6440615
`5/1994
`8'055488
`2; 1996
`41‘
`8/1999
`10/1999
`
`ll-23888l
`11-274461
`
`18
`
`1 B
`
`13
`12
`r—*—\r \
`1 7
`18
`
`USO0RE41867E
`
`US RE41,867 E
`(10) Patent Number:
`(45) Date of Reissued Patent:
`Oct. 26, 2010
`
`JP
`JP
`JP
`JP
`JP
`8
`
`11-313257
`11345957
`ll-34633l
`2001007309
`2001-18944 1
`222511222;
`
`11/1999
`12/1999
`12 1999
`H2001
`7/2001
`2522;
`
`OTHER PUBLICATIONS
`Partial English Translation of: Hiroyuki Tango “Semicon
`ductor Process Technology” published by Baifukan, Nov.
`30, 1998, pp. 39*44.
`T. liZuka, “CMOS technology and integration capability”, in
`Design of CMOS Super LSI, First published by Baihuukan
`on Apr. 25, 1989, (third on Nov. 20, 1991).
`Japanese Of?ce Action, Dec. 16, 2004.
`
`* Cited
`
`examiner
`
`Prlmary Exam/"aileron? Jackson, 11
`(74) A210" "6% Agent! or F 1'’ miHamre> Schumann’ Mueller
`& Larson, PC.
`(57)
`
`ABSTRACT
`
`A MOS image pick-up device including a semiconductor
`substrate, an imaging region formed on the semiconductor
`substrate by arraying plural unit pixels, and a peripheral cir
`cuit region including a driving circuit for operating the imag
`ing region formed on the semiconductor substrate; the unit
`pixels include a photodiode, MOS (metal-oxide
`semiconductor) transistors and a ?rst device-isolation
`P0111011; the_PeriPh?ra1 099111‘ @gion 11101119“ a 5699119
`
`dev1ce-1solat1on port1on for isolating devices 1n the driving
`circuit; Wherein each of the ?rst device-isolation portion and
`the second device-isolation portion is at least one portion
`selected from an electrically insulating ?lm formed on the
`substrate in order not to erode the substrate, a electrically
`insulating ?lm formed on the substrate so as to erode the
`substrate to a depth ranging from 1 nm to 50 nm, and an
`impurity diffusion region formed Within the substrate. The
`MOS image pick-up device is incorporated in a camera.
`Thereby, devices are isolated betWeen MOS transistors, and
`noise caused by leakage current is decreased.
`
`12 Claims, 6 Drawing Sheets
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`Case 1:16-cv-00290-MN Document 45-7 Filed 11/22/17 Page 3 of 13 PageID #: 1348
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`US. Patent
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`0a. 26, 2010
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`Sheet 1 of6
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`Case 1:16-cv-00290-MN Document 45-7 Filed 11/22/17 Page 4 of 13 PageID #: 1349
`Case 1:16-cv-00290-MN Document 45-7 Filed 11/22/17 Page 4 of 13 PageID #: 1349
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`US. Patent
`
`Oct. 26, 2010
`
`Sheet 2 of6
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`US RE41,867 E
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`Case 1:16-cv-00290-MN Document 45-7 Filed 11/22/17 Page 5 of 13 PageID #: 1350
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`US. Patent
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`0a. 26, 2010
`
`Sheet 3 of6
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`US RE41,867 E
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`Case 1:16-cv-00290-MN Document 45-7 Filed 11/22/17 Page 6 of 13 PageID #: 1351
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`US. Patent
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`0a. 26, 2010
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`Case 1:16-cv-00290-MN Document 45-7 Filed 11/22/17 Page 7 of 13 PageID #: 1352
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`US. Patent
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`0a. 26, 2010
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`Sheet 5 of6
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`US RE41,867 E
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`PRIOR ART
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`Case 1:16-cv-00290-MN Document 45-7 Filed 11/22/17 Page 8 of 13 PageID #: 1353
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`US. Patent
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`0a. 26, 2010
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`Sheet 6 of6
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`US RE41,867 E
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`Case 1:16-cv-00290-MN Document 45-7 Filed 11/22/17 Page 9 of 13 PageID #: 1354
`
`US RE41,867 E
`
`1
`MOS IMAGE PICK-UP DEVICE AND
`CAMERA INCORPORATING THE SAME
`
`Matter enclosed in heavy brackets [ ] appears in the
`original patent but forms no part of this reissue speci?ca
`tion; matter printed in italics indicates the additions
`made by reissue.
`
`FIELD OF THE INVENTION
`
`The present invention relates to a MOS image pick-up
`device that is used for a digital camera or the like, and a
`camera incorporating the same.
`
`BACKGROUND OF THE INVENTION
`
`2
`example, in a CMOS transistor shown in FIG. 4, the oxide
`?lms 27 used for the device-isolation portions are formed by
`thermally oxidizing the substrate 21, and thus they erode the
`substrate 21 by approximately half of the ?lm thickness. In
`the CMOS transistor shown in FIG. 5, the oxide ?lms 28
`used for the device-isolation portions ?ll trenches formed on
`the substrate 21, so that the ?lms erode the substrate 21 by
`their entire thickness. Since the substrate will be subjected to
`a great stress at parts eroded by the oxide ?lms in the device
`isolation portions, a large leakage current will occur. When
`the device-isolating structure of the CMOS transistor is used
`for an imaging region, noise due to the leakage current will
`be increased considerably.
`
`SUMMARY OF THE INVENTION
`For solving the above-described problems in the conven
`tional techniques, the present invention provides a MOS
`image pick-up device that decreases noise caused by leakage
`current, and also a camera using the MOS image pick-up
`device.
`For achieving the above-described object, a MOS image
`pick-up device according to the present invention has a semi
`conductor substrate, an imaging region formed on the semi
`conductor substrate by arraying plural unit pixels, and a
`peripheral circuit region including a driving circuit for oper
`ating the imaging region formed on the semiconductor
`substrate, wherein each unit pixel has a photodiode, MOS
`(metal-oxide-semiconductor) transistors and a ?rst device
`isolation portion, and the peripheral circuit region includes a
`second device-isolation portion for isolating devices in the
`driving circuit. The MOS image pick-up device is character
`ized in that each of the ?rst device-isolation portion and the
`second device-isolation portion is at least one selected from:
`A) an electrically isolating ?lm formed on the substrate in
`order not to erode the substrate; B) an electrically insulating
`?lm formed on the substrate so as to have a depth eroding the
`substrate in a range of 1 nm to 50 nm; and C) an impurity
`diffusion region formed within the substrate.
`Next, a camera according to the present invention incor
`porates a MOS image pick-up device that has a semiconduc
`tor substrate, an imaging region formed on the semiconduc
`tor substrate by arraying plural unit pixels, and a peripheral
`circuit region including a driving circuit for operating the
`imaging region formed on the semiconductor substrate,
`wherein each unit pixel has a photodiode, MOS (metal-oxide
`semiconductor) transistors and a ?rst device-isolation
`portion, and the peripheral circuit region includes a second
`device-isolation portion for isolating devices in the driving
`circuit. The camera is characterized in that each of the ?rst
`device-isolation portion and the second device-isolation por
`tion is at least one selected from: A) an electrically isolating
`?lm formed on the substrate in order not to erode the sub
`strate; B) an electrically insulating ?lm formed on the sub
`strate so as to have a depth eroding the substrate in a range of
`1 nm to 50 nm; and C) an impurity diffusion region formed
`within the substrate.
`In the present invention, the ‘?rst device-isolation por
`tion’ is formed to electrically isolate devices existing in a
`pixel.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1A is a cross-sectional view showing an example of
`device-isolation portions according to a ?rst embodiment of
`the present invention.
`FIG. 1B is a cross-sectional view showing an example of
`device-isolation portions according to a second embodi
`ment.
`
`A MOS image pick-up device denotes an image sensor
`that ampli?es and reads signals of respective pixels by using
`amplifying circuits including MOS transistors formed on the
`respective pixels. Recently, such MOS image pick-up
`devices, particularly, so-called CMOS (complementary
`MOS) image sensors manufactured in a CMOS process,
`have been marked as image-inputting devices in portable
`apparatuses such as miniature cameras for PCs, due to the
`merits, e.g., they require low voltages and consume less
`power, and the sensors can be integrated with peripheral
`circuits so as to form a one-chip device.
`In a conventional MOS image pick-up device, every cir
`cuit in the peripheral circuit region is designed using a
`CMOS technique to apply both n-channel MOS transistors
`and p-channel MOS transistors. In the imaging region, all of
`the MOS transistors composing each pixel are n-channel
`MOS transistors. In general, the n-channel MOS transistors
`composing the pixel are identi?ed with n-channel MOS tran
`sistors used in the peripheral circuit region.
`FIG. 4 is a cross-sectional view showing a structure of a
`CMOS transistor used for a peripheral circuit region of a
`conventional MOS image pick-up device. In a semiconduc
`tor substrate 21, an n-type well 26 and a p-type well 25 are
`formed. A p-channel MOS transistor 22 is formed in the
`n-type well 26, and an n-channel MOS transistor 23 is
`formed in the p-type well 25. These transistors are isolated
`electrically from each other by device-isolation portions 24.
`The device-isolation portions 24 are oxide ?lms 27 formed
`by LOCOS (local oxidation of silicon). For further
`miniaturization, oxide ?lms 28 formed by STI (shallow
`trench isolation) are used for the electron-isolating portions
`as shown in FIG. 5.
`Since the MOS image pick-up device includes an ampli
`fying circuit in each pixel as described above, it can amplify
`weak signals so as to realize high sensitivity. On the other
`hand, when a large amount of current leaks into the
`photodiode, the leakage current may be ampli?ed and cause
`a considerable noise.
`In the above-described conventional MOS image pick-up
`device, n-channel MOS transistors composing the pixel are
`regarded as identical in the structure to the n-channel MOS
`transistors used in the peripheral circuit region, i.e..
`n-channel MOS transistors of a CMOS transistor. Moreover,
`the device-isolation portions among the transistors are con
`sidered to have a common structure in the imaging region
`and the peripheral region.
`However, the CMOS transistors used for the peripheral
`circuit region are developed in a trend for miniaturizing
`semiconductor LSI. Therefore, the main object in develop
`ment of the CMOS transistors is a high-speed process, while
`substantially no attention is paid for leakage current. For
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`Case 1:16-cv-00290-MN Document 45-7 Filed 11/22/17 Page 10 of 13 PageID #: 1355
`
`US RE41,867 E
`
`3
`FIG. 2 is a schematic vieW showing a con?guration of a
`MOS image pick-up device according to the present inven
`tion.
`FIG. 3 is a circuit diagram shoWing an example of a
`dynamic circuit that can be used for a driving circuit of a
`MOS image pick-up device of the present invention.
`FIG. 4 is a cross-sectional vieW shoWing a structure of a
`CMOS transistor and its device-isolation portions for com
`posing a conventional MOS image pick-up device.
`FIG. 5 is a cross-sectional vieW shoWing a structure of a
`CMOS transistor and its device-isolation portions for com
`posing a conventional MOS image pick-up device.
`FIG. 6 is a graph for comparing leakage currents that vary
`depending on isolation oxide ?lms in the ?rst embodiment
`of the present invention.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`In the present invention, each of the ?rst device-isolation
`portion and the second device-isolation portion is at least
`one of: A) an electrically isolating ?lm formed on the sub
`strate in order not to erode the substrate; B) an electrically
`insulating ?lm formed on the substrate so as to have a depth
`eroding the substrate in a range of 1 nm to 50 nm; and C) an
`impurity diffusion region formed Within the substrate.
`Therefore, stress applied to the substrate is decreased and the
`leakage current can be inhibited. As a result, noise caused by
`the leakage current can be decreased. When the device
`isolation portion is a ?lm of B), stress applied to the device
`isolation portion can be decreased and the leakage current
`can be inhibited since the erosion depth into the substrate is
`shalloW, i.e., it is controlled Within a range of 1 nm to 50 nm.
`It is preferable in the MOS image pick-up device that the
`impurity diffusion region is formed by ion implantation.
`It is preferable in the MOS image pick-up device that the
`insulating ?lm has a thickness ranging from 1 nm to 500 nm.
`It is preferable in the MOS image pick-up device that in
`the imaging region the ?rst device-isolation portion formed
`adjacent to the photodiode is composed of an impurity diffu
`sion region formed in the substrate.
`It is preferable in the MOS image pick-up device that at
`least one part of the driving circuit is a dynamic circuit,
`thereby decreasing the energy consumption.
`It is preferable in the MOS image pick-up device that a
`dark current inhibiting layer is formed in the surface layer of
`the photodiode, thereby inhibiting leakage current occurring
`due to defects in the vicinity of the substrate surface on the
`photodiode.
`As described above, according to a MOS image pick-up
`device of the present invention Where device-isolation por
`tions among MOS transistors have a particular structure,
`noise caused by leakage current can be decreased.
`The details Will be described beloW With reference to the
`attached draWings.
`FIG. 2 shoWs an example of a MOS image pick-up device
`of the present invention. This solid-state imaging device has
`an imaging region 7 With plural pixels 6 arranged one
`dimensionally or tWo-dimensionally, and a peripheral circuit
`region arranged around the imaging region.
`This MOS image pick-up device includes, on a semicon
`ductor substrate, an imaging region 7 in Which plural pixels
`6 are arrayed tWo-dimensionally, a vertical shift resistor 8
`and a horiZontal shift resistor 9 for selecting pixels, and a
`timing-generation circuit 10 for feeding pulses necessary for
`the shift resistors (hereinafter, a region other than the imag
`
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`4
`ing region 7 is expressed as ‘a peripheral circuit region’,
`Which includes the vertical shift resistor 8, the horiZontal
`shift resistor 9, and the timing-generation circuit 10). In the
`imaging region 7, each of the pixels 6 is composed of a
`photodiode 1 and four MOS transistors, i.e., a charge
`transferring transistor 2, a resetting transistor 3, an amplify
`ing transistor 4 and a selecting transistor 5. In the peripheral
`circuit region, the vertical shift resistor 8, the horiZontal shift
`resistor 9 and the timing-generation circuit 10 are composed
`by using plural MOS transistors.
`Each of the pixels 6 composing the imaging region 7
`includes the photodiode 1 and the four MOS transistors, i.e.,
`the charge-transferring transistor 2, the resetting transistor 3,
`the amplifying transistor 4 and the selecting transistor 5. The
`charge-transferring transistor 2 uses the photodiode 1 as a
`source, and its drain is electrically connected With a gate of
`the amplifying transistor 4. The amplifying transistor 4 has a
`drain that is electrically connected With a poWer supply volt
`age and a source that is electrically connected With a drain of
`the selecting transistor 5. The resetting transistor 3 has a
`source that is electrically connected With a drain of the
`charge-transferring transistor 2 and also a source that is elec
`trically connected With a poWer supply voltage. The select
`ing transistor 5 has a source connected to an output line.
`The folloWing is a brief explanation about functions of the
`respective transistors. The charge-transferring transistor 2
`transfers signal charge generated due to a photoelectric
`exchange at the photodiode 1 into a detecting portion (the
`drain of the charge-transferring transistor 2). The detecting
`portion stores signal charge and inputs a voltage correspond
`ing to the electric charge into the amplifying transistor 4.
`The amplifying transistor 4 ampli?es the voltage of the
`detecting portion, and the selecting transistor 5 as a sWitch
`for taking out output of the amplifying transistor 4 selects a
`pixel for reading the signal. The resetting transistor 3 dis
`charges the signal electric charge stored in the detecting por
`tion at a predetermined time interval.
`FIG. 1A and FIG. 1B are cross-sectional vieWs shoWing
`examples of MOS transistors and the peripheral structures.
`In each MOS transistor 12, a source 14 and a drain 15 as
`n-type diffusion regions are formed Within a p-type semicon
`ductor substrate 11 (or a p-type Well). Agate electrode 17 is
`formed on a part of the semiconductor substrate 11 through
`an insulating ?lm 16, and the gate electrode 17 is located
`betWeen the source 14 and the drain 15.
`As shoWn in FIGS. 1A and 1B, respective MOS transis
`tors 12 are electrically isolated from each other by device
`isolation portions 13. Each device-isolation portion 13 can
`be con?gured by forming an isolation oxide ?lm 18 on the
`semiconductor substrate 11 as shoWn in FIG. 1A.
`Alternatively, the device-isolation portion 13 can be con?g
`ured by forming an isolation-diffusion region 19 Within the
`semiconductor substrate 11 as shoWn in FIG. 1B.
`Alternatively, both the isolation oxide ?lm 18 and the
`isolation-diffusion region 19 can be formed together. Struc
`tures of the device-isolation portions Will be detailed later.
`The photodiode 1 is an n-type diffusion region formed
`Within the p-type semiconductor substrate (or a p-type Well).
`As described above, the photodiode composes a source of a
`charge-transferring transistor, and similar to the sources for
`other MOS transistors, a device-isolation portion is formed
`in a region adjacent to a photodiode.
`It is further preferable that a p-type diffusion region is
`formed as a dark current inhibiting layer on the surface layer
`part of the n-type diffusion region as a photodiode. In this
`case, it is preferable that the dark current inhibiting layer
`
`

`

`Case 1:16-cv-00290-MN Document 45-7 Filed 11/22/17 Page 11 of 13 PageID #: 1356
`
`US RE41,867 E
`
`5
`extends to the device-isolation portion formed adjacent to
`the photodiode. That is, When the device-isolation portion is
`composed of an isolation oxide ?lm, preferably, it extends
`beloW the isolation oxide ?lm. When the device-isolation
`portion is composed of an isolation-diffusion region, the
`dark current inhibiting layer preferably extends into the
`isolation-diffusion region.
`Although an n-channel MOS transistor is shoWn as an
`example of MOS transistors composing the respective
`pixels, it is also possible to use a p-channel MOS transistor.
`In this case, the MOS transistor has a structure Where a
`source as a p-type diffusion region and a drain are formed in
`an n-type semiconductor substrate (or n-type Well). The pho
`todiode is composed of a p-type diffusion region, and the
`dark current inhibiting layer is composed of an n-type diffu
`sion region.
`As shoWn in FIG. 2, a peripheral circuit region includes a
`horizontal shift resistor 8 and a vertical shift resistor 9 for
`pixel selection, and a driving circuit such as a timing
`generation circuit 10 for feeding pulses necessary for opera
`tion of the shift resistors.
`In the peripheral circuit, it is preferable that the driving
`circuit is composed of a dynamic circuit for decreasing
`poWer consumption. FIG. 3 is a circuit diagram shoWing an
`example of a dynamic circuit available for the horiZontal
`shift resistor and the vertical shift resistor.
`Since a typical dynamic circuit retains data dynamically
`in capacitors (20a, 20b and 20c in FIG. 3), a great leakage
`current can destroy data. HoWever, this embodiment can
`solve this problem since a structure for decreasing the leak
`age current is used for the device-isolation portions that iso
`late MOS transistors of the driving circuit.
`A driving circuit contains plural MOS transistors, and the
`MOS transistors are electrically isolated from each other by
`device-isolation portions. The device-isolation portions can
`be con?gured similar to the device-isolation portions in an
`imaging region. That is, each device-isolation portion can be
`con?gured by forming an isolation oxide ?lm on the semi
`conductor substrate; forming an isolation-diffusion region
`Within the semiconductor substrate; or forming both the iso
`lation oxide ?lm and the isolation-diffusion region together.
`The structures of the device-isolation portions Will be
`detailed later.
`It is further preferable that all the MOS transistors com
`posing pixels of the imaging region and the MOS transistors
`composing the driving circuit in the peripheral circuit region
`have the same structure, so that the manufacturing process
`can be simpli?ed.
`The folloWing description is about device-isolation por
`tions among MOS transistors in the imaging region and the
`peripheral circuit region.
`As described above, both the imaging region and the
`peripheral circuit region have device-isolation portions con
`?gured by forming an isolation oxide ?lm on a semiconduc
`tor substrate (hereinafter, referred to as ‘a ?rst
`embodiment’), or by forming an isolation-diffusion region
`Within a semiconductor substrate (hereinafter, referred to as
`‘a second embodiment’).
`FIG. 1A is a cross-sectional vieW shoWing device
`isolation portions 13 in the ?rst embodiment. For each of the
`device-isolation portions 13, an isolation oxide ?lm 18 is
`formed on a semiconductor substrate 11. The isolation oxide
`?lm 18 does not erode the semiconductor substrate 11, and it
`is, for example, a deposited ?lm formed on the ?at surface of
`the semiconductor substrate. Such an isolation oxide ?lm 18
`can be formed, for example, by a CVD method.
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`FIG. 6 is a graph for comparing leakage currents that vary
`depending on isolation oxide ?lms.
`When the isolation oxide ?lm 18 has a thickness as large
`as 800 nm (‘B’ in FIG. 6), stress Will be concentrated to end
`portions of the isolation oxide ?lm 18 at the interface
`betWeen the isolation oxide ?lm 18 and either the source 14
`or the drain 15, due to an in?uence of heat treatment or the
`like carried out after formation of the isolation oxide ?lm 18.
`As a result, the stress becomes greater and the leakage cur
`rent is increased to 1.3 times in a comparison With a case of
`an oxide ?lm 27 formed by LOCOS (local oxidation of
`silicon) illustrated as ‘A’ in FIG. 6. Preferably, the ?lm thick
`ness is decreased to not more than 500 nm, preferably not
`more than 400 nm, more preferably not more than 250 nm,
`so that the leakage current at the end portions of the isolation
`oxide ?lm 18 can be decreased in comparison With the leak
`age current of the oxide ?lm 27 formed by LOCOS (local
`oxidation of silicon). When the thickness of the isolation
`oxide ?lm 18 is 250 nm (‘C’ in FIG. 6), the leakage current is
`as loW as 0.8 times.
`Since an LSl of a typical CMOS has a GND poWer source
`in the unit cells, current can leak from GND to VDD (e.g.,
`3V), passing beneath the isolation oxide ?lm, and thus, the
`isolation oxide ?lm should be thickened to be about 300 nm
`for improving voltage endurance for device-isolation. On the
`other hand, since an ampli?cation type unit pixel does not
`alWays require a GND poWer source in the pixel, the thick
`ness of the isolation oxide ?lm 18 can be decreased to a
`range of 4 nm to 250 nm, thereby decreasing the leakage
`current of the isolation oxide ?lm 18.
`Furthermore, by annealing in a hydrogen atmosphere after
`formation of the isolation oxide ?lm 18, defects caused by
`stress at the end portions of the isolation oxide ?lm 18 can be
`corrected. This can further decrease the leakage current to
`0.4 times (‘E’ in FIG. 6).
`In the insulating ?lm shoWn in FIG. 1A, the isolation
`oxide ?lm 18 is formed on the semiconductor substrate 11
`together With an insulating ?lm in order not to erode the
`substrate. A test result shoWs that When a depth that the
`isolation oxide ?lm 18 erodes the semiconductor substrate
`11 is 50 nm or less, annealing in a hydrogen atmosphere can
`decrease leakage current, i.e., the leakage current indicated
`as D in FIG. 6 is 0.6 times the leakage current in the oxide
`?lm 27 formed by LOCOS (local oxidation of silicon).
`FIG. 1B is a cross-sectional vieW of device-isolation por
`tions in a second embodiment. Each device-isolation portion
`13 includes an isolation-diffusion region 19 formed Within
`the semiconductor substrate 11. According to the second
`embodiment, the effect of inhibiting leakage current is fur
`ther improved in comparison With the ?rst embodiment. The
`isolation-diffusion regions 19 Will be p-type diffusion
`regions for isolating n-channel MOS transistors, While
`n-type diffusion regions are used for isolating p-type MOS
`transistors. The isolation-diffusion regions 19 can be formed
`by, for example, ion-implanting p-type or n-type impurities
`into a semiconductor substrate.
`The impurity concentration and diffusion depth of the
`isolation-diffusion regions 19 Will not be limited speci?cally
`as long as the MOS transistor 12 can be isolated electrically.
`The impurity concentration is, for example, 1014 cm'3 to
`1022 cm_3, preferably 1015 cm-3 to 1020 cm_3, further pref
`erably 1017 cm'3 to 1020 cm_3. The diffusion depth is, for
`example, more than 0 pm and not more than 7 um, prefer
`ably more than 0 pm and not more than 2 pm, further prefer
`ably more than 0 pm and not more than 1 um.
`The device-isolation portion can have a structure for using
`both an isolation oxide ?lm and an isolation-diffusion region
`
`

`

`Case 1:16-cv-00290-MN Document 45-7 Filed 11/22/17 Page 12 of 13 PageID #: 1357
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`US RE41,867 E
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`7
`(hereinafter, the structure is referred to as ‘a third
`embodiment’). In the structure, even When leakage current
`occurs at the interface betWeen the isolation oxide ?lm and
`the semiconductor substrate, this leakage current can be
`recontacted in the isolation-diffusion region, thereby
`enhancing the effect of decreasing the leakage current.
`For the imaging region, it is preferable that the second
`embodiment is applied for the structure of the device
`isolation portion adjacent to the photodiode, so that an excel
`lent effect is obtained in inhibiting leakage current. Though
`the second embodiment can be used for the other device
`isolation portion in the imaging region, use of either the ?rst
`or third embodiment is particularly preferable, since the
`amplifying circuit in each pixel can be operated at high
`speed.
`In the peripheral circuit region, it is preferable to use
`either the ?rst or the third embodiment for the structure of
`the device-isolation portion, since the driving circuit can be
`operated at high speed.
`The device-isolation portion in the imaging region and the
`device-isolation portion in the peripheral circuit region can
`be selected separately from the ?rst, second and third
`embodiments. Preferred examples of the combinations are
`described beloW.
`In a ?rst combination, the device-isolation portion in the
`imaging region and that in the peripheral circuit region have
`the same structure. In this case, though the second embodi
`ment can be used for the device-isolation portion, the ?rst or
`third embodiment is preferred particularly.
`In a second combination, the second embodiment is used
`for the device-isolation portion in the imaging region While
`the ?rst or third embodiment is used for the device-isolation
`portion in the peripheral circuit region. This structure can
`decrease leakage current leaking into the photodiode and
`realiZe a high-speed operation of the driving circuit.
`In a third combination, the second embodiment is used for
`the device-isolation portion adjacent to the photodiode in the
`imaging region, and either the ?rst or the third embodiment
`is used for the other device-isolation portions, and the ?rst or
`the third embodiment is used for the device-isolation portion
`in the peripheral circuit region.
`Accordingly, leakage current leaking into the photodiode
`can be decreased, and the driving circuit and the amplifying
`circuit in the pixel can be operated at high speed.
`What is claimed is:
`1. A MOS (metal-oxide-semiconductor) image pick-up
`device comprising:
`a semiconductor substrate,
`an imaging region formed on the semiconductor substrate
`by arraying plural unit pixels, and
`a peripheral circuit region comprising a driving circuit for
`operating the imaging region formed on the semicon
`ductor substrate;
`Where each of the unit pixels comprises: a photodiode,
`MOS transistors, and a ?rst device-isolation portion
`comprising a portion next to the photodiode and a por
`tion not next to the photodiode, and
`the peripheral circuit region comprises a second device
`isolation portion for isolating devices in the driving
`circuit,
`Wherein the folloWing are satis?ed:
`I. each of the ?rst device-isolation portion not next to the
`photodiode and the second device-isolation portion has
`a structure comprising:
`A. an electrically insulating ?lm formed on a surface of
`the substrate so as to erode the substrate to a depth in
`a range ofl nm to 50 nm, or
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`B. both an electrically insulating ?lm formed on a sur
`face of the substrate so as to erode the substrate to a
`depth in a range of 1 nm to 50 nm and an impurity
`diffusion region formed Within the substrate, and
`II. each of the ?rst device-isolation portions next to the
`photodiode has a structure consisting of only an impu
`rity diffusion region formed Within the substrate
`directly under the substrate surface.
`2. The MOS image pick-up device according to claim 1,
`Wherein the impurity diffusion region is formed by ion
`implantation.
`3. The MOS image pick-up device according to claim 1,
`Wherein at least one part of the driving circuit is a dynamic
`circuit.
`4. The MOS image pick-up device according to claim 1,
`Wherein the photodiode has a surface portion having a dark
`current inhibiting layer.
`5. The MOS image pick-up device according to claim 1,
`Wherein the ?rst device-isolation portion and the second
`device-isolation portion are formed by annealing in a hydro
`gen atmosphere.
`6. A camera comprising a MOS (metal-oxide
`semiconductor) image pick-up device comprising:
`a semiconductor substrate,
`an imaging region formed on the semiconductor substrate
`by arraying plural unit pixels, and
`a peripheral circuit region comprising a driving circuit for
`operating the imaging region formed on the semicon
`ductor substrate;
`Where each of the unit pixels comprises: a photodiode,
`MOS transistors, and a ?rst device-isolation portion
`comprising a p