Case 1:16-cv-00290-MN Document 1-7 Filed 04/22/16 Page 1 of 24 PageID #: 205
`Case 1:16-cv-OO290-MN Document 1-7 Filed 04/22/16 Page 1 of 24 PageID #: 205
`
`EXHIBIT G
`
`
`
`

`

`Case 1:16-cv-00290-MN Document 1-7 Filed 04/22/16 Page 2 of 24 PageID #: 206
`
`US008378401B2
`
`(12) Ulllted States Patent
`Mori et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 8,378,401 B2
`Feb. 19, 2013
`
`(54) SOLID STATE IMAGING APPARATUS,
`METHOD FOR DRIVING THE SAME AND
`CAMERA USING THE SAME
`
`(75) Inventors: Mitsuyoshi Mori, Kyoto (JP); Takumi
`Yamaguchi, Kyoto (JP); Takahiko
`Murata’ Osaka (JP)
`
`(73) Assignee: Panasonic Corporation, Osaka (JP)
`
`( * ) Notice:
`
`Subject‘ to any disclaimer, the term of this
`patent is extended or adjusted under 35
`USC 154(b) by 0 days.
`
`EP
`EP
`
`a
`
`a
`
`6,091,449 A
`Q1
`6,352,869 B1
`6,541,794 B1
`6,552,323 B2
`6,657,665 B1
`6,734,906 B1 *
`
`0 es e a .
`
`7/2000 Matsunaga et al.
`g?lccllash t l
`3/2002 Guidash
`4/2003 Patterson et al.
`4/2003 Guidash et a1,
`12/2003 Guidash
`5/2004 Hashimoto ................. .. 348/302
`(Continued)
`
`FOREIGN PATENT DOCUMENTS
`0 845 900 A1
`@1998
`0 926 738 A2
`@999
`(Continued)
`
`OTHER PUBLICATIONS
`
`(21) Appl. No.: 13/335,537
`
`(22) Filed:
`
`Dec- 221 2011
`
`(65)
`
`Prior Publication Data
`US 2012/0098040 A1
`Apr. 26, 2012
`
`Related US. Application Data
`
`(60) Division of application No. 12/178,250, ?led on Jul.
`23, 2008, noW Pat. No. 8,106,431, Which is a
`continuation of application No. 10/706,918, ?led on
`Nov. 14, 2003, noW Pat. No. 7,436,010.
`
`(30)
`
`Foreign Application priority Data
`
`Feb. 13, 2003
`
`(JP) ............................... .. 2003-034692
`
`(51) Int- Cl-
`(2012-01)
`H 01L 31/062
`(52) US. Cl. . 257/292; 257/223; 257/444; 257/E27.132;
`257/E27.139
`(58) Field of Classi?cation Search ................ .. 257/223,
`257/291*293,443*445, E27.132,E27.139
`See application ?le for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,708,263 A
`1/1998 Wong
`5,955,753 A
`9/1999 Takahashi
`
`United States Of?ce Action issued in US. Appl. No. 12/202,804,
`mailed Dec. 6, 2010.
`
`(Commued)
`
`_
`Prlmary Exammer i John? Ingham
`(74) Attorney, Agent, or Fzrm * McDermottW1ll & Emery
`LLP
`
`(57)
`
`ABSTRACT
`.
`.
`.
`.
`.
`A sol1d state 1mag1ng apparatus includes: a plurality of pho
`toelectric conversion cells each including a plurality of pho
`toelectric sections arranged in an array of at least tWo roWs
`and tWo columns; a plurality of ?oating diffusion sections
`each being connected to each of ones of the photoelectric
`sections Which are included in the same roW of each said
`photoelectric conversion cell via each of a plurality of transfer
`transistors, and being shared by said ones ofthe photoelectric
`sections; a plurality of read-out lines each being selectively
`connected to at least tWo of the transfer transistors; and a
`plurality of piXel ampli?er transistors each detecting and
`outputting the potential of each said the ?oating diffusion
`section. Charges of the photoelectric conversion sections
`each being connected to one of the read-out lines and being
`read out by the transfer transistors are read out by different
`?oating diffusion sections.
`
`42 Claims, 10 Drawing Sheets
`
`
`
`4o 5
`
`
`
`7 2. _.._ .. .11.... 8
`
`FOURTH ROW
`3
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`
`ROW DIRECTION
`
`21
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`
`

`

`Case 1:16-cv-00290-MN Document 1-7 Filed 04/22/16 Page 3 of 24 PageID #: 207
`
`US 8,378,401 B2
`Page 2
`
`US. PATENT DOCUMENTS
`
`12/2005 Hashimoto et a1.
`6,977,684 B1
`2001/0052941 A1 12/2001 Matsunaga et a1.
`2002/0018131 A1
`2/2002 Kochi
`2002/ 0024068 A1
`2/ 2002 Shinohara
`2002/0145582 A1 10/2002 YamaZaki et al.
`2006/0001751 A1
`1/2006 Abe et al.
`
`EP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`KR
`W0
`
`A
`
`FOREIGN PATENT DOCUMENTS
`A2 11/1999
`0 954 032
`2/1997
`09-046596
`4/1999
`11-097662
`7/1999
`11-195776
`11/1999
`11-312800
`1/2000
`2000-12821
`2/2000
`2000-059697
`3/2000
`2000-78475
`5/2000
`2000-152086
`8/2000
`2000-224482
`8/2000
`A
`2000-224482
`A 10/2001
`2001-298177
`A 11/2001
`2001-326856
`3/2002
`2002-077731
`6/2004
`2004-172950
`8/2000
`2000-0052598
`2/1997
`WO 97/07630
`
`A
`
`OTHER PUBLICATIONS
`United States Of?ce Action issued in US. Appl. No. 12/202,804
`dated Jun. 21, 2011.
`Japanese Decision of Rejection, W/ English translation thereof,
`issued in Japanese Patent Application No. JP 2006-343810 dated
`Mar. 9, 2010.
`Japanese Decision to Dismiss the Amendment, W/ English translation
`thereof, issued in Japanese Patent Application No. JP 2006-343810
`dated Mar. 9, 2010.
`United States Notice of Allowance issued in US. Appl. No.
`12/178,250, mailed Sep. 30, 2011.
`United States Notice of Allowance issued in US. Appl. No.
`10/706,918, mailed Jul. 9, 2008.
`Japanese Notice of Reasons for Rejection, W/ English translation
`thereof, issued in Japanese Patent Application No. JP 2006-343810
`dated Oct. 13, 2009.
`Chinese Of?ce Action Issued in corresponding Chinese Patent Appli
`cation No. CN 2003801009766, dated Feb. 2, 2007.
`Japanese Of?ce Action issued in corresponding Japanese Patent
`Application No. JP 2004-034818, dated Oct. 24, 2006.
`White et al., “Characterization of Surface Channel CCD Image
`Arrays at Low Light Levels”, IEEE Journal of Solid State Circuits,
`vol. sc-9, No. 1, Feb. 1974, pp. 1-13.
`
`* cited by examiner
`
`

`

`Case 1:16-cv-00290-MN Document 1-7 Filed 04/22/16 Page 4 of 24 PageID #: 208
`
`US. Patent
`
`Feb. 19, 2013
`
`Sheet 1 0110
`
`US 8,378,401 B2
`
`FIG. 1
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`

`Case 1:16-cv-00290-MN Document 1-7 Filed 04/22/16 Page 5 of 24 PageID #: 209
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`US. Patent
`
`Feb. 19, 2013
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`US 8,378,401 B2
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`Case 1:16-cv-00290-MN Document 1-7 Filed 04/22/16 Page 6 of 24 PageID #: 210
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`US. Patent
`
`Feb. 19, 2013
`
`Sheet 3 0f 10
`
`US 8,378,401 B2
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`Case 1:16-cv-00290-MN Document 1-7 Filed 04/22/16 Page 7 of 24 PageID #: 211
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`US. Patent
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`Feb. 19, 2013
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`US 8,378,401 B2
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`Case 1:16-cv-00290-MN Document 1-7 Filed 04/22/16 Page 8 of 24 PageID #: 212
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`US. Patent
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`Feb. 19, 2013
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`US 8,378,401 B2
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`Case 1:16-cv-00290-MN Document 1-7 Filed 04/22/16 Page 9 of 24 PageID #: 213
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`US. Patent
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`Feb. 19, 2013
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`Case 1:16-cv-00290-MN Document 1-7 Filed 04/22/16 Page 10 of 24 PageID #: 214
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`US. Patent
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`Case 1:16-cv-00290-MN Document 1-7 Filed 04/22/16 Page 11 of 24 PageID #: 215
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`US. Patent
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`Feb. 19, 2013
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`US 8,378,401 B2
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`Case 1:16-cv-00290-MN Document 1-7 Filed 04/22/16 Page 13 of 24 PageID #: 217
`
`US. Patent
`
`Feb. 19, 2013
`
`Sheet 10 0f 10
`
`US 8,378,401 B2
`
`FIG. 10
`PRIOR ART
`
`L 113
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`Case 1:16-cv-00290-MN Document 1-7 Filed 04/22/16 Page 14 of 24 PageID #: 218
`
`US 8,378,401 B2
`
`1
`SOLID STATE IMAGING APPARATUS,
`METHOD FOR DRIVING THE SAME AND
`CAMERA USING THE SAME
`
`RELATED APPLICATIONS
`
`This application is a Divisional of US. application Ser. No.
`12/178,250, ?led on Jul. 23, 2008 now US. Pat. No. 8,106,
`431, Which is a Continuation of US. application Ser. No.
`10/706,918, ?led on Nov. 14, 2003, now US. Pat. No. 7,436,
`010, claiming priority of Japanese Patent Application No.
`2003-034692, ?led on Feb. 13, 2003, the entire contents of
`each of Which are hereby incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a solid state imaging appa
`ratus in Which a plurality of photoelectric conversion sections
`are arranged in an array, a method for driving the solid state
`imaging apparatus and a camera using the solid state imaging
`apparatus.
`FIG. 10 is a diagram illustrating a general circuit con?gu
`ration for a MOS type image sensor, i.e., a knoWn solid
`imaging apparatus (e. g., see M. H. White, D. R. Lange, F. C.
`Blaha and I. A. Mach, “Characterization of Surface Channel
`CCD Image Arrays at LoW Light Levels”, IEEE J. Solid-State
`Circuits, SC-9, pp. 1-13 (1974)).
`As shoWn in FIG. 10, a photoelectric conversion cell
`includes a photodiode (PD) section 101, a transfer transistor
`113, a reset transistor 122, a pixel ampli?er transistor 123, a
`select transistor 152, a ?oating diffusion (FD) section 109, a
`poWer supply line 131 and an output signal line 138.
`The PD section 101 of Which the anode is grounded is
`connected to the drain of the transfer transistor 113 at the
`cathode. The source of the transfer transistor 113 is connected
`to the respective sources of the FD section 109, the gate of the
`pixel ampli?er transistor 123 and the source of the reset
`transistor 122. The gate of the transfer transistor 113 is con
`nected to a read-out line 134. The reset transistor 122 Which
`receives a reset signal 137 at the gate includes a drain con
`nected to the drain of the pixel ampli?er transistor 123 and the
`poWer supply line 131. The source of the pixel ampli?er
`transistor 123 is connected to the drain of the select transistor
`152. The select transistor 152 receives a selection signal SEL
`at the gate and includes a source connected to the output
`signal line 138.
`The output signal line 138 is connected to the source of a
`load gate 125. The gate of the load gate 125 is connected to a
`load gate line 140 thereof and the drain is connected to a
`source poWer supply line 141.
`In this con?guration, a predetermined voltage is applied to
`the load gate line 140 so that the load gate 125 becomes a
`constant current source, and then the transfer transistor 1 13 is
`temporarily turned ON to transfer charge photoelectric-con
`verted in the PD section 101 to the FD section 109. Then, the
`potential of the PD section 101 is detected by the pixel ampli
`?er transistor 123. In this case, by turning the select transistor
`152 ON, signal charge can be detected through the output
`signal line 138.
`HoWever, in the knoWn solid state apparatus, four transis
`tors 113, 122, 123 and 152 and ?ve lines 131, 134, 137, 138
`and 150 are required for total in each photoelectric conversion
`cell. Accordingly, the areas of transistor and line sections in a
`cell are increased. For example, if a photoelectric conversion
`cell is designed, assuming that the area of a photoelectric
`conversion cell is 4.1 um><4.1 pm, with the design rule of0.35
`pm, the aperture ratio of the PD section 101 to the photoelec
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`tric conversion cell is only about 5%. Therefore, it is di?icult
`to ensure a suf?ciently large area of opening of the PD section
`101 and also to reduce the siZe of the photoelectric conversion
`cell.
`
`SUMMARY OF THE INVENTION
`
`It is an object of the present invention to solve the above
`described problems and, to reduce, in a FDA (?oating diffu
`sion ampli?er) system, the siZe of a photoelectric conversion
`cell While increasing an aperture area of a photoelectric con
`version section.
`To achieve the above-described object, the present inven
`tion has been devised, so that a con?guration in Which a
`transistor and an interconnect can be shared by a plurality of
`photoelectric conversion (PD) sections is used in a solid state
`imaging apparatus.
`Speci?cally, a ?rst solid sate imaging apparatus includes: a
`plurality of photoelectric conversion cells each including a
`plurality of photoelectric sections arranged in an array of at
`least tWo roWs and tWo columns; a plurality of ?oating diffu
`sion sections each being connected to each of ones of the
`photoelectric sections Which are included in the same roW of
`each said photoelectric conversion cell via each of a plurality
`of transfer transistors, and being shared by said ones of the
`photoelectric sections Which are included in the same roW; a
`plurality of read-out lines each being selectively connected to
`at least tWo of the transfer transistors; and a plurality of pixel
`ampli?er transistors each detecting and outputting the poten
`tial of each said the ?oating diffusion section. In the appara
`tus, respective charges of the photoelectric conversion sec
`tions each being connected to one of the read-out lines and
`being read out by the transfer transistors are read out by
`different ?oating diffusion sections.
`In the ?rst solid imaging apparatus, each said ?oating
`diffusion section is shared by ones of the photoelectric con
`version sections included in the same roW, and furthermore,
`respective charges of the photoelectric conversion sections
`each being connected to one of the read-out lines and being
`read out by the transfer transistors are read out by different
`?oating diffusion sections. Thus, the number of read-out lines
`per photoelectric conversion cell becomes 0.5 . As a result, the
`aperture ratio of the photoelectric conversion sections to the
`photoelectric conversion cell can be increased and also the
`siZe of the photoelectric cell can be reduced.
`In the ?rst solid state imaging apparatus, it is preferable
`that each saidread-out line is connected to a transfer transistor
`connected to ones of the photoelectric conversion sections
`Which are included in the same column. Thus, charges of at
`least tWo of said ones of the photoelectric conversion sections
`Which are included in the same column can be output through
`a ?oating diffusion section, a pixel ampli?er transistor and a
`signal line.
`Moreover, in the ?rst solid state imaging apparatus, it is
`preferable that Wherein each said read-out line is connected to
`a transfer transistor connected to ones of the photoelectric
`conversion sections Which are included in tWo adjacent col
`umns, respectively. Thus, charges of at least tWo of said ones
`of the photoelectric conversion sections Which are included in
`tWo adjacent columns, respectively, can be output through a
`?oating diffusion section, a pixel ampli?er transistor and a
`signal line.
`In the ?rst solid state imaging apparatus, it is preferable
`that each said ?oating diffusion section and each said pixel
`ampli?er transistor are shared by a roW Which is read out by a
`transfer transistor connected to one of the read-out line and
`another roW Which is adjacent to the read-out roW.
`
`

`

`Case 1:16-cv-00290-MN Document 1-7 Filed 04/22/16 Page 15 of 24 PageID #: 219
`
`US 8,378,401 B2
`
`3
`It is preferable that the ?rst solid state imaging apparatus
`further includes: a signal line for outputting a signal from
`each said pixel ampli?er transistor to the outside; and a select
`transistor Which is provided betWeen the pixel ampli?er tran
`sistor and the signal line to selectively conduct betWeen the
`pixel ampli?er transistor and the signal line. Thus, charges
`from one of the photoelectric conversion sections Which are
`included in adjacent roWs, respectively, can be detected
`through a shared signal line.
`In the ?rst solid state imaging apparatus, it is preferable
`that each said ?oating diffusion section and each said pixel
`ampli?er transistor are shared by photoelectric conversion
`sections Which are adjacent to each other in the roW direction
`or in the column direction. Thus, the aperture ratio of the
`photoelectric conversion sections to the photoelectric conver
`sion cell can be increased and also the siZe of the photoelectric
`cell can be reduced.
`In the ?rst solid state imaging apparatus, it is preferable
`that in each said ?oating diffusion section, a reset section for
`resetting charge stored in the ?oating diffusion section is
`provided. Thus, it is possible to stop, after charge read out
`from a photoelectric conversion section has been detected by
`an ampli?er, detection of charge by the pixel ampli?er tran
`sistor.
`In the ?rst solid state imaging apparatus, it is preferable
`that the photoelectric conversion sections are arranged so as
`to be spaced apart from one another by a certain distance in
`the roW direction or in the column direction. Thus, a high
`quality image can be obtained from signals read out from the
`photoelectric conversion sections.
`It is preferable that the ?rst solid state imaging apparatus
`further includes a signal processing circuit for processing an
`output signal from each said pixel ampli?er transistor. Thus,
`a high quality image can be obtained.
`In the ?rst solid state imaging apparatus, it is preferable
`that the photoelectric conversion cells are separated from one
`another by a poWer supply line Which also functions as a
`light-shielding ?lm. Thus, a poWer supply line can be formed
`in a different interconnect layer from an interconnect layer in
`Which an output signal line connected to a pixel ampli?er
`transistor is formed. Therefore, the siZe of a photoelectric
`conversion cell can be further reduced and also the aperture
`area can be increased.
`A method for driving a solid state imaging apparatus
`according to the present invention is directed to a method for
`driving the ?rst solid state imaging apparatus of the present
`invention and includes: a ?rst step of transferring, in each said
`photoelectric conversion cell, by a ?rst read-out line of the
`read-out lines, signal charges from ones of the photoelectric
`conversion sections Which are not included in the same roW
`but included in tWo columns adjacent to each other, respec
`tively, to one of the ?oating diffusion sections connected to
`said ones of the photoelectric conversion sections; and a
`second step of transferring, by a second read-out line of the
`read-out lines, signal charges from ones of the photoelectric
`conversion sections Which have not been read out in the ?rst
`step to the same ?oating diffusion section connected to said
`ones of the photoelectric conversion sections as that in the
`?rst step.
`A second solid state imaging apparatus according to the
`present invention includes: a plurality of photoelectric con
`version cells each including a plurality of photoelectric sec
`tions arranged in an array of at least tWo roWs; a plurality of
`?oating diffusion sections each being connected, via each of
`a plurality of transfer transistors, to each of ones of the pho
`toelectric conversion sections Which are included in adjacent
`roWs, respectively, and Which are included in the same col
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`umn in each said photoelectric conversion cell, and each
`being shared by said ones of the photoelectric conversion
`sections; a plurality of read-out lines each being connected to
`one of the transfer transistors and independently reading out
`charge from each of said ones of the photoelectric conversion
`sections to each said ?oating diffusion section shared by said
`ones of the photoelectric conversion sections; and a plurality
`of pixel ampli?er transistors each detecting and outputting
`the potential of the ?oating diffusion section.
`In the second solid state apparatus, each said ?oating dif
`fusion section is connected to some of the plurality of transfer
`transistors, is shared by ones of the photoelectric conversion
`sections Which are included in adjacent roWs, respectively,
`and Which are included in the same. Furthermore, some of the
`plurality of read-out lines each independently reading out
`charge from each of said ones of the photoelectric conversion
`sections are connected to each said transfer transistor. Thus, a
`roW-select transistor Which is usually provided is not needed.
`As a result, the number of interconnects per photoelectric
`conversion section is reduced from 5 to 3.5. Therefore, the
`area of the photoelectric conversion cell itself can be reduced
`While increasing the area of the photoelectric sections.
`It is preferable that the second solid state imaging appara
`tus further includes a reset transistor for resetting charge
`stored in each said ?oating diffusion section and the drain of
`the reset transistor is connected to the drain of the pixel
`ampli?er transistor so that a drain is shared by the reset
`transistor and the pixel ampli?er transistor. Thus, an intercon
`nect connecting betWeen the drain of the reset transistor and
`the drain of the pixel ampli?er transistor can be shared.
`Accordingly, the number of interconnects per the photoelec
`tric conversion cell can be further reduced.
`In the second solid state imaging apparatus, it is preferable
`that each said ?oating diffusion section is arranged betWeen
`ones of the photoelectric conversion sections Which are adja
`cent to each other in the roW direction in each said photoelec
`tric conversion cell. Thus, the area of ?oating diffusion sec
`tions per photoelectric conversion cell can be reduced.
`In the second solid state imaging apparatus, it is preferable
`that each said transfer transistor is made of an MIS transistor,
`and a gate of the MIS transistor is arranged in the column
`direction. Thus, each said the read-out line can be also func
`tion as an interconnect of a transfer transistor, so that the area
`of the read-out lines occupying the photoelectric conversion
`cell can be reduced.
`Moreover, in the second solid state imaging apparatus, it is
`preferable that each said pixel ampli?er transistor is arranged
`betWeen roWs Which include some of the photoelectric con
`version sections and are adjacent to each other in each said
`photoelectric conversion cell. Thus, the area of the pixel
`ampli?er transistor per photoelectric conversion cell can be
`reduced Whereas the area of the photoelectric conversion
`sections can be increased. Therefore, light sensitivity is
`increased.
`Moreover, in the second solid state imaging apparatus, it is
`preferable that each said pixel ampli?er transistor and each
`said ?oating diffusion section are arranged betWeen adjacent
`ones of the read out lines. Thus, an interconnect connecting
`betWeen the pixel ampli?er transistor and the ?oating diffu
`sion section can be shortened, so that the areas of the pixel
`ampli?er transistor and the ?oating diffusion section per pho
`toelectric conversion cell can be reduced.
`Moreover, in the second solid state imaging apparatus, it is
`preferable that each said pixel ampli?er transistor is arranged
`betWeen ones of the photoelectric cells Which are adjacent to
`each other in the column direction. Thus, an opening for each
`said photoelectric conversion section can be formed so as to
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`5
`have a large area extending in the roW direction. Therefore,
`even if the siZe of the cell is reduced, light sensitivity can be
`maintained.
`Moreover, in the second solid state imaging apparatus, it is
`preferable that each said transfer transistor is made of an MIS
`transistor, and each said pixel ampli?er transistor is arranged
`betWeen respective gates of the MIS transistor and another
`MIS transistor. Thus, an empty region located in an area of the
`cell in Which a roW and a column intersect to each other can be
`utiliZed. Therefore, the area of the photoelectric conversion
`sections can be increased and the area of the photoelectric
`conversion cell itself can be reduced.
`In the case Where the second solid state imaging apparatus
`includes the reset transistors, it is preferable that each said
`reset transistor is arranged betWeen roWs Which include some
`of the photoelectric conversion sections and are adjacent to
`each other in each said photoelectric conversion cell. Thus,
`the area of the reset transistors per photoelectric conversion
`section can be reduced. Therefore, the area of the photoelec
`tric conversion sections can be increased and the area of the
`photoelectric conversion cell itself can be reduced.
`Moreover, in the case Where the second solid state imaging
`apparatus includes the reset transistors, it is preferable that
`each said pixel ampli?er transistor and the ?oating diffusion
`section are arranged betWeen adjacent ones of the read out
`lines. Thus, an interconnect betWeen the ?oating diffusion
`section can be omitted and the source of the reset transistor
`and the ?oating diffusion section can be connected to each
`other to be shared. Therefore, the areas of the reset transistors
`and the ?oating diffusion sections per photoelectric conver
`sion cell can be reduced.
`Moreover, in the case Where the second solid state imaging
`apparatus includes the reset transistors, it is preferable that
`each said reset transistor is connected to a line arranged
`betWeen ones of the photoelectric cells Which are adjacent to
`each other in the roW direction. Thus, pitches of the photo
`electric sections in roW directions can be matched in a simple
`manner, so that resolution is improved.
`Moreover, in the case Where the second solid state imaging
`apparatus includes the reset transistors, it is preferable that
`each said reset transistor is arranged betWeen ones of the
`photoelectric conversion cells Which are adjacent to each
`other in the column direction. Thus, an opening for each said
`photoelectric conversion section can be formed so as to have
`a large area extending in the roW direction. Therefore, even if
`the siZe of the cell is reduced, light sensitivity can be main
`tained.
`In this case, it is preferable that each said transfer transistor
`is made of an MIS transistor, and each said reset transistor is
`arranged betWeen respective gate of the MIS transistor and
`another MIS transistor. Thus, an empty region located in an
`area of the cell in Which a roW and a column intersect to each
`other can be utiliZed. Therefore, the area of the photoelectric
`conversion sections can be increased and the area of the
`photoelectric conversion cell itself can be reduced.
`In the second solid state imaging apparatus, it is preferable
`that each said ?oating diffusion section is arranged betWeen
`ones of the photoelectric conversion cells Which are adjacent
`to each other in the column direction. Thus, the area of the
`?oating diffusion sections per photoelectric conversion cell
`can be reduced.
`In the second solid state imaging apparatus, it is preferable
`that the photoelectric conversion sections are arranged so as
`to be spaced apart from one another by a certain distance in at
`least one of the roW direction and the column direction. Thus,
`inclination in the resolution of an image taken can be cor
`rected. Therefore, a high quality image can be obtained.
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`In the case Where the second solid state imaging apparatus
`includes the reset transistors, it is preferable that the line
`connecting respective drains of the reset transistor and the
`pixel ampli?er transistor also functions as a light-shielding
`?lm. Thus, the number of interconnects per photoelectric
`conversion cell can be reduced. Therefore, the area of the
`photoelectric sections can be increased and the area of the
`photoelectric conversion cell itself can be reduced.
`It is preferable that each of the ?rst and second solid state
`imaging apparatus further includes a signal processing circuit
`for processing an output signal output from each said pixel
`ampli?er transistor. Thus, a high resolution image can be
`obtained.
`A camera according to the present invention includes the
`?rst or second solid state imaging apparatus of the present
`invention. Thus, the camera of the present invention can
`achieve a high resolution image.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a circuit diagram illustrating an exemplary pho
`toelectric conversion cell in a solid state imaging apparatus
`according to a ?rst embodiment of the present invention.
`FIG. 2 is a timing chart shoWing timing for driving the solid
`state imaging apparatus of the ?rst embodiment.
`FIG. 3 is a circuit diagram illustrating an exemplary pho
`toelectric conversion cell in a solid state imaging apparatus
`according to a modi?ed example of the ?rst embodiment.
`FIG. 4 is a circuit diagram illustrating an exemplary pho
`toelectric conversion cell in a solid state imaging apparatus
`according to a second embodiment of the present invention.
`FIG. 5 is a timing chart shoWing timing for driving the solid
`state imaging apparatus of the second embodiment.
`FIG. 6 is a circuit diagram illustrating an exemplary pho
`toelectric conversion cell in a solid state imaging apparatus
`according to a third embodiment of the present invention.
`FIG. 7 is a timing chart shoWing timing for driving the solid
`state imaging apparatus of the third embodiment.
`FIG. 8 is a plane vieW schematically illustrating a layout of
`the photoelectric conversion cell in the solid state imaging
`apparatus of the third embodiment.
`FIG. 9 is a table shoWing the aperture ratio of PD sections
`to a photoelectric conversion cell in each of regions A through
`E of FIG. 8 Where a transistor and the like are arranged.
`FIG. 10 is a circuit diagram illustrating a photoelectric
`conversion cell in a knoWn solid imaging apparatus.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`First Embodiment
`
`A ?rst embodiment of the present invention Will be
`described With reference to the accompanying draWings.
`FIG. 1 is a circuit diagram illustrating an exemplary pho
`toelectric conversion cell in a solid state imaging apparatus
`according to the ?rst embodiment of the present invention.
`As shoWn in FIG. 1, for example, photoelectric conversion
`(PD) sections 1, 2, 3 and 4 each of Which is made of a
`photodiode and converts incident light to electric energy are
`arranged in this order in the roW direction. Furthermore, PD
`sections 5, 6, 7 and 8 are arranged in this order in the roW
`direction so that the PD sections 5, 6, 7 and 8 are adjacent to
`the PD sections 1, 2, 3 and 4, respectively, in the column
`direction.
`
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`7
`Here, in this application, the roW direction means to be the
`direction in Which a roW number increases and the column
`direction means to be the direction in Which a column number
`increases.
`BetWeen the ?rst and 0”’ rows (not shoWn), a ?rst ?oating
`diffusion (FD) section 9 for storing photoelectric-converted
`charges from the PD sections 1 and 5 included in the ?rst roW
`and PD sections included in the 0th roW is provided. BetWeen
`the second and third roWs, a second ?oating diffusion section
`10 for storing photoelectric-converted charges from the PD
`sections 2 and 6 included in the second roW and the PD
`sections 3 and 7 include