`
`Exhibit 17
`
`
`
`Case 1:14-cv-01430-LPS Document 308-17 Filed 06/22/20 Page 2 of 7 PageID #: 20948
`Case 1:14-cv-01430-LPS-CJB Document 109-2 Filed 04/20/16 Page 203 of 240 PageID #:
` 3232
`
`Click to edit Master title style
`Samsung Foundry
`
`3D TSV Technology &
`Wide IO Memory Solutions
`
`
`
`Smart & Innovative Foundry Solution Smart & Innovative Foundry Solution
`
`
`
`
`
`Click to edit Master title style Chip packaging progress
`
`Case 1:14-cv-01430-LPS Document 308-17 Filed 06/22/20 Page 3 of 7 PageID #: 20949
`Case 1:14-cv-01430-LPS-CJB Document 109-2 Filed 04/20/16 Page 204 of 240 PageID #:
` 3233
`
` 3D TSV is becoming reality, enabling more
`performance, less power, smaller form-factor
`
`LDP-PoP
`
` WB-SIP
`
`3D TSV
`
`FC-PoP
`
`WB-PoP
`
`
`Technology complexity
`
`2006
`
`2008
`
`2010
`
`2011
`
`2013
`
`Smart & Innovative Foundry Solution
`
`
`
`
`
`Click to edit Master title style TSV (Through Silicon Via) Technology
`
`Case 1:14-cv-01430-LPS Document 308-17 Filed 06/22/20 Page 4 of 7 PageID #: 20950
`Case 1:14-cv-01430-LPS-CJB Document 109-2 Filed 04/20/16 Page 205 of 240 PageID #:
` 3234
`
` Current Application Sweet Spot in Samsung
` 3D TSV : Logic and Wide IO Memory direct stacking with TSV
`
`35%
`
`50%
`
`8 x
`
`Package Size
`Package Size
`POP
`
`Power
`Power
`Consumption
`Consumption
`
`* Wide IO (512bits @
`200MHz SDR)
`
`Bandwidth
`3D TSV
`
`Conventional PoP Solution
`( Package-on-Package)
`
`Direct chip connection using TSV
`(TSV-micro bump joint)
`
`Smart & Innovative Foundry Solution
`
`
`
`
`
`Click to edit Master title style Wide IO Memory status
`
`Case 1:14-cv-01430-LPS Document 308-17 Filed 06/22/20 Page 5 of 7 PageID #: 20951
`Case 1:14-cv-01430-LPS-CJB Document 109-2 Filed 04/20/16 Page 206 of 240 PageID #:
` 3235
`
` Wide IO DRAM : Non-JEDEC type ball interface
` Customer Sample in Early-2013
`
`Wide IO DRAM2 : To be JEDEC standard
` Details to be discussed at JEDEC conference (Jun’12)
`
`Wide IO
`
`Smart & Innovative Foundry Solution
`
`
`
`
`
`Click to edit Master title style Readiness of TSV Design Infrastructure
`
`Case 1:14-cv-01430-LPS Document 308-17 Filed 06/22/20 Page 6 of 7 PageID #: 20952
`Case 1:14-cv-01430-LPS-CJB Document 109-2 Filed 04/20/16 Page 207 of 240 PageID #:
` 3236
`
` TSV PDK & Design Methodology is proven @ 32nm node
` TSV specific PDK
`• Add-on 32nm DRC, LVS run decks for TSV design rules
`• RC extraction of TSV paths with enhanced PEX tool
`
` TSV specific design methodology
`• Layout automation of TSV array block using Wide IO Memory pin configuration
`• TSV stress simulation
`• Thermal simulation
`• Power & signal integrity analysis for SOC - Wide IO Memory interface
`
`
`Smart & Innovative Foundry Solution
`
`
`
`Click to edit Master title style
`
`Case 1:14-cv-01430-LPS Document 308-17 Filed 06/22/20 Page 7 of 7 PageID #: 20953
`Case 1:14-cv-01430-LPS-CJB Document 109-2 Filed 04/20/16 Page 208 of 240 PageID #:
` 3237
`
`Thank You
`
`Smart & Innovative Foundry Solution
`
`
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