Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 1 of 11 PageID #: 16115
`
`Exhibit F
`
`

`

`Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 2 of 11 PageID #: 16116
`Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 2 of 11 PageID #: 16116
`
`Smart tardllssemhlv
`SEZ AG. Villach. Austria [Requires Advanced
`Pre-Assemhly Methods
`
`Br. Jnchen lllliiller. Peter Stamplra,
`Werner ltriininger
`Infineon Technologies. Munich. Germany
`Ernst Gaulhufer, Ileinz flyrer
`
`only 5—10pm, depending on the
`device. For some applications, a
`certain bulk is needed to assure
`functionality. So the limit to
`thinning is in the region of 20
`pm, although for some products
`it may even be possible to reach
`10 pm as the final thickness.
`
`
`
`
`
`
`
`
`
`__
`‘I . The continuing trend is torthinnsr wafers.
`
`afers or (lice with
`thicknesses down to
`
`100mm are virtually
`a standard require»
`ment for smart card
`applications. For a
`long time now, the
`most common thickness of about 180
`
`pm has increasingly been replaced by
`thinner successors. Consequently,
`there is already a market requirement
`for I‘super-thin" dice. 'In Japan, for
`example. there are strong efforts to stan—
`dardize a new generation of cohtaetlefis
`smart cards with a final thickness of"
`
`only 250 pm. It is therefore clear that
`these cards, with only a third ofthe cur»
`rent thickness, require extremely thin
`dice.
`
`Based on these developments it can
`be seen that the asgeragefithickness of a'
`thinned wafer is being halved every two
`years. So we can expect a thickness of
`about 50 pm by 2002 at the latest (Fig.
`1). ([his is not far from the ultimate
`
`limit. The active layer ofa chip takes up
`
`Thinning process
`The most common process
`sequence leading to thin wafers
`is divided into the following
`steps: taping the wafer’s active
`side, backgrinding the wafer,
`and etching the backside. Detap-
`ing and separation also must be done
`before assembly.
`Taping may be the simplest part of
`the process block, and it is done to pro
`tect the active side. A taping system
`applies grinding tape to the frontside of
`the wafer, Here, the wafer still has its
`original thickness of about 725 pm {for
`200111111 wafers), so the risk of breaking
`the wafer is quite low. It is essential to
`get firm contact or adhesion between
`the device side and the tape, especially
`at the wafer rini. Water and silicon dust
`
`exhibits the same adhesive strength
`during the thinning process and detap-
`ing. The adhesive strength of UV tapes
`is reduced to about 1-5 96 by UV irradi-
`ation, which is applied after thinning to
`make detaping n'iuch easier.
`Tape often is processed in rolls. In
`this case it has to be cut on the edge of
`the wafer, often done with a special
`heated knife. This method has some
`
`problems, such as ragged cutting and
`scratching of the wafer edge by a mis-
`aligned blade. Another idea is to use a
`precut tape. rThese tapes already have
`the shape of the wafer, and you can
`avoid the above-mentioned problems.
`It is only pressed on the active side,
`though, so more care must be taken in
`positioning wafer and tape to get an
`optimized result.
`
`applications
`assembly
`Advanced
`require advanced pre-assemblv tech-
`niques. For smart cards.
`thinning
`wafers and handling thin dice are
`essential. Packaging the die in the
`card in a cost-effective manner is
`
`also a challenge.
`
`penetration between wafer and tape
`during grinding would crack the wafer,
`and penetration of acid during spin
`etching also would damage the chips.
`Currently, two main groups of tapes
`in use are pressure—sensitive tape and
`UV tape. Pressure-sensitive tape
`
`SEMICONDUETDFIINTEHHATIIIHALEEI- www. semiconductor. net
`.JlJLY ECIZIU
`
`HIGHLY CONFIDENTIAL
`
`ELM30800030869
`
`

`

`Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 3 of 11 PageID #: 16117
`Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 3 of 11 PageID #: 16117
`
`ISMART CAR-D ASSEMBLY FIEGUIFIEE ADVANCED FEE-ASSEMBLY METHODS
`
`As smart cards get thinner, thinning and packaging the
`
`die require advanced technology.
`
`grinding station without handling the
`wafer itself. This is a decisive advan—
`
`tage in manufacturing thin wafers.
`If wafers are very thin they can even
`"roll up.” As they get thinner, the
`
`
`
`
`
`
`
`11.0
`
`ms
`__'1513
`were: IllinIman. [In
`
`the support unit. Using a support unit
`for processing very thin wafers is still in
`its infancy, and a lot ofwork remains to
`be done to make this process usable.
`Etching is the next step. As men-
`tioned above, the ground wafers
`show a strong tendency to bend.
`' Bow"'_ol= GROUND-AND:
`In the normal case, the wafers
`_ErcI-IEi:i 'WAFEHB
`'
`'
`produce a bow that is open at the
`I Grinding
`device side. This stress, which
`I Grinding 81 etching
`originally is responsible for the
`bow, easily could be avoided if
`the grinding damage were
`removed by etching the dam-
`aged silicon on the backside.
`Figure 2 demonstrates how
`much how can be removed by
`etching. Spin-etching is one way
`to perform this step. Without
`additional protection of the
`device side, it is vet}r easy with a
`spin-etching system to remove
`the damaged silicon zone using acidic
`compounds containing HF and
`I-INOE.
`There are other reasons for the etch-
`
`v'vafer's become more “elastic.” It is pos—
`sible for them to behave like foil or
`
`metal sheets. One idea for process
`support would be to use supporting
`media, such as plates or other wafers,
`to hold the process wafer. This is an
`advantage for handling during the
`thinning process, but it requires addi-
`tional processes to apply and remove
`
`ing step in manufacturing thin wafers.
`One is the enhancement of the die
`
`strength. The grinding damage corre-
`lates directly with the grinding marks.
`If these marks are removed you will get
`much better values in die
`
`-
`2.— Bow ills—gram at different treated waters.
`
`Grinding typically is done in two
`steps: coarse grinding and fine grind—
`ing. The wafer is ground from the
`backside using a wheel containing dia-
`nionds ofweIl—defined dimensions in a
`
`special bonding (ceramics, epoxy
`or wax). The coarse step removes
`most ofthe thickness ofthe wafer
`
`(>90%). This coarse grind causes
`some crystal damage in the back-
`side silicon. The damage could __
`reach a depth of~20-3U pm:
`The second step takes off only
`small amount of silicon
`
`a
`
`—
`
`(~IU%), amounting to only It}
`50 pm. The fine grinding step
`also removes part of the damage
`that was caused by coarse grind—
`ing.
`I'Iovvever, both grinding
`steps cause damage to the sur—
`face, though the damage from
`fine grinding is less severe, going
`only about 15-20 pm deep.
`As the wafer gets thinner, it can bow,
`especially With the influence of all the
`different layers on the 'frontside. This
`effect is amplified by the grinding
`damage, because the stability of the
`wafer is reduced. In other words, the
`grinding process itself leads to a bow-
`ing of the wafer.
`This bowing is one ofthe main
`problems in producing thin
`wafers. As coarse grinding causes
`the deeper damage, the maxi-
`mum bovv occurs after this pro—
`cess step. In general it is very dif-
`ficult to handle bent wafers. This
`
`
`STRENGTH an wrangler: WAFEHE
`
`I Back
`'Front -
`
`-
`
`
`
`
`
`job for the
`is always a critical
`equipment handling systems and
`can result in wafer breakage.
`Some of the newer equipment
`types use a modified handling
`system based on an index table to
`handle these bent wafers. This
`table moves the wafer from the
`
`
`
`
`
` ' 3 pm ntpllad
`
`'10 um etched
`
`2—5 pm etched
`
`coarse grinding station to the fine :3. Etching awaygrinding damage strengthensthe die orwafar.
`
`strength. As shown in Figure 3,
`the more the damage layer is
`etched, the greater the improve-
`ment in die strength. The best
`breakage values are achieved by
`etching to a depth of~25 pm. In
`both front and back breakage
`tests, the 25 pm etched die needs
`considerably higher forces for
`breakage than for 3 or 10 pm
`etched dice. Further investiga—
`tions show a minimum removal
`
`of ID to 15 pm is required to
`approach
`the maximum
`strength. This also depends on
`
`wwwsamicnnducmnnen
`‘EESEMICCINDUGTDFII III'ERIIIHIIJII Al
`.J Li LY EUCIO
`
`HIGHLY CONFIDENTIAL
`
`ELM30800030870
`
`

`

`Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 4 of 11 PageID #: 16118
`Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 4 of 11 PageID #: 16118
`
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`Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 5 of 11 PageID #: 16119
`
`

`

`Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 6 of 11 PageID #: 16120
`Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 6 of 11 PageID #: 16120
`
`Used industrial
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`Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 7 of 11 PageID #: 16121
`Case 1:14-cv-01432—LPS Document 238-6 Filed 12/12/19 Page 7 of 11 PagelD #: 16121—
`
`[SMART DARD ABBEMBLY REQUIRES ADVANCED DRE-ASSEMBLY METHDDB
`
`
`thin wafers.
`
`After cutting,
`the dice are sepa-
`rated on the die-
`
`ing tape. This is
`an ideal form for
`
`transport. The
`risk of damaging
`the chips is now
`practically zero.
`The
`products
`can be sent to
`
`assembly
`the
`line, where the
`first step will be
`picking up the
`die
`from the
`frame.
`
`DIE BINDING SEQUENCE
`
`Sewn“ 2
`
`Vacuum
`
`_
`
`-
`.
`I'
`
`Placing
`of chip on
`substrate
`
`l
`I
`
`'.
`i
`‘
`
`r____‘ Adhesive
`
`|
`
`Copper
`
`Adhesive
`
`/
`
`pm
`
`_—I-
`ring
`
`CU
`
`Dicecchips
`
`“mum:
`\
`
`-—- ojactcr pin
`
`7. Dia bond sequences include ejection from tape and placement
`
`Assembly
`0n the assembly line, the dice are
`installed in the packages, e.g. smart
`cards. With the following process
`sequence,
`it
`is possible to support a
`high—volume process with a yield of
`several millions of smart card modules
`
`per week.
`Die bonding is the first step. In this
`step, each chip is picked up and placed
`onto the package module, which has
`been prepared with glue or some other
`adhesive. From the backside of the
`
`wafer, the cieetor pin moves upward
`and releases the die from the glued
`wafer foil as shown in Figure 7,
`
`sequence 1. For this step, it is impor-
`tant that the die’s backside, where the
`die is glued, consistently exhibits very
`good properties. Now, the bond tool
`holds the die with a vacuum and places
`the chip onto the package substrate,
`which has been prepared with die
`adhesive. The positioning tolerance is
`typically <50 pm in the x and y direc-
`tions. To maintain the electrical per-
`formance of the product for NMOS
`le, a dielectric is necessary between
`backside of chip and metal tape. This
`could be realized, for example, using a
`non—conductive adhesive. With chips
`fabricated in CMOS technology, a
`conductive adhesive with good pro-
`cessing proper
`ties is sufficient
`to assure the
`
`
`
`3. SEM, chip wire-bonded.
`
`electrical per-
`formance
`of
`
`the chip.
`die
`The
`adhesive is now
`cured within
`60 seconds at a
`maximum tern-
`
`perature
`150°C.
`
`of
`The
`
`curing profile
`has to match
`with the die
`
`adhesive to pre—
`vent
`voids
`
`occurring under the chip, which could
`lead to lower thermal resistance of the
`
`product or microcracks during wire
`building.
`Wire bonding is the next step. item,
`the die is now interconnected with the
`
`ISO contact pads (Fig. 8) of the pack-
`age. 'l"his is effected using a very thin
`gold wire (~20-25 um) between 1.5 and
`3.5 mm long. The cycle time for com-
`plete wirebonding of one die could be
`faster than 1 second. This naturally de-
`pends on the number of wire bonds
`needed, the wire length and the wire
`bond technology. The temperature at
`the substrate has to be over 200°C for
`
`this thermosonic bonding process.
`Since the maximum thickness for
`
`the chipcard module is 600 pm, the
`loop height (height between chipcard
`surface and peak nfwire) has to be less
`than 200 inn. Using a special wire
`bond technology, the loop height can
`be reduced to about 110 um.
`Encapsulation is done next to pro—
`tect the die from mechanical and ther-
`
`mal stresses and achieve high reliabili—
`ty for the package. While chemically
`compatible with the iC surface and
`substrate (tape), the encapsulant has to
`be processed without voids within 2-3
`seconds in mass production. In smart
`card packaging, UV—curcd encapsu-
`lants are being used. 'I‘hermally cured
`adhesives have difficulties with mois-
`
`www. samlconductm r‘-. net.
`DESEMICDNDUCTDPIHIEIIEIIU HM
`JULY EEI‘JCI
`
`HIGHLY CONFIDENTIAL
`
`ELM30800030874
`
`

`

`Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 8 of 11 PageID #: 16122
`Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 8 of 11 PagelD #: 16122
`
`
`
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`TEL’s Low K 500 solution, for exampleYou choose
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`To shoot past the competition,
`visit www.telusa.comfsod
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`Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 9 of 11 PageID #: 16123
`Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 9 of 11 PageID #: 16123
`
`I SMART CARD ASSEMBLY REQUIRES ADVANGED PRE-ASSEMSLY METHODS
`
`finisnlrnpluiilll,‘
`
`Polymer
`r'iipclliu
`
`Soldcrtlluap
`
`
`
`Etching cf the wafer backside is
`
`necessary as a minimum for some
`
`products to remove all forms of
`
`contamination before the wafers are
`
`subjected to subsequent process
`
`steps on the backside.
`
`I
`
`' carcls,the countless
`
`combinations of
`
`flip-chip technolo-
`gy can be reduced
`to the four princi-
`ples shown in Fig-
`ure 9.
`For connection
`
`
`Formm are: ACF has
`been the most promising flip-chip
`technology because it is much faster
`than others. Parallel evaluation of
`
`the bumped
`of
`chip into the card,
`to
`connect
`an
`antenna for exam-
`
`wafer—level redistribution is being
`done. For chipcards with ISO con-
`
`E. Hip-chip technologies include anisotropic—ally conductive foils and veri-
`one bumping materials.
`
`ture resistance and reliability through
`temperature cycling. Also, dispensing
`the correct amount is difficult, leading
`to unacceptable geometry variations in
`the final assembly.
`A robust encapsulation process has
`to fulfill the following requirements:
`good adhesion to substrate, void—free,
`full coverage of wire and die, low ther-
`mal expansion (e.g. silicon~filled),
`high throughput, single component
`material and high moisture resistance.
`Electrical testing is done on com-
`pletion of these three steps. After this
`last quality check, the modules are
`ready for shipment.
`
`Emerging interconnect
`technologies
`Flip-chip technology provides the
`substrate direct electrical access to the
`
`die. In comparison mainly with the
`predominant standard of wire-bonded
`packages, flip-chip as an interface
`technology offers a platform for new
`approaches in packaging. For smart
`
`ple, an anisotrOpi-
`cally conductive
`film (ACF)
`foil
`could be used. ACF is an adhesive foil
`
`in which small conductive particles
`are scattered. Each pad of the chip or
`the package could be connected elec-
`trically to the corresponding pad of the
`antenna by the sandwiched conduc-
`tive particles. Due to the scattered and
`well—defined diameter of the particles,
`
`"""i.~}!§ia‘-‘n
`-:
`_
`,
`.
`
`system on oard application d cribed
`
`below‘ flip;c_l;j'p,tech_r___iology is.
`l”!
`3” ~i j‘hflilqd'ffor making the
`”5391:1293
`iriultipolar connection for the LCD.
`
`Future oopioe
`
`. A new future topic that is attracting
`a lot of interest from the research and
`
`marketing departments of card compa—
`
`
`
`1 El. System on Card provides limited computing along with communications in e eerd.
`
`wwsemiconducuonnafi
`IEEBEMICDNDUDTDRIITEIHhTIflIAL
`.JIJLY emu
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`HIGHLY CONFIDENTIAL
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`ELM3D800030876
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`

`

`Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 10 of 11 PageID #: 16124
`Filed _1_g_[124_19__ Page 10 of 11_P
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`v w
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`Have a Mask —
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`[AIMEETM it
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`The new Carl Zeiss System AIMSW‘ fab together with the Aerial Image
`Measurement Software is designed to suit into the manufacturing lines for masks
`and wafers for quality control, repair verification, and defect review classification
`of all kinds of masks through the use of aerial image measurement.
`
`Carl Zeiss
`Microelectronic Systems
`D-O??40 Jena - Phone: +49-{Ul3641f6d-2563 ‘ Fax: +49-ifll3i341l'64-2938
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`Case 1:14-cv-01432-LPS Document 238-6 Filed 12/12/19 Page 11 of 11 PageID #: 16125
`Case 1:14-cv-0143
`
`Document 238-6 Filed 12/12/19 Page 11 of 11 PagelD #: 16125.
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`FIRE-ASSEMBLY METHDDS
`
`
`
`nies is the “System on Card" (SOC).
`SOC is essentially a small version ofa
`personal computer implanted on a
`chipcartl. Figure 10 shows a first sam-
`plc ofa System on Card with LCD, bio-
`metric sensor and ISO module From
`
`Iniincon Technologies (Munich. Ger—
`many}.
`These features would offer a lot of
`
`advantages and convenience for the
`customer, so the market volume could
`rise enormously.2 For this application,
`especially for the packages and their
`integration into the card, it is necessary
`that very thin le — less than 100 pm
`thick — are available.
`
`The ultimate requirements for [C
`thickness are postulated from the
`future topic "1C in paper”.2 For this
`application, which prorides an IC
`thickness down to a minimum of 30 pin
`(half the thickness of a human hair},
`the next stage in achieving an even
`thinner, I'icxt—gcneration IC is opened.
`A final thickness in the range of 10 pin
`approaches the physical limits because
`the active layers of the IC are between
`a depth of I 0 and 30 pm. It follows that
`the requirement for wafers with a thick—
`ness of, for example, 20 pm is OI)\'i0llS-
`I_v the last stage that technology could
`reach. 'I
`
`References
`
`l\'Illt;‘llt.'l'—l"ll1}PCT, Lini‘
`1. Masters 'l'hesis. A.
`versitv of Regensliurg. 1999.
`2. IEEE, Smart Card Technologies and App] i-
`cations. \h’orkslmp. Berlin. 1998.
`7:. LC. h-Icl..augh|in, .-\. 1:: “-’illoughliv, "l“rac—
`ture of Silicon Wafers." I. of Crystal Growth,
`85, 1987-. p. 5:.
`‘I. K. \‘EIsntake, M Iuata, "Cracklleclingand
`Fracture Strength of Silicon C rystals ,l. of
`\-lnleria|s Science, 21, 1986, p. 2l83.
`5. W. Raiiltl, W. IElTIug. Handbuch der Chip—
`karten, I-ianscr, Munich, 3. edition, I999.
`6. H. l-Ioudeau, P. Stanipka. I". Piischner. Die
`IIIrirIerue Cliipkarlc -
`.'\nl0r(leruilgen 11nd
`liosungcn, Calvanoteclniik, Iahrlnich (let (it.
`Cesellschaft iiir Obel'fliit-liciileciiiiik, 1998.
`7'. Diinne Chips
`fiir
`h-liitigeliiiuse.
`h-‘larltt&'I"chIuii<, 3U. 1999,1341
`8. Chervl Mel-lotion, Cynthia M. Guinhert,
`“Defects Caused h} k-Ieehanieal Baclgriiitl-
`ing of \Kdiets and their I‘llimination bx Wet
`
`Chemical Etching,” Solid State 'l‘ecimoiogr,
`November 1998.
`(J. {1.8. Patent 3,9613%
`10. “'I‘he Importance of Measuring Cumula—
`tive I-‘ihn Stresses and its Relationship to
`\ll’afer Backgrindingz Characterizing Process
`Interactions," ADE Corp Appliealion Note,
`No. D3010, 1993.
`
`Dr. Jochen Mitller received his MS. in pure
`it applied chemistry from the University of
`Regensburg in 1994, In 1995 he received his
`PhD. in inorganic chemistry lrom the Universi-
`ty oi Flegensburg. Beginning in 1995 he worked
`for lnlineon Technologies as a process engineer
`in the was 9 preacsembly departments and in
`process integration. Since 1999. he has been
`a senior development engineer for chip mod-
`ules at Infineon‘s chipcard and security IB's
`Unit.
`email: jochenmuellerfiinfinemoom
`
`Peter Stemptta has a master’s degree in
`mechanical enginEering focusing on production
`technology. From 1994 until 1999. he was
`responsible for the development of controller
`modules and chip card modules at Siemens AG
`[now lnlineon Technologies}. From October
`199? to October 1999 he worked as senior
`manager in packaging definition. From October
`1999 to December 1999 he was a senior man-
`ager with responsibilities in the field of techni-
`cal marketing. He has been the marketing
`director oi the chipcard packaging center at
`lntineon Technologies since December 1999.
`email: peteostarnpkafiinlineoncom
`
`Werner Kroeninger received his master's
`degree in physics with main areas of interest in
`solid physics. optics and applied physics from
`the University or Fiegensburg in 1999. in 1999
`he worked as a scientific collaborator as the
`Freuenholer lnstitut liSCi in Wtirzburg. From
`1991] to 1995 he worked for Flodenetock Pre-
`cision Optics. After 1995 he worked as pro-
`cess engineer in several lielde such as CVD.
`tungsten and epitaxy for lnlineon Technologies.
`He currently is manager of ore-assembly.
`e-mail: WernenKmeningerflinfineoncom
`
`Ernst: Gaulhofer received his master's
`degree in electronics 9 communications in
`1993. Before joining SE in 1995. he worked
`tor American Microsystems Inc. and Austria
`Mikiosysteme AG in Austria. Gaulholer cur-
`rently is vice president at world-wide process
`application at SE2.
`e-meil: egaulhofmflsecat
`
`Heinz Dyrer received his masher's degree in
`mochanical engineering and economics in
`1993. He ioined SE2 in 1995 to work in techni-
`cal marketing and was responsible for value-
`based marketing communication. in 1998 he
`became marketing manager with responsibili-
`ties in die field or product marketing and mor-
`lteting coordination worldwide. He currently is
`director at marketing for Europe and Southeast
`Asia.
`e-maii: boyrerflsezct
`
`JULY 2000
`EEEIBEMIDDNDUGTDHINTERllilllflliilL
`
`www.53miconduct‘.mr.net
`
`HIGHLY CONFIDENTIAL
`
`ELM3D800030878
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