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`Exhibit A
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`United States Court of Appeals
`for the Federal Circuit
`______________________
`
`CALIFORNIA INSTITUTE OF TECHNOLOGY,
`Plaintiff-Appellee
`
`v.
`
`BROADCOM LIMITED, NKA BROADCOM INC.,
`BROADCOM CORPORATION, AVAGO
`TECHNOLOGIES LIMITED, NKA AVAGO
`TECHNOLOGIES INTERNATIONAL SALES PTE.
`LIMITED, APPLE INC.,
`Defendants-Appellants
`______________________
`
`2020-2222, 2021-1527
`______________________
`
`Appeals from the United States District Court for the
`Central District of California in No. 2:16-cv-03714-GW-
`AGR, Judge George H. Wu.
`______________________
`
`Decided: February 4, 2022
`______________________
`
`KATHLEEN M. SULLIVAN, Quinn Emanuel Urquhart &
`Sullivan, LLP, Los Angeles, CA, argued for plaintiff-appel-
`lee. Also represented by JAMES R. ASPERGER; BRIAN P.
`BIDDINGER, EDWARD J. DEFRANCO, New York, NY; TODD
`MICHAEL BRIGGS, KEVIN P.B. JOHNSON, Redwood Shores,
`CA; DEREK L. SHAFFER, Washington, DC; KEVIN
`ALEXANDER SMITH, San Francisco, CA.
`
`
`

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`2
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`THE CALIFORNIA INSTITUTE v. BROADCOM LIMITED
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`
` WILLIAM F. LEE, Wilmer Cutler Pickering Hale and
`Dorr LLP, Boston, MA, argued for defendants-appellants.
`Also represented by LAUREN B. FLETCHER, MADELEINE C.
`LAUPHEIMER, JOSEPH J. MUELLER; STEVEN JARED HORN,
`DAVID P. YIN, Washington, DC; MARK D. SELWYN, Palo
`Alto, CA.
` ______________________
`
`Before LOURIE, LINN, and DYK, Circuit Judges.
`Opinion for the Court filed by Circuit Judge LINN.
`Opinion concurring-in-part and dissenting-in-part filed by
`Circuit Judge DYK.
`LINN, Circuit Judge.
`Broadcom Limited, Broadcom Corporation, and Avago
`Technologies Ltd. (collectively “Broadcom”) and Apple Inc.
`(“Apple”) appeal from the adverse decision of the District
`Court for the Central District of California in an infringe-
`ment suit filed by the California Institute of Technology
`(“Caltech”) for infringement of its U.S. Patents No.
`7,116,710 (“the ’710 patent”), No. 7,421,032 (“the ’032 pa-
`tent”), and No. 7,916,781 (“the ’781 patent”).
`Because the district court did not err in its construction
`of the claim limitation “repeat” and because substantial ev-
`idence supports the jury’s verdict of infringement of the as-
`serted claims of the ’710 and ’032 patents, we affirm the
`district court’s denial of JMOL on infringement thereof.
`We also affirm the district court’s conclusion that claim 13
`of the ’781 patent is patent-eligible but vacate the jury’s
`verdict of infringement thereof because of the district
`court’s failure to instruct the jury on the construction of the
`claim term “variable number of subsets.” We thus remand
`for a new trial on infringement of claim 13 of the ’781 pa-
`tent. We further affirm the district court’s summary judg-
`ment findings of no invalidity based on IPR estoppel and
`its determination of no inequitable conduct. We affirm the
`
`

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`THE CALIFORNIA INSTITUTE v. BROADCOM LIMITED
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`3
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`district court’s decision with respect to its jury instructions
`on extraterritoriality. But because Caltech’s two-tier dam-
`ages theory cannot be supported on this record, we vacate
`the jury’s damages award and remand for a new trial on
`damages.
`
`BACKGROUND
`I. The Caltech Patents
`Caltech’s ’710 and ’032 patents disclose circuits that
`generate and receive irregular repeat and accumulate
`(“IRA”) codes, a type of error correction code designed to
`improve the speed and reliability of data transmissions.
`Wireless data transmissions are ordinarily susceptible to
`corruption arising from noise or other forms of interfer-
`ence. IRA codes help to identify and correct corruption af-
`ter it occurs.
`The encoding process begins with the processing of
`data before it is transmitted. The data consists of infor-
`mation bits in the form of 1’s and 0’s. The information bits
`are input into an encoder, a device that generates code-
`words comprised of parity bits and the original information
`bits. Parity bits are appended at the end of a codeword.
`Codewords are created in part by repeating information
`bits in order to increase the transmission’s reliability.
`When noise or other forms of interference introduce errors
`into the codewords during transmission, the decoder iden-
`tifies these errors and relies on the codeword’s redundant
`incorporation of the original string of information bits to
`correct and eliminate the errors.
`Before Caltech’s patents, error correction codes had al-
`ready incorporated repetition and irregular repetition.
`These codes, however, were less than optimally efficient be-
`cause they were either encoded or decoded in quadratic
`time, which meant that the number of computations
`
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`required to correct a given number of bits far exceeded the
`number of bits ultimately corrected.
`In the ’710 and ’032 patents, the IRA codes are linear-
`time encodable and decodable, rather than quadratic. ’710
`patent, col. 2, ll. 6–7 (“The encoded data output from the
`inner coder may be transmitted on a channel and decoded
`in linear time.”); id. col. 2, l. 59 (“The inner coder 206 may
`be a linear rate-1 coder.”); id. col. 3, ll. 25–26 (“An IRA code
`is a linear code.”). Using a linear code means that the re-
`lationship between the bits corrected and the computations
`required is directly proportional. Minimizing the number
`of calculations that an encoder or decoder must perform
`permits smaller, more efficient chips with lower power re-
`quirements.
`The claimed improvement involves encoding the infor-
`mation bits through a process of irregular repetition,
`scrambling, summing, and accumulation. Repeating in-
`putted information bits is necessary to increase the relia-
`bility of data transmissions, and irregular repetition
`minimizes the number of times that information bits are
`repeated. Minimizing the number of times that an infor-
`mation bit is repeated is crucial to the efficiency of the
`claimed inventions because the repetitions impact the de-
`vice’s coding rate or speed, as well as the code’s complexity.
`The fewer repeated bits there are, the fewer number of
`computations that an encoder must perform, which in turn
`permits smaller circuits, decreased power requirements,
`and decreased operating temperatures in devices incorpo-
`rating the circuits.
`The claims and accompanying specifications of the Cal-
`tech patents make clear that each inputted information bit
`must be repeated. The parties agree that every claim at
`issue requires irregular repetition of information bits ei-
`ther explicitly or via the court’s construction. This is so
`even where the irregular repetition is not expressly
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`required by the claims. For example, the agreed-upon con-
`struction of a Tanner graph in the ’032 patent requires that
`“every message bit is repeated . . . .” J. App’x 33. Further-
`more, the claims and accompanying specifications make
`clear that each bit must be repeated irregularly, stating,
`for example in the ’710 patent, “a fraction of the bits in the
`block may be repeated two times, a fraction of bits may be
`repeated three times, and the remainder of bits may be re-
`peated four times.” ’710 patent, col. 2, ll. 53–58.
`The ‘781 patent discloses and claims a method for cre-
`ating codewords in which “information bits appear in a var-
`iable number of subsets.” Before trial, Apple and
`Broadcom sought summary judgment that claim 13 was
`unpatentable under 35 U.S.C. § 101. After finding that the
`claims were directed to a patent-eligible subject matter
`(step 1 of Alice1)—a method of performing error correction
`and detection encoding with the requirement of irregular
`repetition—the court declined to reach whether they con-
`tained an inventive concept (step 2 of Alice). To support
`patentability, Caltech argued that the “variable number of
`subsets” language required irregular information bit repe-
`tition. The district court agreed and adopted and relied on
`Caltech’s interpretation to deny summary judgment of un-
`patentability. No party on appeal challenges this claim in-
`terpretation.
`
`II. The Accused Products
`Caltech alleged infringement by certain Broadcom Wi-
`Fi chips and Apple products incorporating those chips, in-
`cluding smartphones, tablets, and computers. The accused
`Broadcom chips were developed and supplied to Apple pur-
`suant to Master Development and Supply Agreements
`
`
`1 Alice Corp. Pty. Ltd. v. CLS Bank Int’l, 573 U.S.
`208 (2014).
`
`

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`THE CALIFORNIA INSTITUTE v. BROADCOM LIMITED
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`negotiated and entered into in the United States. Caltech
`specifically identified as infringing products two encode1·s
`contained in the Broadcom chips-a Richardson-Urbanke
`("RU") encoder and a low-area ("LA") encoder. In the ac(cid:173)
`cused encoders, incoming information bits are provided to
`AND gates in the RU encoder or multiplexers in the LA
`encodei·.
`
`Throughout the ti·ial and on appeal, the parties treated
`AND gates and multiplexers as functionally identical for
`all relevant issues. It thus suffices to describe in detail the
`RU encoder only. In the RU encoder, each information bit
`is simultaneously fed as one input to 972 separate AND
`gates. Each AND gate receives a second input-a "parity(cid:173)
`check" or "enable" bit of 0 or I-derived from a low-density
`parity check matrix. This matrix is an anay of l 's and O's.
`A low-density parity check matrix is one in which the num(cid:173)
`ber of l's in the matrix is significantly fewer than the num(cid:173)
`ber of O's.
`
`In its brief, Broadcom presents the following table, us(cid:173)
`ing the example of the functioning of a single AND gate, to
`show how outputs ai·e determined by the two inputs:
`
`Input 1
`(Information Bit)
`
`0
`
`0
`
`1
`
`1
`
`Input 2
`(Parity-Check Bit)
`0
`
`AND Gate
`Output
`0
`
`1
`
`0
`
`1
`
`0
`
`0
`
`1
`
`For each AND gate, the output of the gate is 1 if both
`inputs (the information bit and the parity-check bit) are l ;
`otherwise, the output is 0. One consequence of this logic is
`that if the parity-check bit is 1 (as shown in rows two and
`four) , then the output is identical to the information-bit in(cid:173)
`put. If the parity-check bit is 0, the output is 0, regardless
`
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`of the value of the input (rows one and three). Throughout
`trial, the parties referred to parity-check bits and enable
`bits interchangeably. Parity-check bits determine the ac-
`tion of the AND gates, which are open/on when the parity-
`check bit is 1 and closed/off when the parity-check bit is 0.
`Caltech sued Broadcom and Apple on May 26, 2016, al-
`leging infringement under 35 U.S.C. § 271 by Broadcom
`wireless chips and Apple products incorporating those
`chips. Both defendants denied that any of the accused de-
`vices infringed Caltech’s patents, and in turn asserted
`counterclaims for declaratory judgment of non-infringe-
`ment, invalidity under 35 U.S.C. §§ 101, 102, 103, and/or
`112, and unenforceability due to inequitable conduct.
`III. Pre-Trial Proceedings
`Before trial, Apple filed multiple IPR petitions chal-
`lenging the validity of the claims at issue, relying on vari-
`ous prior art references. The Patent Trial and Appeal
`Board (“PTAB” or “Board”) issued a number of written de-
`cisions, which concluded that Apple failed to show the chal-
`lenged claims were unpatentable as obvious. Before the
`district court, Apple and Broadcom argued that the as-
`serted claims would have been obvious over new combina-
`tions of prior art not asserted in the IPR proceedings.
`The district court granted summary judgment of no in-
`validity, interpreting 35 U.S.C. § 315(e)(2) as precluding
`parties from raising invalidity arguments at trial that they
`reasonably could have raised in their IPR petitions. It also
`denied the motion filed by Apple and Broadcom for sum-
`mary judgment of invalidity under 35 U.S.C. § 101 for the
`’781 patent. The district court granted Caltech’s summary
`judgment motion as to inequitable conduct, finding no in-
`equitable conduct with respect to Caltech’s failure to dis-
`close Richardson99 during prosecution. The district court
`reasoned that this prior art reference was not but-for ma-
`terial to the PTO’s grant of Caltech’s patents.
`
`

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`The district court also conducted a Markman hearing
`and initially construed the claim limitation “repeat.” That
`construction is germane to all of the asserted claims. At
`the conclusion of the Markman hearing, the district court
`construed “repeat” to have its plain and ordinary meaning.
`The district court noted that the repeated bits “are a con-
`struct distinct from the original bits from which they are
`created,” but that they need not be generated by storing
`new copied bits in memory.
`IV Trial Proceedings
`A. Infringement of the ’710 and ’032 Patents
`At trial, Caltech argued that the accused chips in-
`fringed claims 20 and 22 of the ’710 patent and claims 11
`and 18 of the ’032 patent. Both groups of claims explicitly
`require irregular repetition; i.e., repetition of groups of in-
`formation bits an irregular number of times. Claims 20
`and 22 of the ’710 patent depend from claim 15, which
`claims:
`15. A coder comprising: a first coder having an in-
`put configured to receive a stream of bits, said first
`coder operative to repeat said stream of bits irreg-
`ularly and scramble the repeated bits; and a second
`coder operative to further encode bits output from
`the first coder at a rate within 10% of one.
`’710 patent, col. 8, ll. 1–6. Claims 11 and 18 of the ’032
`patent cover devices for encoding and decoding pursuant to
`a Tanner graph:2
`
`
`2 During claim construction, the parties agreed that
`a Tanner graph is a visual representation of the “con-
`straints that determine the parity bits” created by an IRA
`code. J. App’x 33.
`
`

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`11. A device comprising: an encoder configured to
`receive a collection of message bits and encode the
`message bits to generate a collection of parity bits
`in accordance with the following Tanner graph:
`
`·········/P\
`•········\p):
`·~ ... ~··
`·········•18r I
`\c} I
`·~ .... •
`c✓.<n ..... .
`•······---r3\:
`......... \:8L
`~ ...... .
`
`
`18. A device comprising: a message passing de-
`
`coder configured to decode a received data stream
`that includes a collection of parity bits, the message
`passing decoder comprising two or more check/var-
`iable nodes operating in parallel to receive mes-
`sages from neighboring check/variable nodes and
`send updated messages to the neighboring varia-
`ble/check nodes, wherein the message passing de-
`coder is configured to decode the received data
`stream that has been encoded in accordance with
`the following Tanner graph:
`
`

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`THE CALIFORNIA INSTITUTE v. BROADCOM LIMITED
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`10
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`
`
`~
`•········/8f I
`......... \o.L I
`... ':' .. ,
`•······•18\~
`•·······.\bi~
`
`.. ,._ .. :
`
`
`’032 patent, col. 8, l. 63–col. 9, l. 34; col. 9, l. 57–col. 10, l.
`42. The district court’s claim construction ruling required
`that the Tanner graphs in claims 11 and 18 also perform
`repetition. J. App’x 33 (defining Tanner graph as a depic-
`tion of “an IRA code as a set of parity checks where every
`message bit is repeated, at least two different subsets of
`message bits are repeated a different number of times”).
`No party challenges this construction on appeal.
`During trial, the district court revisited and clarified
`its earlier claim construction ruling of the term “repeat”
`and instructed the jury that repeat means “generation of
`additional bits, where generation can include, for example,
`duplication or reuse of bits.” Apple and Broadcom then ar-
`gued that the chips did not infringe the ’710 and ’032 pa-
`tents because they did not repeat information bits at all,
`much less irregularly. The jury ultimately found infringe-
`ment of all the asserted claims. Broadcom and Apple filed
`post-trial motions for JMOL and a new trial, challenging
`the jury’s infringement verdict. The district court denied
`JMOL, finding no error in its claim construction ruling and
`
`

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`concluding that the verdict was supported by substantial
`evidence.
`
`B. Infringement of the ’781 Patent
`At trial, Caltech also argued that the accused chips in-
`fringed claim 13 of the ’781 patent. That patent discloses
`and claims a method for creating codewords in which “in-
`formation bits appear in a variable number of subsets.”
`Claim 13 recites:
`A method of encoding a signal, comprising:
`receiving a block of data in the signal to be encoded,
`the block of data including information bits; and
`performing an encoding operation using the infor-
`mation bits as an input, the encoding operation in-
`cluding an accumulation of mod-2 or exclusive-OR
`sums of bits in subsets of the information bits, the
`encoding operation generating at least a portion of
`a codeword,
`wherein the information bits appear in a variable
`number of subsets.
`’781 patent, col. 8, ll. 7–16.
`Despite its construction at the summary judgment
`stage that the claim term “variable number of subsets” re-
`quires irregular information bit repetition, the district
`court declined to provide the jury with an instruction of
`that claim construction determination and the jury deter-
`mined that Apple and Broadcom infringed claim 13 of the
`’781 patent. Broadcom and Apple filed JMOL and new trial
`motions arguing that the district court erred in refusing
`their requested instruction and that JMOL of noninfringe-
`ment was appropriate because the irregular repetition re-
`quirement was not satisfied. In denying these post-trial
`motions, the district court concluded that it was “within its
`
`

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`discretion” not to issue this instruction so as not to “confuse
`the record on this issue.”
`C. Damages
`To compensate for Broadcom and Apple’s infringement,
`Caltech proposed a two-tier damages theory, which sought
`different royalty rates from each of the infringers despite
`the fact that liability arose from the same accused technol-
`ogy in the same chips. Even though the district court
`voiced its discomfort with the two-tier theory, it allowed
`Caltech to present the theory to the jury, which relied on it
`to award Caltech $270,241,171 for Broadcom’s infringe-
`ment and $837,801,178 for Apple’s infringement. The
`jury’s damages award was based on Caltech’s experts’ tes-
`timony, admitted over Broadcom and Apple’s objection.
`Appellants challenged the damages award in their post-
`trial motions, which the district court denied. The district
`court entered
`judgment against Broadcom totaling
`$288,246,156, and against Apple totaling $885,441,828.
`These awards included pre-judgment interest, as well as
`post-judgment interest and an ongoing royalty at the rate
`set by the jury’s verdict.
`Broadcom and Apple appeal. We have jurisdiction pur-
`suant to 28 U.S.C. §1295(a)(1).
`DISCUSSION
`I. Standard of Review
`Claim construction is reviewed de novo when relying
`on intrinsic evidence. Teva Pharms. USA, Inc. v. Sandoz,
`Inc., 574 U.S. 318, 333 (2015). Infringement and damages
`are reviewed for substantial evidence. Lucent Techs., Inc.
`v. Gateway, Inc., 580 F.3d 1301, 1309, 1324 (Fed. Cir.
`2009). Statutory interpretation is reviewed de novo. Power
`Integrations v. Semiconductor Components Indus., LLC,
`926 F.3d 1306, 1313 (Fed. Cir. 2019). Patent-eligibility un-
`der 35 U.S.C. § 101 is reviewed de novo. Recognicorp, LLC
`
`

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`v. Nintendo Co., 855 F.3d 1322, 1326 (Fed. Cir. 2017). We
`review patent jury instructions on patent law issues de
`novo, asking if the instructions were legally erroneous and
`prejudicial. Bettcher Indus., Inc. v. Bunzl USA, Inc., 661
`F.3d 629, 638-39 (Fed. Cir. 2011).
`We review a district court’s order denying JMOL under
`the standard applied by the regional circuit. Apple, Inc. v.
`Samsung Electronics Co., Ltd., 839 F.3d 1034, 1040 (Fed.
`Cir. 2016). In the Ninth Circuit, JMOL “is proper when the
`evidence permits only one reasonable conclusion and the
`conclusion is contrary to that of the jury.” See Monroe v.
`City of Phoenix, 248 F.3d 851, 861 (9th Cir. 2001). The
`Ninth Circuit explains that “[t]he evidence must be viewed
`in the light most favorable to the nonmoving party, and all
`reasonable inferences must be drawn in favor of that
`party.” Id. The Ninth Circuit reviews a district court’s de-
`cision to deny JMOL de novo. Id.
`II. Infringement
`A. The ’710 and ’032 Patents
`Broadcom and Apple argue that the district court erro-
`neously construed “repeat,” contending that the accused
`AND gates and multiplexers do not “repeat” information
`bits in the manner claimed, but instead combine the infor-
`mation bits with bits from a parity-check matrix to output
`new bits reflecting that combination. Broadcom and Apple
`further argue that the AND gates and multiplexers also do
`not generate bits “irregularly,” asserting that they output
`the same number of bits for every information bit. Caltech
`argues in response that expert testimony throughout the
`record establishes that every information bit is repeated an
`irregular number of times. According to Caltech, the jury
`heard testimony explaining that in the RU devices every bit
`in the stream of information bits is fed by wire simultane-
`ously to the information inputs of all 972 AND gates and
`that at any time, at least 3 and up to 12 of those AND gates
`
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`will be enabled to repeat that bit at the output of the AND
`gates. We find no error in the district court’s construction
`of the term “repeat” and agree with Caltech that substan-
`tial evidence in the record supports the jury’s verdict on in-
`fringement.
`1. Claim Construction of “repeat”
`The district court construed “repeat” to mean “genera-
`tion of additional bits, where generation can include, for
`example, duplication or reuse of bits” (emphasis added). J.
`App’x 171. Broadcom and Apple argue that that construc-
`tion is inconsistent with the claim language, the specifica-
`tion and the construction given by another judge in a
`different case.3 Caltech argues in response that the plain
`claim language requiring repeating information bits does
`not require generating new, distinct bits and that the dis-
`trict court was correct in construing the term to not exclude
`the reuse of bits. We agree with Caltech.
`The district court correctly observed that the claims re-
`quire repeating but do not specify how the repeating is to
`occur: “The claims simply require bits to be repeated, with-
`out limiting how specifically the duplicate bits are created
`or stored in the memory.” J. App’x 10. The specifications
`confirm that construction and describe two embodiments,
`neither of which require duplication of bits. The district
`court carefully and fully considered both the language of
`the claims and that of the written description and faithfully
`applied our precedent to reach the construction made dur-
`ing the trial and presented to the jury. We are not
`
`
`3 Broadcom and Apple misplace reliance on the con-
`struction of the term “repeat” made on an undeveloped rec-
`ord in the context of a summary judgment motion. See
`California Institute of Technology v. Hughes Communica-
`tions Inc., 35 F. Supp. 3d 1176 (C.D. Cal. 2014).
`
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`THE CALIFORNIA INSTITUTE v. BROADCOM LIMITED
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`persuaded that the district court erred in construing the
`term “repeat” and, therefore, affirm the same.
`2.
` JMOL on Infringement
`Broadcom and Apple argue that the evidence before the
`jury on infringement permitted only one verdict, namely no
`infringement, and that the district court erred in denying
`JMOL. Broadcom and Apple put forth two rationales for
`noninfringement of the “irregular repeat” requirement, Ap-
`pellant’s Br. 27–31. First, looking at each gate alone and
`commenting on the “repeat” requirement, they argue that
`the AND gate does not “repeat” the inputted information
`bit “because the AND gate’s output depends on not only the
`information bit but also the parity-check-matrix bit.” Ap-
`pellant’s Br. 29. Second, focusing on the “irregular” half of
`“irregular repeat,” they argue that “even if the outputted
`bits could be deemed ‘repeats’ of the information bits,” “any
`repetition is not ‘irregular’ because each information bit
`leads to the same number of outputted bits.” Appellant’s
`Br. 30.
`Caltech argues in response that the jury was provided
`with substantial evidence to support the verdict of infringe-
`ment and that the district court correctly denied JMOL.
`Caltech asserts that the fact that an AND gate doesn’t have
`an information-bit/output match for every information bit
`hardly means that it isn’t repeating any information bit.
`Appellee’s Br. 21–22 (citing J. App’x 3036–38). All that
`matters, according to Caltech, is that sometimes there is
`such a match that qualifies as a “repeat,” so long as each
`and every bit is repeated at least once. Caltech argues that
`Broadcom ignores ample expert testimony, which the jury
`could credit, that sometimes an AND gate repeats an infor-
`mation bit and that, taking the 972 AND gates together,
`the carefully designed parity-bit table/matrix meant that
`“the products output and store information bits between
`two and twelve times.” Appellee’s Br. 22. Caltech asserts
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`that, considering the system as a whole, each information
`bit is in fact repeated, and they are not all repeated the
`same number of times. We agree with Caltech.
`Caltech’s expert, Dr. Matthew Shoemake began his tes-
`timony with reference to the exemplary table reproduced
`above. See J. App’x 3036–38. He explained that in the par-
`ity-check-bit-equals-1 situation (second and fourth rows of
`the table), the output bit is a “repeat” of the information-
`bit input. Where the parity-check bit is 1, the gate affirm-
`atively enables the information bit to be duplicated as the
`output bit. That is a “repeat.” That is so, he explained,
`because the information bit in that situation “flows
`through” to appear again in the output. He also addressed
`the one other situation where the output bit is identical to
`the information bit, namely, in the first row of the above
`table, where both the information bit and the parity-check
`bit are 0, and so is the output. Despite the identity of the
`information bit and the output bit, he explained, that situ-
`ation does not involve a “repeat.” A 0 parity-check bit turns
`every information bit (0 or 1) into a 0 output, so the output
`bit in that situation tells one nothing about the information
`bit. Since the whole point of this encoding scheme is to use
`outputs that give information about the information bits, a
`0 parity-check bit does not produce a “repeat” even when
`the information-bit input and the output are the same.
`Broadcom’s expert, Dr. Wayne Stark, expressly recognized
`that this was exactly what Dr. Shoemake said in his testi-
`mony. J. App’x 3956 (“He said it’s a repeat only if the ena-
`ble [parity-check] signal is a one and it’s not a repeat if an
`enable [parity-check] symbol is a zero.”).
`Dr. Shoemake also explained to the jury that “flow
`through” means that the information bit is repeated at the
`output gate. See, e.g., J. App’x 2810, 2812, 3017–19. When
`the information bit “flows through” to the output gate be-
`cause the parity-check bit is 1, that’s a repeat, both accord-
`ing to the expert’s usage and a plain understanding of the
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`word “repeat.” See, e.g., J. App’x 3038. When the infor-
`mation bit is not allowed to flow through (because the par-
`ity-check bit is 0), that’s not a repeat (even though both the
`information bit and the output bit are 0).4
`In explaining the operation of the RU encoder itself, Dr.
`Shoemake testified that it contains “972 mac_reg modules
`[AND gates], and the information bits are connected to
`every single one of them.” J. App’x 2831. He further testi-
`fied that: “[D]epending on which information bit it is, 3 to
`12 of these gates are enabled which then allows 3 to 12 …
`[information bits] to flow through 3 to 12 times and since
`that number varies, there’s irregular repetition,” J. App’x
`3034-35; “[W]hat really happens in the accused products,
`the tables tell you how many times should information bit
`number one be repeated. And the tables I've mentioned
`several times that they allow information bits, and I should
`force information bits to be repeated between 3 and 12
`times,” J. App’x 3080; and “[T]he information bit starts off
`in one location in the chip, and then it’s connected to 972
`distinct locations so it can be irregularly repeated in this
`architecture.” J. App’x 3018.
`Dr. Shoemake’s position was consistent throughout his
`testimony: the physical connection of the first inputs of all
`972 AND gates for simultaneous receipt of the information
`bit stream and the connection of the parity-bit system to
`the other inputs of the AND gates to selectively enable 3 to
`12 of those gates at any time together implement irregular
`
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`4 Caltech’s Red Brief incorrectly cited this example
`as representing a repeat. Red. Br. 21. This was evidently
`error, given that it directly contracted the directly cited
`pages of Dr. Shoemake’s testimony. This error does not,
`however, change the fact that Caltech correctly identified
`the substantial trial testimony on which the jury could base
`its decision.
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