Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 1 of 39
`Case 5:20-cv-05676—EJD Document 42-7 Filed 12/07/20 Page 1 of 39
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`EXHIBIT E
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`EXHIBIT E
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`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 2 of 39
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`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
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`DEMARAY LLC,
`
`Plaintiff,
`v.
`INTEL CORPORATION,
`Defendant.
`
`Case No. 6:20-cv-00634-ADA
`
`PLAINTIFF DEMARAY LLC’S PRELIMINARY INFRINGEMENT CONTENTIONS
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`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 3 of 39
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`Pursuant to the Court’s October 5, 2020, Order Governing Proceedings – Patent Case,
`Plaintiff Demaray LLC (“Demaray”) provides the following disclosure of its preliminary
`infringement contentions with regard to U.S. Patent Nos. 7,544,276 (“the ’276 Patent”) and
`7,381,657 (“the ’657 Patent”) (collectively, the “Asserted Patents”).
`I.
`Background
`
`These preliminary infringement contentions and associated disclosures (“Preliminary
`Infringement Contentions”) are based on the limited information that Demaray has been able to
`obtain from its investigation to date. Although Demaray has undertaken reasonable efforts to
`prepare these Preliminary Infringement Contentions, the configuration, structure, and operation of
`Defendant Intel Corporation’s (“Intel”) physical vapor deposition (“PVD”) reactors for thin film
`deposition (“Intel PVD Reactors”) in the production of Intel’s semiconductor products are, in
`significant part, proprietary and have not yet been disclosed by Intel. Demaray requested that Intel
`provide specifically identified technical information that would enable Demaray to provide more
`detailed Preliminary Infringement Contentions, but Intel refused Demaray’s request.1 Demaray has
`endeavored to provide a reasonable level of detail in its preliminary infringement contentions
`based upon the limited publicly available information regarding the Intel PVD Reactors and
`production processes for Intel’s semiconductor products. Until discovery is obtained from Intel,
`the proprietary aspects of the Intel PVD Reactors and methods of use of such reactors in the
`production of Intel’s semiconductor products have limited the possible breadth and depth of these
`Preliminary Infringement Contentions. For these reasons, among others, Demaray reserves all
`rights to later amend these Preliminary Infringement Contentions based on information later
`produced by Intel.
`
`
`1 Demaray sent Intel a letter on September 15, 2020, identifying limited core technical
`documents related to its PVD reactors in order to ensure that certain claims of the patents could be
`thoroughly addressed in the Preliminary Infringement Contentions. Specifically, Demaray
`requested that Intel provide documents sufficient to show the suppliers, model numbers, and
`configuration of reactors used for physical vapor deposition of thin films used by Intel for the
`production of semiconductor devices in the last six years. This included, for example, the power
`sources coupled to the target/substrate for each chamber in each reactor and the types of thin films
`deposited by each chamber in each reactor. Intel refused these requests on September 21, 2020.
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`II.
`
`Charts Setting Forth Where In The Accused Products Each Element Of The Asserted
`Claims Are Found
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`Attached as Exhibits A and B are charts setting forth Demaray’s preliminary contentions
`regarding where in the accused products each element of the asserted claims are found and an
`identification of the patent claims presently asserted (“Asserted Claims”) and the products,
`methods, or other instrumentalities presently believed to infringe. All claims identified therein—
`including those claims for which it is noted that further discovery from Intel is believed to be
`required—should be considered asserted, including for purposes of identifying claim terms whose
`constructions may be disputed. Each of the following exhibits, which may contain Demaray
`confidential material, is hereby incorporated by reference:
`Exhibit U.S. Patent No.
`A
`7,544,276
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`B
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`7,381,657
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`Exhibits A and B are intended to be understood by skilled persons in the art. Demaray
`reserves the right to rely on technical documents to further clarify the terms and technologies used
`in these Preliminary Infringement Contentions in its future expert reports and trial evidence.
`Several elements of the Asserted Claims may be satisfied by more than one component, structure,
`process, or action found within or taken by Intel in the production of Intel’s semiconductor
`products or the Intel PVD Reactors. The initial claim charts provided herewith may therefore
`include alternative contentions and theories. For example, where multiple structures are identified
`as corresponding to a particular claim element, the multiple structures may be viewed as
`alternative or supplemental to one another.
`Demaray expressly reserves the right to amend, revise or supplement these disclosures for
`at least any of the following reasons: Intel’s production of discovery about the production
`processes for Intel’s semiconductor products or the Intel PVD Reactors; the disclosure of Intel’s
`claim construction positions, invalidity contentions, or non-infringement contentions; the Court’s
`construction of any of the Asserted Claims or any other legal determination of other issues;
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`analysis undertaken or determinations made based in whole or part on the foregoing; or for any
`other permissible reason.
`These Preliminary Infringement Contentions provide examples of infringement that
`illustrate Demaray’s infringement theories. However, these examples are non-limiting and are
`included to assist in disclosing and understanding Demaray’s infringement theories. For example,
`details regarding the production processes for Intel’s semiconductor products or how the Intel
`PVD Reactors implement certain patent claims may vary from device to device in ways not
`material to the analysis of the Asserted Claims. The specific instrumentalities selected for the most
`detailed discussions in the accompanying charts are, as explained in the charts themselves and as
`further addressed in this document, to be understood as representative of other instrumentalities
`with structures, operation, or other charted characteristics that do not differ from the
`instrumentalities charted in ways that are material to Demaray’s theories of infringement for the
`charted claims.
`Demaray currently understands Intel’s microprocessor products to be grouped by
`generations and code names corresponding to varying microarchitectures. For example, in these
`Preliminary Infringement Contentions, including in Exhibits A-B hereof, a reference to a
`“Broadwell” microarchitecture is intended to include all semiconductor products of that
`microarchitecture, including variants thereof unless otherwise specified.
`III.
`Infringement Under The Doctrine Of Equivalents
`
`The enclosed charts disclose the patent claims at issue that are believed to be literally
`present in Intel’s technology, the elements of which are also believed to be infringed under the
`doctrine of equivalents. Demaray reserves the right to provide further details regarding Intel’s
`infringement under the doctrine of equivalents as discovery is provided by Intel. Demaray further
`reserves the right to assert the doctrine of equivalents in the event that Intel claims that one or
`more claim limitations are not literally present in any of the production processes for Intel’s
`semiconductor products or the Intel PVD Reactors.
`IV.
`Indirect Infringement
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`To the extent that any element of any Asserted Claim is practiced or alleged by Intel to be
`practiced by a party or entity other than Intel, Demaray may assert, and reserves the right to assert,
`that such other party or entity practices such element under the direction or control of Intel or
`otherwise in a manner that renders Intel responsible for the performance of the entirety of the
`asserted claims pursuant to, inter alia, 35 U.S.C. §§ 271(a), (f)(1), (f)(2), and/or (g) and associated
`case law. Further, to the extent that any element of any Asserted Claim is performed or alleged by
`Intel to be performed by a party or entity other than Intel, and Intel further alleges it is not liable
`for direct infringement, Demaray may assert, and reserves the right to assert, that Intel is liable for
`induced and/or contributory infringement pursuant to 35 U.S.C. §§ 271(b) and 271(c) and
`associated case law.
`For example, Demaray may assert that Intel is liable under 35 U.S.C. §§ 271(b) and 271(c)
`for infringement by third-parties involved in research and fabrication of Intel semiconductor
`products using PVD reactors configured or operated as required by the claims that Intel supplies or
`that are configured or operated in that manner at Intel’s direction. Intel, for example, may
`contribute to infringement of the patents-in-suit by providing PVD reactors to third-parties
`configured such that they have no substantial non-infringing use or by encouraging or requiring
`third-parties to use PVD reactors so configured and may induce use of such configurations by such
`third-parties by providing information about how to configure PVD reactors for use in production
`of Intel semiconductor products, working or partnering with third-parties to develop and market
`products produced using the patented PVD reactor configurations, and by providing such third-
`parties with technical support, as just a few representative examples. Non-limiting examples of
`these and other actions that may support Demaray’s indirect infringement allegations can be found
`on Intel’s website and third-party websites, among numerous other public sources.
`As another example, Intel may actively and intentionally cause infringement with both
`knowledge of the patents-in-suit and the specific intent to cause use of PVD reactors configured as
`required by the Asserted Claims. Production of certain of Intel’s semiconductor products requires
`use of PVD reactors that are configured in an infringing manner and Intel may actively work with
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`third-parties to develop and manufacture Intel semiconductor products using these processes in
`reactors configured in an infringing manner.
`Intel’s actions may further constitute contributory infringement. For example, on
`information and belief, Intel may supply or caused to be supplied from the United States, PVD
`reactors to third-parties configured in a way such that they are especially made or adapted for use
`in an infringing manner and are not staple articles or commodities of commerce suitable for
`substantial non-infringing uses or by encouraging or requiring third-parties to use PVD reactors so
`configured. The PVD reactors as configured may be especially designed to be used in the design,
`development and manufacture of Intel semiconductor products as discussed above.
`Specific examples of detailed acts of infringement that may be being induced and
`contributed to by Intel are set forth in more detail in Exhibits A-B. For the configured PVD
`reactors and semiconductor products produced using the infringing processes, Intel may provide
`specific instructions on both the characteristics and performance requirement of such
`semiconductor products, and the reactor configurations, including infringing reactor
`configurations, required for the production thereof. Thus, Intel’s indirect infringement may occur
`in connection with each such semiconductor product through the provision of such information
`and support to, for example, third-parties involved in the design and manufacture of such
`semiconductor products.
`Demaray incorporates by reference the allegations in its Complaint, along with the analysis
`in the attached charts (Exhibits A-B) with respect to Intel’s direct and indirect infringing activity.
`Demaray further expects Intel to produce documents and information during the course of
`discovery that will support Demaray’s direct and indirect infringement allegations.
`V.
`Production Of Documents
`
`As specified in the Court’s Order Governing Proceedings – Patent Case, Demaray is
`producing (1) documents currently in Demaray’s possession, custody or control evidencing
`conception and reduction to practice for each claimed invention and (2) a copy of the file history
`for each patent-in-suit in this action by production numbers: DEMINT00000001–3160, 3442–98.
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`Demaray consents to sharing documents indicated with the legend “HIGHLY CONFIDENTIAL -
`OUTSIDE COUNSEL EYES ONLY” only with Intel’s outside counsel of record.
`Demaray’s efforts to collect such documents from third-parties, including previous
`assignees of the relevant patents, remains ongoing. Demaray will promptly produce to Intel any
`such non-privileged documents that it may receive after the date of these Preliminary Infringement
`Contentions.
`VI.
`Identification Of Priority Date
`
`As specified in the Court’s Order Governing Proceedings – Patent Case, the inventions of
`the Asserted Claims are currently believed to have been conceived
`and reduced to practice at least as early, and possibly earlier
`. Alternatively, at a minimum, the Asserted Claims of the
`asserted patents are entitled to a priority date of at least as early as March 16, 2002, which is the
`filing date of U.S. Utility App. No. 10/101,863.
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`Dated: October 9, 2020
`
`By:
`
`/s/ C. Maclain Wells
`
`C. Maclain Wells (pro hac vice)
`IRELL & MANELLA LLP
`1800 Avenue of the Stars, Suite 900
`Los Angeles, California 90067
`Telephone: (310) 277-1010
`Facsimile: (310) 203-7199
`mwells@irell.com
`
`Attorneys for Demaray LLC
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`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 9 of 39
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`CERTIFICATE OF SERVICE
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`I am employed in the County of Los Angeles, State of California. I am over the age of 18
`and not a party to the within action. My business address is 1800 Avenue of the Stars, Suite 900,
`Los Angeles, California 90067-4276.
`
`On October 9, 2020, I served the foregoing instrument and associated attachments on all
`counsel of record.
`
`X
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`(BY ELECTRONIC MAIL) I caused the foregoing document to be served
`electronically by electronically mailing a true and correct copy through Irell &
`Manella LLP's electronic mail system to the e-mail address(es), as stated on the
`attached service list, and the transmission was reported as complete and no error
`was reported.
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`Executed on October 9, 2020, at Sebastopol, California.
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`I declare under penalty of perjury under the laws of the State of California that the
`foregoing is true and correct.
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`
`
`C. Maclain Wells
`(Type or print name)
`
`/s/ C. Maclain Wells
`(Signature)
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`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 10 of 39
`Exhibit A – Claim Chart for U.S. Patent No. 7,544,276
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`As used herein and with respect to the ’276 Patent, and based on Demaray’s present understanding, the term “Intel Accused
`Products” means each of the following items that were made, used, imported, offered for sale or sold1 by Intel Corporation, including by
`all subsidiaries, affiliates, or third-parties under Intel’s control (individually and collectively, “Intel”), on or after July 14, 2014:
`
`(a) all physical-vapor-deposition (“PVD”) reactors configured according to the ’276 Patent and used in the manufacture of Intel
`products or elements thereof, which includes reactive-magnetron-sputtering (“RMS”) reactors configured according to the ’276
`Patent and used by Intel in the production of its semiconductor products (“Intel PVD Reactors”);
`
`(b) all Intel PVD Reactors configured according to the ’276 Patent and used in the manufacture of at least the following Intel
`microprocessor products and variants thereof:
`
`Apparent Release Year
`2014
`2015
`2016
`2017
`2018
`2019
`2020
`
`Microprocessor
`Broadwell
`Skylake, Airmont
`Kaby Lake, Goldmont
`Coffee Lake
`Cannon Lake, Amber Lake, Whiskey Lake
`Cascade Lake, Comet Lake, Ice Lake
`Cooper Lake, Tiger Lake
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`(c) all Intel PVD Reactors configured according to the ’276 Patent and used in the manufacture of other Intel microprocessors;
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`(d) all Intel PVD Reactors configured according to the ’276 Patent and used in the manufacture of any Intel products other than
`microprocessors (including, for example and without limitation, Intel chipsets, network interface controllers, network adaptors,
`memories, graphics chips, controllers, FPGAs, baseband processors, modems, transceivers, embedded processors and other
`devices related to communications and computing), as well as use of the Intel PVD Reactors configured according to the ’276
`Patent to make any other Intel non-microprocessor products in the same or materially the same manner as described below; and
`
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`1 References in items (a) – (e) below to a product being “used” in any way should be understood to include any or all of these five
`infringing actions.
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`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 11 of 39
`Exhibit A – Claim Chart for U.S. Patent No. 7,544,276
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`(e) all Intel PVD Reactors configured according to the ’276 Patent and used in the manufacture of any Intel wafers or chips,
`packaged or unpackaged, that constitute or contain semiconductor products within the foregoing descriptions.
`
`This claim chart for the ’276 Patent is intended to cover all Intel Accused Products. The theory of infringement described below in
`connection with the asserted claims is believed to be analogous to the theory of infringement for all Intel Accused Products.
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`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 12 of 39
`Exhibit A – Claim Chart for U.S. Patent No. 7,544,276
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`’276 Patent
`
`Intel Accused Products
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`1. A reactor according
`to the present
`invention, comprising:
`
`Intel Accused Products2 are reactors according to the present invention and Intel uses such reactors in a variety
`of infringing ways in the production of Intel semiconductor products.
`
`For instance, Intel deposits
`layers (including, e.g., metal nitride layers, such as TaN barrier layers and/or TiN hardmask layers) on
`insulating substrates (e.g., semiconductor wafers) in the production of its semiconductor products, including,
`but not limited to, Intel processors and the other Intel products identified above using Intel Accused Products at
`its fabrication plants and research facilities, including but not limited to premises within the United States.
`
`As a specific example, Intel has deposited such layers in its microprocessors using Intel Accused Products since
`the introduction of its Broadwell Processors in 2014. See, e.g., Dkt. No. 19 (Answer) (for example, see
`specifically ¶¶ 25 (“Intel admits that it uses RMS reactors for deposition of layers in its semiconductor
`products.”), 50 (“Intel admits that it deposits certain TaN and/or TiN layers for certain of its Broadwell
`Processors, which are fabricated using silicon wafers.”)).
`
`As a further example, Intel configures and uses, among other reactors, Intel Accused Products in the Endura
`product line from Applied Materials, Inc. for deposition of such layers (including, e.g., metal nitride layers,
`such as TaN barrier layers and/or TiN hardmask layers) in its semiconductor products. Intel has identified
`Applied Materials as a Preferred Quality Supplier. DEMINT00003440–41. On information and belief, Intel can
`modify these reactors for application-specific processes to deposit specific materials. For example, the Endura
`product line includes reactors that can be configured for deposition of TaN layers (e.g., CuBS RFX PVD with
`the Encore II Ta(N) barrier chamber) and TiN layers (e.g., Cirrus ionized PVD chamber). See, e.g.,
`DEMINT00003382–83 (TaN layers); DEMINT00003376–77 (TiN layers).
`
`2 In the interests of brevity, these charts refer primarily to Intel, and Intel’s activities and equipment. Nonetheless, Demaray’s
`infringement theories include Intel potentially having others practice the asserted claims on its behalf, and other forms of infringement, as
`described in the cover document served with these charts and hereby incorporated within the charts.
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`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 13 of 39
`Exhibit A – Claim Chart for U.S. Patent No. 7,544,276
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`As an example, a reactor from Applied Materials is shown below:
`
`As a further example, Intel may modify or caused to be modified reactors from Applied Materials with
`application-specific process kits to deposit specific materials. The Endura product line includes reactors that can
`be configured for deposition of TaN layers (e.g., CuBS RFX PVD with the Encore II Ta(N) barrier chamber)
`and TiN layers (e.g., Cirrus ionized PVD chamber). See, e.g., DEMINT00003382–83 (TaN layers),
`DEMINT00003376–77 (TiN layers).
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`As an example, an image of an Endura CuBS RFX PVD is shown below:
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`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 14 of 39
`Exhibit A – Claim Chart for U.S. Patent No. 7,544,276
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`To the extent the claim preamble is deemed limiting, Intel Accused Products thus meet this limitation.
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`[a] a target area for
`receiving a target;
`
`The Intel Accused Products comprise a target area for receiving a target and Intel uses such reactors configured
`as required in a variety of infringing ways in the production of Intel semiconductor products.
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`As an example, for Intel Accused Products, “[i]n PVD, the target is the source of the material to be deposited.
`Atoms are ejected from the target as a result of the bombardment of energetic particles.” DEMINT00003432;
`see Dkt. No. 19 (Answer) (for example, see specifically ¶ 51 (“Intel admits that it fabricates semiconductor
`products in part by using a process gas, a target, and a substrate.”)).
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`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 15 of 39
`Exhibit A – Claim Chart for U.S. Patent No. 7,544,276
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`As a further example, Intel uses Intel Accused Products configured according to the ’276 Patent for depositing
`TaN in certain of its semiconductor products. In such configurations, tantalum is the source material (i.e., the
`metal target). The reactors as configured include a target area (indicated as “target” in the image below) for
`receiving the tantalum:
`
`DEMINT00003241–93 (for example, see specifically at DEMINT00003285 (Fig. 1)) (annotated).
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`As an example, the target and target area in an Endura PVD reactor is shown below:
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`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 16 of 39
`Exhibit A – Claim Chart for U.S. Patent No. 7,544,276
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`[b] a substrate area
`opposite the target
`area for receiving a
`substrate;
`
`The Intel Accused Products comprise a substrate area opposite the target area for receiving a substrate and Intel
`uses such reactors configured as required in a variety of infringing ways in the production of Intel
`semiconductor products.
`
`As an example, for Intel Accused Products a substrate is “[t]he material upon which thin films are manipulated.
`Silicon is most commonly used for semiconductors ....” DEMINT00003431; see Dkt. No. 19 (Answer) (for
`example, see specifically ¶ 51 (“Intel admits that it fabricates semiconductor products in part by using a process
`gas, a target, and a substrate.”)).
`
`As a further example, the substrate in Intel Accused Products configured according to the ’276 Patent for
`deposition of a TaN barrier layer in the Broadwell Processors, for instance, is a silicon wafer. The reactors as
`configured include a substrate area is opposite the target area for receiving the silicon substrates (indicated as
`“wafer”) as illustrated below:
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`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 17 of 39
`Exhibit A – Claim Chart for U.S. Patent No. 7,544,276
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`See DEMINT00003241–93 (for example, see specifically at DEMINT00003285 (Fig. 1)) (annotated).
`
`As an example, the substrate area in an Endura PVD reactor is shown below:
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`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 18 of 39
`Exhibit A – Claim Chart for U.S. Patent No. 7,544,276
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`[c] a pulsed DC power
`supply coupled to the
`target area, the pulsed
`DC power supply
`providing alternating
`negative and positive
`voltages to the target;
`
`The Intel Accused Products comprise a pulsed DC power supply coupled to the target area, the pulsed DC
`power supply providing alternating negative and positive voltages to the target and Intel uses such reactors
`configured as required in a variety of infringing ways in the production of Intel semiconductor products.
`
`For example, in Intel Accused Products configured according to the ’276 Patent a power source is coupled to
`the target area as illustrated below:
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`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 19 of 39
`Exhibit A – Claim Chart for U.S. Patent No. 7,544,276
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`See DEMINT00003241–93 (for example, see specifically at DEMINT00003285 (Fig. 1)) (annotated).
`
`As a further example, the presence of a DC power unit in a reactor for RMS deposition (e.g., TaN when using a
`tantalum target and a process gas that includes nitrogen) is illustrated below:
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`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 20 of 39
`Exhibit A – Claim Chart for U.S. Patent No. 7,544,276
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`See DEMINT00003214–32 (for example, see specifically at DEMINT00003222 (“DC” power supply in 1st
`generation iPVD products).
`
`As an example, a pulsed DC power unit in an Endura reactor configured for RMS deposition (e.g., TaN, when
`using a tantalum target and a process gas that includes nitrogen) is shown below:
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`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 21 of 39
`Exhibit A – Claim Chart for U.S. Patent No. 7,544,276
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`[d] an RF bias power
`supply coupled to the
`substrate; and
`
`The Intel Accused Products comprise an RF bias power supply coupled to the substrate and Intel uses such
`reactors configured as required in a variety of infringing ways in the production of Intel semiconductor
`products.
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`For example, in Intel Accused Products configured according to the ’276 Patent a power supply is coupled to
`the substrate area to bias the substrate as illustrated below:
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`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 22 of 39
`Exhibit A – Claim Chart for U.S. Patent No. 7,544,276
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`See DEMINT00003241–93 (for example, see specifically at DEMINT00003285 (Fig. 1)) (annotated).
`
`As an example, the presence of an RF bias power supply in an Endura reactor for RMS deposition (e.g., TaN,
`when using a tantalum target and a process gas that includes nitrogen) is shown below:
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`[e] a narrow band-
`rejection filter that
`rejects at a frequency
`of the RF bias power
`supply coupled
`between the pulsed
`DC power supply and
`the target area.
`
`The Intel Accused Products comprise a narrow band-rejection filter that rejects at a frequency of the RF bias
`power supply coupled between the pulsed DC power supply and the target area and Intel uses such reactors
`configured as required in a variety of infringing ways in the production of Intel semiconductor products.
`
`For example, in Intel Accused Products configured according to the ’276 Patent, a narrowband filter is coupled
`between the pulsed DC power supply and the target area in a reactor for deposition of tantalum nitride (when
`using a tantalum target and a process gas that includes nitrogen). A narrowband filter is used in the Intel
`Accused Products as configured to, for example, protect the pulsed DC power supply from feedback from the
`RF bias power supply.
`
`10882778
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`

`

`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 23 of 39
`Exhibit B – Claim Chart for U.S. Patent No. 7,381,657
`
`As used herein and with respect to the ’657 Patent and based on Demaray’s present understanding, the term “Intel Accused
`Products” means each of the following items that were made, used, imported, offered for sale or sold by Intel Corporation, including by
`all subsidiaries, affiliates, and third-parties under Intel’s control (individually and collectively, “Intel”), on or after July 14, 2014:
`
`(a) all Intel semiconductor products that include at least one layer of material deposited according to the ’657 Patent, which to
`Demaray’s present understanding includes at least the following Intel microprocessor products and variants thereof:
`
`Apparent Release Year
`2014
`2015
`2016
`2017
`2018
`2019
`2020
`
`Microprocessor
`Broadwell
`Skylake, Airmont
`Kaby Lake, Goldmont
`Coffee Lake
`Cannon Lake, Amber Lake, Whiskey Lake
`Cascade Lake, Comet Lake, Ice Lake
`Cooper Lake, Tiger Lake
`
`(b) all subsequent Intel microprocessor products that include at least one layer of material deposited according to the ’657 Patent, as
`well as any other microprocessor products that include at least one layer of material manufactured in the same or materially the
`same manner as described below;
`
`(c) all Intel products other than microprocessors (including, for example and without limitation, Intel chipsets, network interface
`controllers, network adaptors, memory and storage devices, graphics chips, controllers, FPGAs, baseband processors, modems,
`transceivers, embedded processors and other devices related to communications and computing), that include at least one layer of
`material deposited according to the ’657 Patent, as well as any other Intel non-microprocessor products that include at least one
`layer of material manufactured in the same or materially the same manner as described below;
`
`(d) any other Intel semiconductor products that infringe the asserted claims for analogous reasons to those described below; and,
`
`(e) any Intel wafers or chips, packaged or unpackaged, that constitute or contain products within the foregoing descriptions.
`
`This claim chart for the ’657 Patent is intended to cover all Intel Accused Products. The theory of infringement described below in
`connection with the asserted claims is believed to be analogous to the theory of infringement for all Intel Accused Products.
`
`10881964
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`

`

`Case 5:20-cv-05676-EJD Document 42-7 Filed 12/07/20 Page 24 of 39
`Exhibit B – Claim Chart for U.S. Patent No. 7,381,657
`
`’657 Patent
`
`Intel Accused Products
`
`1. A method of
`depositing a film on an
`insulating substrate,
`comprising:
`
`Intel practices1 a method of depositing a film on an insulating substrate in a variety of ways in the production of
`the Intel Accused Products.
`
`. For instance, Intel deposits layers (including, e.g.,
`metal nitride layers, such as TaN barrier layers and/or TiN hardmask layers) on insulating substrates (e.g.,
`semiconductor wafers) in the production of its semiconductor products, including, but not limited to, Intel
`processors and the other Intel Accused Products identified above.
`
`As a specific example, Intel has deposited such layers in its microprocessors since the introduction of its
`Broadwell Processors in 2014. See, e.g., Dkt. No. 19 (Answer) (for example, see specifically ¶¶ 25 (“Intel
`admits that it uses RMS reactors for deposition of layers in its semiconductor products.”), 50 (“Intel admits that
`it deposits certain TaN and/or TiN layers for certain of its Broadwell Processors, which are fabricated using
`silicon wafers.”)).
`
`As a further example, Intel uses, among other reactors, reactors in the Endura product line from Applied
`Materials, Inc. for deposition of such layers (including, e.g., metal nitride layers, such as TaN barrier layers
`and/or TiN hardmask layers) in its semiconductor products. Intel has identified Applied Materials as a Preferred
`Quality Supplier. DEMINT00003440–41. On information and belief, these reactors can be modified for
`application-specific processes to deposit specific materials. For example, the Endura product line includes
`reactors that can be configured for deposition of TaN layers (e.g., CuBS RFX PVD with the Encore II Ta(N)
`barrier ch