Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 1 of 83
`Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 1 of 83
`
`
`
`EXHIBIT 6
`EXHIBIT 6
`
`

`

`USO09529958B2
`
`(12) United States Patent
`Konda
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 9,529,958 B2
`*Dec. 27, 2016
`
`(54)
`
`VLSI LAYOUTS OF FULLY CONNECTED
`GENERALIZED AND PYRAMD NETWORKS
`WITH LOCALITY EXPLOITATION
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`(71)
`
`Applicant: Konda Technologies Inc., San Jose,
`CA (US)
`
`(72)
`
`Inventor: Venkat Konda, San Jose, CA (US)
`
`(73)
`
`Assignee: Konda Technologies Inc., San Jose,
`CA (US)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`This patent is Subject to a terminal dis
`claimer.
`
`(21)
`
`Appl. No.: 14/522,599
`
`(22)
`
`Filed:
`
`Oct. 24, 2014
`
`(65)
`
`Prior Publication Data
`US 2015/OO46895 A1
`Feb. 12, 2015
`
`(51)
`
`(52)
`
`(58)
`
`(2006.01)
`
`Int. C.
`G06F 7/50
`U.S. C.
`CPC ................................. G06F 17/5077 (2013.01)
`Field of Classification Search
`CPC .............. G06F 17/5054: G06F 15/7867; G06F
`15/8015; G06F 17/5077; G06F 12/0897;
`G06F 12/123; G06F 17/509; G06F
`2212/271; G06F 3/017: G06F 11/1438:
`G06F 11/1441; G06F 15/08; G06F 17/13;
`G06F 17/30; G06F 19/3418; G06F
`19/322; G06F 19/3406; B65B
`7/164: G06T 1/20
`
`(Continued)
`
`6,335,930 B1* 1/2002 Lee ............................... 370,387
`8,269,523 B2 * 9/2012 Konda ................ GO6F 17,5077
`326/38
`
`(Continued)
`Primary Examiner — Binh Tat
`(57)
`ABSTRACT
`VLSI layouts of generalized multi-stage and pyramid net
`works for broadcast, unicast and multicast connections are
`presented using only horizontal and vertical links with
`spacial locality exploitation. The VLSI layouts employ
`shuffle exchange links where outlet links of cross links from
`Switches in a stage in one Sub-integrated circuit block are
`connected to inlet links of Switches in the Succeeding stage
`in another Sub-integrated circuit block so that said cross
`links are either vertical links or horizontal and vice versa.
`Furthermore the shuffle exchange links are employed
`between different sub-integrated circuit blocks so that spa
`cially nearer Sub-integrated circuit blocks are connected
`with shorter links compared to the shuffle exchange links
`between spacially farther sub-integrated circuit blocks. In
`one embodiment the Sub-integrated circuit blocks are
`arranged in a hypercube arrangement in a two-dimensional
`plane. The VLSI layouts exploit the benefits of significantly
`lower cross points, lower signal latency, lower power and
`full connectivity with significantly fast compilation. The
`VLSI layouts with spacial locality exploitation presented are
`applicable to generalized multi-stage and pyramid networks,
`generalized folded multi-stage and pyramid networks, gen
`eralized butterfly fat tree and pyramid networks, generalized
`multi-link multi-stage and pyramid networks, generalized
`folded multi-link multi-stage and pyramid networks, gener
`alized multi-link butterfly fat tree and pyramid networks,
`generalized hypercube networks, and generalized cube con
`nected cycles networks for speedup of sa1. The embodi
`ments of VLSI layouts are useful in wide target applications
`such as FPGAs, CPLDs, pSoCs, ASIC placement and route
`tools, networking applications, parallel & distributed com
`puting, and reconfigurable computing.
`
`20 Claims, 43 Drawing Sheets
`
`Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 2 of 83
`
`s
`
`Recieve request to form a connection from an inlet link of an input switch
`
`From each outgoing middle link of the input switch, recursively derive the
`lists of reachable middle switches in each middle stage, traveling forward
`from middle stage 1 to middle stage Log N
`
`1010
`
`12
`
`Mark all the middle
`links betwee all
`the stages used to
`set up the
`connection, so that
`they are
`Urawailable for
`other connections
`
`1030
`
`From the output switch of each destination, recursively derive the the list of 1030
`middle switches, from which the destination is reachable, in each middle
`stage, traveling backwards from output stage to middle stage Log N
`
`1040
`w
`Using the lists generated in the previous two steps, by matching up the corresponding
`available middle switches in the middle stage LogN, generate the lists of reachable
`destinations starting from each outgoing middle link of the input switch
`
`one outgoing middle link from YEs
`the input switch, by taking the
`nearest U-turn for each
`destinatic
`
`
`
`Set up the connection through
`two outgoing middle links from
`the input switch, by taking the
`nearest U-turn for each
`destination
`
`
`
`hereasingle outgoing middle linkfor-the
`input switch through which all destinations are
`reachable
`
`150
`X
`
`Find two outgoing middle links from the 100
`input switch through which all the
`destinations are reachable
`
`
`
`

`

`US 9,529,958 B2
`Page 2
`
`(58) Field of Classification Search
`USPC .................................................. 71.6/126 130
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`8,898,611 B2 * 1 1/2014 Konda .......................... T16,121
`2012/0269.190 A1* 10, 2012 Konda .................. GO6F 17,509
`370,388
`2014/031393.0 A1* 10, 2014 Konda ................ HO4L 49.1515
`370,254
`2/2015 Konda .................. HO4L 49,102
`370,411
`
`2015.0049768 A1
`
`* cited by examiner
`
`Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 3 of 83
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`

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`Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 4 of 83
`18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 4 of 83
`Case 5
`
`U.S. Patent
`
`Dec. 27, 2016
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`Sheet 1 of 43
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`US 9,529,958 B2
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`Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 5 of 83
`Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 5 of 83
`
`U.S. Patent
`
`Dec. 27, 2016
`
`Sheet 2 of 43
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`US 9,529,958 B2
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`Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 6 of 83
`18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 6 of 83
`Case 5
`
`U.S. Patent
`
`Dec. 27, 2016
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`Sheet 3 of 43
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`U.S. Patent
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`Dec. 27, 2016
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`Sheet 4 of 43
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`US 9,529,958 B2
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`Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 7 of 83
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`--------------------------------------
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`U.S. Patent
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`Dec. 27, 2016
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`U.S. Patent
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`Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 9 of 83
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`U.S. Patent
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`Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 10 of 83
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`U.S. Patent
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`Dec. 27, 2016
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`Sheet 8 of 43
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`Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 11 of 83
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`&###############################
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`

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`U.S. Patent
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`Dec. 27, 2016
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`Sheet 9 of 43
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`Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 12 of 83
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`U.S. Patent
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`Dec. 27, 2016
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`Sheet 10 of 43
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`Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 19 of 83
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`Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 20 of 83
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`Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 26 of 83
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`Dec. 27, 2016
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`US 9,529,958 B2
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`1.
`VLSI LAYOUTS OF FULLY CONNECTED
`GENERALIZED AND PYRAMD NETWORKS
`WITH LOCALITY EXPLOITATION
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`
`This is a Continuation Application and claims priority of
`U.S. patent application Ser. No. 13/502.207 entitled “VLSI
`LAYOUTS OF FULLY CONNECTED GENERALIZED
`AND PYRAMID NETWORKS WITH LOCALITY
`EXPLOITATION” by Venkat Konda assigned to the same
`assignee as the current application and filed Apr. 16, 2012,
`which is incorporated by reference in its entirety. This
`application is related to and incorporates by reference in its
`entirety the PCT Application Serial No. PCT/US10/52984
`entitled VLSI LAYOUTS OF FULLY CONNECTED
`GENERALIZED AND PYRAMID NETWORKS WITH
`LOCALITY EXPLOITATION” by Venkat Konda assigned
`to the same assignee as the current application, filed Oct. 16.
`2010, the U.S. Provisional Patent Application Ser. No.
`61/252,603 entitled “VLSI LAYOUTS OF FULLY CON
`NECTED NETWORKS WITH LOCALITY EXPLOITA
`TION’ by Venkat Konda assigned to the same assignee as
`the current application, filed Oct. 16, 2009, and the U.S.
`Provisional Patent Application Ser. No. 61/252,609 entitled
`VLSI LAYOUTS OF FULLY CONNECTED GENERAL
`IZED AND PYRAMID NETWORKS by Venkat Konda
`assigned to the same assignee as the current application,
`filed Oct. 16, 2009.
`This application is related to and incorporates by refer
`ence in its entirety the U.S. Pat. No. 8,270,400 entitled
`FULLY CONNECTED GENERALIZED MULTI-STAGE
`NETWORKS” by Venkat Konda assigned to the same
`assignee as the current application, issued Sep. 18, 2012, the
`U.S. Provisional Patent Application Ser. No. 60/905,526
`entitled LARGE SCALE CROSSPOINT REDUCTION
`WITH NONBLOCKING UNICAST & MULTICAST IN
`ARBITRARILY LARGE MULTI-STAGE NETWORKS
`by Venkat Konda assigned to the same assignee as the
`current application, filed Mar. 6, 2007, and the U.S. Provi
`sional Patent Application Ser. No. 60/940,383 entitled
`FULLY CONNECTED GENERALIZED MULTI-STAGE
`NETWORKS” by Venkat Konda assigned to the same
`assignee as the current application, filed May 25, 2007.
`This application is related to and incorporates by refer
`ence in its entirety the U.S. Pat. No. 8,170,040 entitled
`FULLY CONNECTED GENERALIZED BUTTERFLY
`FAT TREE NETWORKS by Venkat Konda assigned to the
`same assignee as the current application, issued May 1,
`2012, the U.S. Provisional Patent Application Ser. No.
`60/940,387 entitled “FULLY CONNECTED GENERAL
`IZED BUTTERFLY FAT TREE NETWORKS by Venkat
`Konda assigned to the same assignee as the current appli
`cation, filed May 25, 2007, and the U.S. Provisional Patent
`55
`Application Ser. No. 60/940,390 entitled “FULLY CON
`NECTED GENERALIZED MULTI-LINK BUTTERFLY
`FAT TREE NETWORKS by Venkat Konda assigned to the
`same assignee as the current application, filed May 25, 2007
`This application is related to and incorporates by refer
`ence in its entirety the U.S. Pat. No. 8.363,649 entitled
`FULLY CONNECTED GENERALIZED MULTI-LINK
`MULTI-STAGE NETWORKS” by Venkat Konda assigned
`to the same assignee as the current application, issued Jan.
`29, 2013, the U.S. Provisional Patent Application Ser. No.
`65
`60/940,389 entitled “FULLY CONNECTED GENERAL
`IZED REARRANGEABLY NONBLOCKING MULTI
`
`10
`
`15
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`60
`
`Case 5:18-cv-07581-LHK Document 31-6 Filed 03/04/19 Page 47 of 83
`
`2
`LINK MULTI-STAGE NETWORKS by Venkat Konda
`assigned to the same assignee as the current application,
`filed May 25, 2007, the U.S. Provisional Patent Application
`Ser. No. 60/940,391 entitled “FULLY CONNECTED GEN
`ERALIZED FOLDED MULTI-STAGE NETWORKS by
`Venkat Konda assigned to the same assignee as the current
`application, filed May 25, 2007 and the U.S. Provisional
`Patent Application Ser. No. 60/940,392 entitled “FULLY
`CONNECTED GENERALIZED STRICTLY NON
`BLOCKING MULTI-LINK MULTI-STAGE NET
`WORKS by Venkat Konda assigned to the same assignee
`as the current application, filed May 25, 2007.
`This application is related to and incorporates by refer
`ence in its entirety the U.S. Pat. No. 8.269,523 entitled
`VLSI LAYOUTS OF FULLY CONNECTED GENERAL
`IZED NETWORKS by Venkat Konda assigned to the same
`assignee as the current application, issued Sep. 18, 2012, the
`PCT Application Serial No. PCT/U08/64605 entitled “VLSI
`LAYOUTS OF FULLY CONNECTED GENERALIZED
`NETWORKS” by Venkat Konda assigned to the same
`assignee as the current application, filed May 22, 2008, and
`the U.S. Provisional Patent Application Ser. No. 60/940,394
`entitled VLSI LAYOUTS OF FULLY CONNECTED
`GENERALIZED NETWORKS” by Venkat Konda assigned
`to the same assignee as the current application, filed May 25,
`2007.
`This application is related to and incorporates by refer
`ence in its entirety the U.S. application Ser. No. 14/199,168
`entitled OPTIMIZATION OF MULTI-STAGE HIERAR
`CHICAL NETWORKS FOR PRACTICAL ROUTING
`APPLICATIONS” by Venkat Konda assigned to the same
`assignee as the current application, filed Mar. 6, 2014 and
`the PCT Application Serial No. PCT/US 12/53814 entitled
`“OPTIMIZATION OF MULTI-STAGE HIERARCHICAL
`NETWORKS FOR PRACTICAL ROUTING APPLICA
`TIONS''' by Venkat Konda assigned to the same assignee as
`the current application, filed Sep. 6, 2012, and both of them
`in turn are Continuation in Part applications to the U.S.
`Provisional Patent Application Ser. No. 61/531,615 entitled
`“OPTIMIZATION OF MULTI-STAGE HIERARCHICAL
`NETWORKS FOR PRACTICAL ROUTING APPLICA
`TIONS''' by Venkat Konda assigned to the same assignee as
`the current application, filed Sep. 7, 2011.
`This application is related to and incorporates by refer
`ence in its entirety the U.S. application Ser. No. 14/329,876
`entitled “FAST SCHEDULING AND OPTIMIZATION OF
`MULTI-STAGE HIERARCHICAL NETWORKS” by
`Venkat Konda assigned to the same assignee as the current
`application, filed Jul. 11, 2014 and the U.S. Provisional
`Patent Application Ser. No. 61/846,083 entitled “FAST
`SCHEDULING AND OPTIMIZATION OF MULTI
`STAGE HIERARCHICALNETWORKS by Venkat Konda
`assigned to the same assignee as the current application,
`filed Jul