Case 5:18-cv-07581-LHK Document 31-14 Filed 03/04/19 Page 1 of 3
`Case 5:18-cv-07581-LHK Document 31-14 Filed 03/04/19 Page 1 of 3
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`EXHIBIT 14
`EXHIBIT 14
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`EXHIBIT 14
`EXHIBIT 14
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`

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`Case 5:18-cv-07581-LHK Document 31-14 Filed 03/04/19 Page 2 of 3
`GF14LPP EFLX®4K Gen 2 TARGET SPEC
`
`The EFLX®4K Logic IP core is an embeddable FPGA IP core containing 2,520 Look-Up-Tables
`(LUTs: each is 6-input, or dual-5-input, with 2 independent outputs with 2 bypassable flip flops)
`in Reconfigurable Building Blocks (RBBs) and 21Kbits RAM, an improved XFLX™ interconnect
`network, multiple clocks & scan: fully reconfigurable in-field at any time.
`The EFLX4K DSP core
`Name
`has 40 DSP MACs (22x22
`Technology
`multiplier with 48 bit
`Metal Stack
`accumulator). In the Gen2
`Nominal Supply Voltages (Vj)
`architecture,
`MACs
`Junction Temperature (°C)
`cascade up to 10 stages
`Leakage Power
`without
`using
`the
`Area (mm2)
`interconnect network.
`Clock inputs
`Each EFLX core is a
`Input and Output Pins
`standalone
`embedded
`FPGA.
` Cores can be
`Look-up Tables
`arrayed up to at least 7x7
`(6-input LUT with two
`to create arrays of up to
`independent outputs)
`~200K+ LUT4s. Logic and
`Total Flip Flops (ex DSP)
`DSP cores can be mixed.
`Distributed Memory (Kb)
`And
`RAM
`can
`be
`22-bit DSP MACs
`integrated as well.
`EFLX Array Sizes Possible
`Our improved, Gen 2
`Design-for-Test Support
`XFLX
`programmable
`LUT Utilization
`interconnect has been
`optimized for higher performance, especially for large arrays.
`
`EFLX®4K Core Gen 2
`GlobalFoundries 14LPP
`Optimized for GF 13 Metal Stack
`0.6, 0.7, 0.8, 0.9
`−40 to 125
`3.5mW (NN, 0.8Vj, 25C Tj)
`~1.28
`Mesh, multiple access points
`632 input & 632 output, each
`with an optional flip flop
`Logic/Mem Core
`DSP Core
`2,520
`1,880
`(~4.0K LUT4)
`(~3.0K LUT4)
`6,304
`5,024
`21Kbits
`1Kbits
`0
`40
`1×1 to at least 7×7
`Yes, 99% fault coverage
`Typically ~90%
`
`EFLX features full connectivity
`inside the core, and provides
`ArrayLinx™ interconnects at the
`boundary to concatenate multiple
`cores: ~50 array sizes are possible
`from 4,000 LUT4s up to ~200K LUT4s.
`
`Gen 2 DFT improvements achieve
`99% coverage of all faults & a new
`configuration
`load mode for test
`reduces test times about 100 times
`faster than Gen 1 to lower test costs.
`
`
`
`
`May 2018. Copyright 2014-2018 Flex Logix® Technologies, Inc.
`EFLX®, Flex Logix®, XFLX, ArrayLinx are Trademarks of Flex Logix Technologies
`
`

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`Case 5:18-cv-07581-LHK Document 31-14 Filed 03/04/19 Page 3 of 3
`
`GF 14LPP EFLX4K Core
`
`
`May 2018
`
`www.flex-logix.com page 2
`
`The EFLX4K Core has 632 input
`pins and 632 output pins placed as
`follows: 64 West, 64 East, 252
`North, and 252 South. The I/O pins
`provide user access to the EFLX
`core. Each pin has a bypassable flip
`flop. When multiple cores are
`concatenated into EFLX arrays, the
`pins along the abutting edges are
`disabled
`(or
`are
`used
`for
`controlling
`embedded
`RAM
`blocks).
`Besides input/output pins, there are clock, configuration, and test/DFT pins. Each Core has
`an internal power grid which can be connected to the customer’s digital SoC power grid. The Core
`has power control pins. The Core also has configuration inputs on the West side and configuration
`inputs on the South side to load the bitstream. An AXI or JTAG interface is available for
`configuration. A clock mesh provides multiple connect points. The configuration bits can be read
`back anytime to enable checking for soft errors to improve reliability for high-reliability
`applications. A new test mode enables test times about 100x faster for lower test cost.
`
`GF14 EFLX4K dimensions: 0.95mm wide x 1.35mm tall
`
`Deliverables and EDA Design Views
`Front-end Design view (with NDA)
`Back-end Design Views (with License)
`Encrypted Verilog Netlist with Timing Annotation &
`Encrypted Verilog Netlist
`SDF
`LIB
`GDS-II
`Footprint LEF
`CDL/Spice netlist
`Detailed datasheet & DSP User’s Guide
`Integration guidelines & assistance
`Silicon validation report, when ready
`Test Vectors for DFT fault coverage of 99%
`EFLX Compiler evaluation version
`EFLX Compiler bitstream generation version
`
`
`
`
`May 2018. Copyright 2014-2018 Flex Logix Technologies, Inc.
`
`