Case 5:18-cv-07581-LHK Document 31-11 Filed 03/04/19 Page 1 of 3
`Case 5:18-cv-07581-LHK Document 31-11 Filed 03/04/19 Page 1 of 3
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`EXHIBIT 11
`EXHIBIT 11
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`EXHIBIT 11
`EXHIBIT 11
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`

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`Case 5:18-cv-07581-LHK Document 31-11 Filed 03/04/19 Page 2 of 3
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`IO
`
`RBB Logic
`
`IO
`
`RBB Logic
`
`IO
`
`RBB Logic
`
`
`
`IO
`
`TSMC 40ULP/LP EFLX®100 CORE PRODUCT BRIEF
`The EFLX®100 is an embedded FPGA IP core, for implementing reconfigurable logic,
`containing 120 Look-Up-Tables (LUTs: each is a dual 4-input LUT with 2 independent outputs
`and 2 bypassable flip flops) in Reconfigurable Building Blocks (RBBs), patented XFLX
`interconnect network, multiple clocks & scan: reconfigurable at any time. Target specs:
` EFLX100 Logic Core
`Name
`EFLX100 Core
`
`Technology
`TSMC 40nm ULP/LP CMOS
`Metal Utilization
`5 metal layers: M1+4X
`
`Nominal Supply Voltage (V)
`0.9V & 1.1V
`
`Junction Temperature (°C)
`−40 to 125 Tj
`
`Leakage Power (μW)
`Deep Sleep Mode 0.5μW
`for EFLX-100 core
`Sleep Mode 1.5μW
`with eHVT Bit Cell
`
` (at 85°C, 0.9V, TT)
`110 – 270 MHz depending on VT/Vdd chosen
`16-bit Counter Frequency (MHz)
`(TT, 85C, 0.9 or 1.1V)
`0.13
`1 to 8
`152 inputs and 152 outputs
` Logic Core
`DSP Core
`
` EFLX100 DSP Core
`
`
`
`
`
`
`IO
`
`RBB Logic
`
`IO
`
`RBB DSP
`
` IO
`
`RBB Logic
`
`Area (mm2)
`Clock Inputs
`Input and Output Pins
`
`Dual 4-input LUTs with 2
`independent outputs
`Total flip flops (ex DSP)
`DSP MACs
`EFLX Array Size
`1×1 to 5x5
`Design-for-Test Support
`Yes
`Utilization
`Typically ~90%
`AXI/JTAG soft IP
`Yes, if requested
`TSMC 40LP Compatibility
`Yes (inquire for 40LP specs)
`The EFLX100 core is available in 4 different VT configurations and 2 nominal voltages: each
`optimized for different performance-to-power requirements for different target applications.
`Specs for EFLX100 based on GDS for TSMC 40ULP:
`Deep
`Sleep
`Mode
`Leakage
`μW
`
`120
`
`544
`0
`
`88
`
`480
`2
`
`16-bit Counter
`MHz
`TT, 85C
`
`Core
`Sleep
`Mode
`Leakage
`μW
`
`
`
`
`IO
`
`Configuration
`Bit Cell and
`Static Logic:
`select a VT
`
`RBB and
`DSP logic:
`select a VT
`
`0.9V
`
`1.1V
`
`TT, 85C, 0.9V
`
`1.5
`0.5
`190
`110
`eHVT
`eHVT
`1.5
`0.5
`270
`180
`SVT
`eHVT
`4.5
`1.5
`190
`110
`HVT
`HVT
`4.5
`1.5
`270
`180
`SVT
`HVT
`Inquire for EFLX100 TSMC 40LP specs: GDS is compatible
`
`May 2018. Copyright 2014-2016 Flex Logix® Technologies, Inc.
`
`

`

`Case 5:18-cv-07581-LHK Document 31-11 Filed 03/04/19 Page 3 of 3
`
`TSMC40 ULP/LP EFLX100 Core
`
`
`Product Brief | May 2018
`
`www.flex-logix.com page 2
`EFLX FPGA Core
`
`the
`three major blocks:
`The EFLX100 Core comprises of
`reconfigurable building blocks (RBBs) of Logic/DSP types, the XFLX
`interconnect network, and the user I/Os. EFLX features full connectivity
`inside the core, and provides ArrayLinx™ interconnects at the boundary
`to concatenate multiple.
`
`User I/Os
`User I/Os
`The EFLX100 user I/O configuration is shown below left. The EFLX100 control pins are show
`below right.
`
`RBB
`
`(cid:29009)
`
`RBB
`
`Interconnects
`
`Expandable Network I/Os
`
`IOB
`
`(cid:29009)
`
`IOB
`
`User Clock
`
`3
`
`6
`
`DFT
`User Clock
`Power Ctrl
`Config.
`
`EFLX-100
`
`User Clock
`
`
`
`Power Ctrl
`3DFT (Aux.)
`5Config. (Aux.)
`
`2
`
`User Clock
`
`DFT 2
`2Config.
`
`Power Ctrl
`
`2
`
`User I/Os: 16 input pins + 16 output pins
`
`~438µm actual
`
`User I/Os:
`60 input pins + 60 output pins
`~298 um actual
`
`=
`
`1 output
`& 1 inputs
`
`EFLX-100
`
`=
`
`1 outputs
`& 1 inputs
`User I/Os:
`60 input pins + 60 output pins
`
`User I/Os: 16 input pins + 16 output pins
`
`Each core has an internal power grid (VDDH and VSS)
`which can be connected to the customer’s digital SoC
`power grid. The core has power control pins for
`power-on and power gating. The core includes
`configuration bits which are configurable via AXI, JTAG
`or our custom serial interface. On each side of the core,
`there are 2 input clocks and 2 output clocks which
`concatenate in EFLX arrays.
`The EFLX core is available now and silicon validation is
`complete.. Contact info@flex-logix.com.
`
`
`Deliverables and EDA Design Views
`Front-end Design view (with NDA)
`Back-end Design Views (with License)
`Encrypted Verilog Netlist with Timing Annotation &
`Encrypted Verilog Netlist
`SDF
`LIB
`GDS-II
`LEF
`CDL/Spice netlist
`Detailed datasheet & DSP User’s Guide
`Integration guidelines & assistance
`Silicon evaluation report
`Test vectors
`EFLX Compiler evaluation version
`EFLX Compiler bitstream generation version
`
`May 2018. Copyright 2014-2018 Flex Logix® Technologies, Inc.
`EFLX®, Flex Logix®, XFLX and ArrayLinx are trademarks of Flex Logix Technologies
`
`