` #:1035
`
`
`
`
`
`
`
`
`EXHIBIT C
`
`
`
`
`
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 2 of 36 Page ID
` #:1036
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 3 of 36 Page ID
` #:1037
`
`This page intentionally left blank
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 4 of 36 Page ID
` #:1038
`
`Multipliers
`Symbol
`T
`G
`M (MEG in SPICE)
`k
`m
`H (or u)
`n
`P
`f
`a (not used in SPICE)
`
`Value
`1012
`109
`106
`103
`io-3
`10 6
`10 9
`1012
`io~15
`10'8
`
`Name
`terra
`giga
`mega
`kilo
`milli
`micro
`nano
`pico
`femto
`atto
`
`Physical Constants
`Value/Units
`Name
`Symbol
`Vacuum dielectric
`8.85 aF/|am
`constant
`Silicon dielectric
`constant
`Si02 dielectric
`constant
`SiN, dielectric
`constant
`Boltzmann's constant
`Electronic charge
`Temperature
`Thermal voltage
`
`£<»
`
`esi
`
`s,„
`
`^Ni
`
`k
`q
`T
`vT
`
`11.7s,,
`
`3.97£0
`
`16e0
`
`1.38 x 10"23J/K
`1.6 x 10'19C
`Kelvin
`kT/q = 26 mV @ 300K
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 5 of 36 Page ID
` #:1039
`
`CMOS
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 6 of 36 Page ID
` #:1040
`
`IEEE Press
`445 Hoes Lane
`Piscataway, NJ 08854
`
`IEEE Press Editorial Board
`Lajos Hanzo, Editor in Chief
`
`R. Abari
`J. Anderson
`F. Canavero
`T. G. Croda
`
`M. El-Hawary
`B. M. Hammerli
`M. Lanzerotti
`O. Malik
`
`S. Nahavandi
`W. Reeve
`T. Samad
`G. Zobrist
`
`Kenneth Moore, Director of IEEE Book and Information Services (BIS)
`
`IEEE Solid-State Circuits Society, Sponsor
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 7 of 36 Page ID
` #:1041
`
`CMOS
`Circuit Design, Layout, and Simulation
`
`Third Edition
`
`R. Jacob Baker
`
`IEEE Press Series on Microelectronic Systems
`Stuart K. Tewksbury and Joe E. Brewer, Series Editors
`
`IEEE PRESS
`
`»WILEY
`
`A JOHN WILEY & SONS, INC., PUBLICATION
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 8 of 36 Page ID
` #:1042
`
`Copyright © 2010 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
`
`Published by John Wiley & Sons, Inc., Hoboken, New Jersey.
`Published simultaneously in Canada.
`
`No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or
`by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as
`permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior
`written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to
`the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax
`(978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should
`be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ
`07030, (201) 748-6011, fax (201) 748-6008, or online at http://www.wiley.com/go/permission.
`
`Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in
`preparing this book, they make no representations or warranties with respect to the accuracy or
`completeness of the contents of this book and specifically disclaim any implied warranties of
`merchantability or fitness for a particular purpose. No warranty may be created or extended by sales
`representatives or written sales materials. The advice and strategies contained herein may not be suitable
`for your situation. You should consult with a professional where appropriate. Neither the publisher nor
`author shall be liable for any loss of profit or any other commercial damages, including but not limited
`to special, incidental, consequential, or other damages.
`
`For general information on our other products and services or for technical support, please contact our
`Customer Care Department within the United States at (800) 762-2974, outside the United States at
`(317) 572-3993 or fax (317) 572-4002.
`
`Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may
`not be available in electronic format. For information about Wiley products, visit our web site at
`www.wiley.com.
`
`Library of Congress Cataloging-in-Publication Data:
`
`Baker, R. Jacob, 1964-
`CMOS : circuit design, layout, and simulation / Jake Baker. — 3rd ed.
`p. cm.
`Summary: "The third edition of CMOS: Circuit Design, Layout, and Simulation continues to cover the
`practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a
`wide range of analog/digital circuit blocks, the BSIM model, data converter architectures, and much
`more. The 3rd edition completes the revised 2nd edition by adding one more chapter (chapter 30) at the
`end, which describes on implementing the data converter topologies discussed in Chapter 29. This addi-
`tional, practical information should make the book even more useful as an academic text and companion
`for the working design engineer. Images, data presented throughout the book were updated, and more
`practical examples, problems are presented in this new edition to enhance the practicality of the book"—
`Provided by publisher.
`Summary: "The third edition of CMOS: Circuit Design, Layout, and Simulation continues to cover the
`practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a
`wide range of analog/digital circuit blocks, the BSIM
`model, data converter architectures, and much more"— Provided by publisher.
`ISBN 978-0-470-88132-3 (hardback)
`1. Metal oxide semiconductors, Complementary—Design and construction. 2. Integrated circuits—
`Design and construction. 3. Metal oxide semiconductor field-effect transistors. I. Title.
`TK7871.99.M44B35 2010
`621.39732—dc22
`
`2010016630
`
`Printed in the United States of America.
`
`10 9 8 7 6 5 4 3 21
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 9 of 36 Page ID
` #:1043
`
`Chapter
`
`2
`
`The Well
`
`To develop a fundamental understanding of CMOS integrated circuit layout and design,
`we begin with a study of the well. The well is the first layer fabricated when making a
`CMOS IC. The approach of studying the details of each fabrication (layout) layer will
`build a solid foundation for understanding the performance limitations and parasitics (the
`pn junctions, capacitances, and resistances inherent in a CMOS circuit) of the CMOS
`process.
`The Substrate (The Unprocessed Wafer)
`CMOS circuits are fabricated on and in a silicon wafer, as discussed in Ch. 1. This wafer
`is doped with donor atoms, such as phosphorus for an n-type wafer, or acceptor atoms,
`such as boron for a p-type wafer. Our discussion centers around a p-type wafer (the most
`common substrate used in CMOS IC processing). When designing CMOS integrated
`circuits with a p-type wafer, n-channel MOSFETs (NMOS for short) are fabricated
`directly in the p-type wafer, while p-channel transistors, PMOS, are fabricated in an
`"n-well." The substrate or well are sometimes referred to as the bulk or body of a
`MOSFET. CMOS processes that fabricate MOSFETs in the bulk are known as "bulk
`CMOS processes." The well and the substrate are illustrated in Fig. 2.1, though not to
`scale.
`
`Often an epitaxial layer is grown on the wafer. In this book we will not make a
`distinction between this layer and the substrate. Some processes use a p-well or both n-
`and p-wells (sometimes called twin tub processes). A process that uses a p-type (n-type)
`substrate with an n-well (p-well) is called an "n-well process" ("p-well process"). We will
`assume, throughout this book, that an n-well process is used for the layout and design
`discussions.
`A Parasitic Diode
`Notice, in Fig. 2.1, that the n-well and the p-substrate form a diode. In CMOS circuits, the
`substrate is usually tied to the lowest voltage in the circuit (generally, the substrate is
`grounded) to keep this diode from forward biasing. Ideally, zero current flows in the
`substrate. We won't concern ourselves with how the substrate is connected to ground at
`this point (see Ch. 4).
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 10 of 36 Page ID
` #:1044
`CMOS Circuit Design, Layout, and Simulation
`32
`
`n-well
`
`Flip chip
`
`>
`on its side
`and enlarge
`
`MOSFETs are not shown.
`
`p-type epi layer (p-)
`
`p-type substrate (p+)
`
`Usually, we
`' will not show
`'the epitaxial
`layer. Many
`processes don't use
`the epi layer.
`
`Figure 2.1 The top (layout) and side (cross-sectional) view of a die.
`
`Using the N-well as a Resistor
`In addition to being used as the body for p-channel transistors, the n-well can be used as a
`resistor, Fig. 2.2. The voltage on either side of the resistor must be large enough to keep
`the substrate/well diode from forward biasing.
`
`Substrate
`connection
`
`Resistor leads
`
`Shows parasitic
`diode
`
`- V W-
`
`n-well
`
`p-substrate
`
`Figure 2.2 The n-well can be used as a resistor.
`
`2.1 Patterning
`CMOS integrated circuits are formed by patterning different layers on and in the silicon
`wafer. Consider the following sequence of events that apply, in a fundamental way, to any
`layer that we need to pattern. We start out with a clean, bare wafer, as shown in Fig. 2.3a.
`The distance given by the line A to B will be used as a reference in Figs. 2.3b—j. Figures
`2.3b—j are cross-sectional views of the dashed line shown in (a). The small box in Fig.
`2.3a is drawn with a layout program (and used for mask generation) to indicate where to
`put the patterned layer.
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 11 of 36 Page ID
` #:1045
`Chapter 2 The Well
`33
`
`Figure 2.3 Generic sequence of events used in photo patterning.
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 12 of 36 Page ID
` #:1046
`CMOS Circuit Design, Layout, and Simulation
`34
`
`The first step in our generic patterning discussion is to grow an oxide, Si02 or
`glass, a very good insulator, on the wafer. Simply exposing the wafer to air yields the
`reaction Si + 02 —> Si02. However, semiconductor processes must have tightly controlled
`conditions to precisely set the thickness and purity of the oxide. We can grow the oxide
`using a reaction with steam, H20, or with 02 alone. The oxide resulting from the reaction
`with steam is called a wet oxide, while the reaction with 02 is a dry oxide. Both oxides
`are called thermal oxides due to the increased temperature used during oxide growth. The
`growth rate increases with temperature. The main benefit of the wet oxide is fast growing
`time. The main drawback of the wet oxide is the hydrogen byproduct. In general terms,
`the oxide grown using the wet techniques is not as pure as the dry oxide. The dry oxide
`generally takes a considerably longer time to grow. Both methods of growing oxide are
`found in CMOS processes. An important observation we should make when looking at
`Fig. 2.3c is that the oxide growth actually consumes silicon. This is illustrated in Fig. 2.4.
`The overall thickness of the oxide is related to thickness of the consumed silicon by
`xSi = 0.45 -xox
`(2.1)
`
`XSi\
`v
`
`A
`
`y
`
`p-substrate
`
`Figure 2.4 How growing oxide consumes silicon.
`
`The next step of the generic CMOS patterning process is to deposit a
`photosensitive resist layer across the wafer (see Fig. 2.3d). Keep in mind that the
`dimensions of the layers, that is, oxide, resist, and the wafer, are not drawn to scale. The
`thickness of a wafer is typically 500 um, while the thickness of a grown oxide or a
`deposited resist may be only a urn (10~6 m) or even less. After the resist is baked, the
`mask derived from the layout program, Figs. 2.3e and f, is used to selectively illuminate
`areas of the wafer, Fig. 2.3g. In practice, a single mask called a reticle, with openings
`several times larger than the final illuminated area on the wafer, is used to project the
`pattern and is stepped across the wafer with a machine called a stepper to generate the
`patterns needed to create multiple copies of a single chip. The light passing through the
`opening in the reticle is photographically reduced to illuminate the correct size area on the
`wafer.
`
`is developed (Fig. 2.3h), removing the areas that were
`The photoresist
`illuminated. This process is called a positive resist process because the area that was
`illuminated was removed. A negative resist process removes the areas of resist that were
`not exposed to the light. Using both types of resist allows the process designer to cut
`down on the number of masks needed to define a CMOS process. Because creating the
`masks is expensive, lowering the number of masks is equated with lowering the cost of a
`process. This is also important in large manufacturing plants where fewer steps equal
`lower cost.
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 13 of 36 Page ID
` #:1047
`Chapter 2 The Well
`35
`
`The next step in the patterning process is to remove the exposed oxide areas (Fig.
`2.3i). Notice that the etchant etches under the resist, causing the opening in the oxide to
`be larger than what was specified by the mask. Some manufacturers intentionally bloat
`(make larger) or shrink (make smaller) the masks as specified by the layout program.
`Figure 2.3j shows the cross-sectional view of the opening after the resist has been
`removed.
`2.1.1 Patterning the N-well
`At this point we can make an n-well by diffusing donor atoms, those with five valence
`electrons, as compared to the 4 four found in silicon, into the wafer. Referring to our
`generic patterning discussion given in Fig. 2.3, we begin by depositing a layer of resist
`directly on the wafer, Fig. 2.3d (without oxide). This is followed by exposing the resist to
`light through a mask (Figs. 2.3f and g) and developing or removing the resist (Fig. 2.3h).
`The mask used is generated with a layout program. The next step in fabricating the n-well
`is to expose the wafer to donor atoms. The resist blocks the diffusion of the atoms, while
`the openings allow the donor atoms to penetrate into the wafer. This is shown in Fig.
`2.5a. After a certain amount of time, depending on the depth of the n-well desired, the
`diffusion source is removed (Fig. 2.5b). Notice that the n-well "outdiffuses" under the
`resist; that is, the final n-well size is not the same as the mask size. Again, the foundry
`where the chips are fabricated may bloat or shrink the mask to compensate for this lateral
`diffusion. The final step in making the n-well is the removal of the resist (Fig. 2.5c).
`
`Figure 2.5 Formation of the n-well.
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 14 of 36 Page ID
` #:1048
`36
`CMOS Circuit Design, Layout, and Simulation
`
`2.2 Laying Out the N-well
`When we lay out the n-well, we are viewing the chip from the top. One of the key points
`in this discussion, as well as the discussions to follow, is that we do layout to a generic
`scale factor. If, for example, the minimum device dimensions are 50 nm (= 0.05 urn =
`50 x 10_9m), then an n-well box drawn 10 by 10, see Fig. 2.6, has an actual size after it
`is fabricated of 10- 50 nm or half a micron (0.5 um = 500 nm), neglecting lateral
`diffusion or other process imperfections. We scale the layout when we generate the GDS
`(calma stream format) or CIF (Caltech-intermediate-format) file from a layout program.
`(A GDS or CIF file is what the mask maker uses to make reticles.) Using integers to do
`layout simplifies things. We'll see in a moment that many electrical parameters are ratios
`(such as resistance) and so the scale factor cancels out of the ratio.
`
`Cross section
`shown below
`
`n-well
`
`p-substrate
`
`Figure 2.6 Layout and cross-sectional view of a 10 by 10 (drawn) n-well.
`
`2.2.1 Design Rules for the N-well
`Now that we've laid out the n-well (drawn a box in a layout program), we might ask the
`question, "Are there any limitations or constraints on the size and spacing of the
`n-wells?" That is to say, "Can we make the n-well 2 by 2?" Can we make the distance
`between the n-wells 1? As we might expect, there are minimum spacing and size
`requirements for all layers in a CMOS process. Process engineers, who design the
`integrated circuit process, specify the design rules. The design rules vary from one
`process technology (say a process with a scale factor of 1 urn) to another (say a process
`with a scale factor of 50 nm).
`Figure 2.7 shows sample design rules for the n-well. The minimum size (width or
`length) of any n-well is 6, while the minimum spacing between different n-wells is 9. As
`the layout becomes complicated, the need for a program that ensures that the design rules
`are not violated is needed. This program is called a design rule checker program (DRC
`program). Note that the minimum size may be set by the quality of patterning the resist
`(as seen in Fig. 2.5), while the spacing is set by the parasitic npn transistor seen in Fig.
`2.7. (We don't want the n-wells interacting to prevent the parasitic npn from turning on.)
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 15 of 36 Page ID
` #:1049
`Chapter 2 The Well
`37
`
`Width
`Width
`5.
`?_ Spacing 5.
`*
`K
`>!
`
`Cross section
`shown below
`
`*
`
`Design rules: width of
`the n-well must be at
`least 6 while spacing
`should be at least 9.
`
`n-well
`
`n-well
`SL T
`Parasitic npn bipolar transistor
`
`p-substrate
`
`Figure 2.7 Sample design rules for the n-well.
`
`2.3 Resistance Calculation
`In addition to serving as a region in which to build PMOS transistors (called the body or
`bulk of the PMOS devices), n-wells are often used to create resistors. The resistance of a
`material is a function of the material's resistivity, p, and the material's dimensions. For
`example, the slab of material in Fig. 2.8 between the two leads has a resistance given by
`D = £ L ■ scale _ P L_
`t'W-scale
`t'w
`In semiconductor processing, all of the fabricated thicknesses, /, seen in a cross-
`sectional view, such as the n-well's, are fixed in depth (this is important). When doing
`layout, we only have control over W (width) and L (length) of the material. The W and L
`are what we see from the top view, that is, the layout view. We can rewrite Eq. (2.2) as
`
`(2.2)
`
`^ — ^square
`
`'
`
`,"
`
`^ ^square
`
`"
`
`(2.3)
`
`ls me sheet resistance of the material in Q/square (noting that when L = W the
`^square
`layout is square and R = R
`).
`
`Layout view
`
`W
`
`-B
`
`Figure 2.8 Calculation of the resistance of a rectangular block of material.
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 16 of 36 Page ID
` #:1050
`CMOS Circuit Design, Layout, and Simulation
`38
`
`Example 2.1
`Calculate the resistance of an n-well that is 10 wide and 100 long. Assume that the
`n-well's sheet resistance is typically 2 kQ/square; however, it can vary with
`process shifts from 1.6 to 2.4 kfl/square.
`The typical resistance, using Eq. (2.3), between the ends of the n-well is
`
`R
`
`2,000 ^j°- = 20 Kl
`
`The maximum value of the resistor is 24k, while the minimum value is 16k. ■
`Layout of Corners
`Often, to minimize space, resistors are laid out in a serpentine pattern. The comers, that
`is, where the layer bends, are not rectangular. This is shown in Fig. 2.9a. All sections in
`Fig 2.9a are square, so the resistance of sections 1 and 3 is Rsquare. The equivalent
`resistance of section 2 between the adjacent sides, however, is approximately 0.6 R uare.
`The overall resistance between points A and B is therefore 2.6 -Rs
`. As seen in Ex. 2.1
`the actual resistance value varies with process shifts. The layout shown in Fig. 2.9b uses
`wires to connect separate sections of unit resistors to avoid comers. Avoiding comers in a
`resistor is the (generally) preferred method of layout in analog circuit design where the
`ratio of two resistors is important. For example, the gain of an op-amp circuit may be
`RJRr
`
`Layout (top view)
`
`.£
`
`(a)
`
`(b)
`
`Figure 2.9 (a) Calculating the resistance of a corner section and (b) layout to avoid corners.
`
`2.3.1 The N-well Resistor
`At this point, it is appropriate to show the actual cross-sectional view of the n-well after
`all processing steps are completed (Fig. 2.10). The n+ and p+ implants are used to
`increase the threshold voltage of the field devices; more will be said on this in Ch. 7. In
`all practical situations, the sheet resistance of the n-well is measured with the field
`implant in place, that is, with the n+ implant between the two metal connections in Fig.
`2.10. Not shown in Fig. 2.10 is the connection to substrate. The field oxide (FOX; also
`known as ROX or recessed oxide) are discussed in Chs. 4 and 7 when we discuss the
`active and poly layers. The reader shouldn't, at this point, feel they should understand any
`of the cross-sectional layers in Fig. 2.10 except the n-well. Note that the field implants
`aren 't drawn in the layout and so their existence is transparent to the designer.
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 17 of 36 Page ID
` #:1051
`Chapter 2 The Well
`39
`
`Figure 2.10 Cross-sectional view of n-well showing field implant. The field
`implantation is sometimes called the "channel stop implant."
`
`2.4 The N-well/Substrate Diode
`As seen in Fig. 2.1, placing an n-well in the p-substrate forms a diode. It is important to
`understand how to model a diode for hand calculations and in SPICE simulations. In
`particular, let's discuss general diodes using the n-well/substrate pn junction as an
`example. The DC characteristics of the diode are given by the Shockley diode equation,
`or
`
`ID = ls(e%
`
`- i)
`
`(2.4)
`
`The current ID is the diode current; Is is the scale (saturation) current; Vd is the voltage
`across the diode where the anode, A, (p-type material) is assumed positive with respect to
`the cathode, K, (n-type); and VT is the thermal voltage, which is given by y where k =
`Boltzmann's constant (1.3806 x 10"23 Joules per degree Kelvin), T is temperature in
`Kelvin, n is the emission coefficient (a term that is related to the doping profile and
`affects both the exponential behavior of the diode and the diode's turn-on voltage), and q
`is the electron charge of 1.6022 x 10~19 coulombs. The scale current and thus the overall
`diode current are related in SPICE by an area factor (not associated with or to be confused
`with the scale term we use in layouts, Eq. (2.2)). The SPICE (Simulation Program with
`Integrated Circuit Emphasis) circuit simulation program assumes that the value of Is
`supplied in the model statement was measured for a device with a reference area of 1. If
`an area factor of 2 is supplied for a diode, then Is is doubled in Eq. (2.4).
`2.4.1 A Brief Introduction to PN Junction Physics
`A conducting material is made up of atoms that have easily shared orbiting electrons. As
`a simple example, copper is a better conductor than aluminum because the copper atom's
`electrons aren't as tightly coupled to its nucleus allowing its electrons to move around
`more easily. An insulator has, for example, eight valence electrons tightly coupled to the
`atom's nucleus. A significant electric field is required to break these electrons away from
`their nucleus (and thus for current conduction). A semiconductor, like silicon, has four
`valence electrons. Silicon's conductivity falls between an insulator and a conductor (and
`thus the name "semiconductor"). As silicon atoms are brought together, they form both a
`periodic crystal structure and bands of energy that restrict the allowable energies an
`electron can occupy. At absolute zero temperature, (T=0 K), all of the valence electrons
`in the semiconductor crystal reside in the valence energy band, Ev. As temperature
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 18 of 36 Page ID
` #:1052
`CMOS Circuit Design, Layout, and Simulation
`40
`
`increases, the electrons gain energy (heat is absorbed by the silicon crystal), which causes
`some of the valence electrons to break free and move to a conducting energy level, Ec.
`Figure 2.11 shows the movement of an electron from the valence band to the conduction
`band. Note that there aren't any allowable energies between Ev and Ec in the silicon
`crystal structure (if the atom were by itself, that is, not in a crystal structure this exact
`limitation isn't present). Further note that when the electron moves from the valence
`energy band to the conduction energy band, a hole is left in the valence band. Having an
`electron in the conduction band increases the material's conductivity (the electron can
`move around easily in the semiconductor material because it's not tightly coupled to an
`atom's nucleus). At the same time a hole in the valence band increases the material's
`conductivity (electrons in the valence band can move around more easily by simply
`falling into the open hole). The key point is that increasing the number of electrons or
`holes increases the materials conductivity. Since the hole is more tightly coupled to the
`atom's nucleus (actually the electrons in the valence band), its mobility (ability to move
`around) is lower than the electron's mobility in the conduction band. This point is
`fundamentally important. The fact that the mobility of a hole is lower than the mobility
`of an electron (in silicon) results in, among other things, the size of PMOS devices being
`larger than the size of NMOS devices (when designing circuits) in order for each device
`to have the same drive strength.
`
`. electron
`
`^
`
`hole
`Figure 2.11 An electron moving to the conduction band, leaving
`behind a hole in the valence band.
`
`F..
`
`Carrier Concentrations
`Pure silicon is often called intrinsic silicon. As the temperature of the silicon crystal is
`increased it absorbs heat. Some of the electrons in the valence band gain enough energy
`to jump the bandgap energy of silicon, Eg (see also Eq. (23.21)), as seen in Fig. 2.11. This
`movement of an electron from the valence band to the conduction band is called
`generation. When the electron loses energy and falls back into the valence band, it is
`called recombination. The time the electron spends in the conduction band, before it
`recombines (drops back to the valence energy band), is random and often characterized by
`the carrier lifetime, Tr(a root-mean-square, RMS, value of the random times the electrons
`spend in the conduction band of the silicon crystal). While discussing the actual processes
`involved with generation-recombination (GR) is outside the scope of this book, the
`carrier lifetime is a practical important parameter for circuit design. Another important
`parameter is the number of electrons in the conduction band (and thus the number of
`holes in the valence band) at a given time (again a random number). These carriers are
`called intrinsic carriers, nt. At room temperature
`«, « 14.5 x 109 carriers/cm2
`
`(2.5)
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 19 of 36 Page ID
` #:1053
`Chapter 2 The Well
`41
`
`noting that cm3 indicates a volume. If we call the number of free electrons (meaning
`electrons excited up in the conduction band of silicon) n and the number of holes p, then
`for intrinsic silicon,
`
`n =p = n-, » 14.5 x 109 carriers/cm3
`(2.6)
`This may seem like a lot of carriers. However, the number of silicon atoms, NSi , in a
`given volume of crystalline silicon is
`NSi = 50 x 1021 atoms/cm*
`(2.7)
`so there is only one excited electron/hole pair for (roughly) every 1012 silicon atoms.
`Next let's add different materials to intrinsic silicon (called doping the silicon) to
`change silicon's electrical properties. If we add a small amount of a material containing
`atoms with five valence electrons like phosphorous (silicon has four), then the added
`atom would bond with the silicon atoms and the donated electron would be free to move
`around (and easily excited to the conduction band). If we call the density of this added
`donor material ND with units of atoms/cm3 and we assume the number of atoms added to
`the silicon is much larger than the intrinsic carrier concentration, then we can write the
`number of free electrons (the electron concentration ri) in the material as
`n « ND when NSi » ND » nt
`(2.8)
`A material with added donor atoms is said to be an "n-type" material. Similarly, if we
`were to add a small material to silicon with atoms having three valence electrons (like
`boron), the added material would bond with the silicon resulting in a hole in the valence
`band. Again, this increases the conductivity of silicon because, now, the electrons in the
`valence band can move into the hole (having the effect of making it look like the hole is
`moving). The added material in this situation is said to be an acceptor material. The
`added material accepts an electron from the silicon crystal. If the density of the added
`acceptor material is labeledNA , then the hole concentration,/?, in the material is
`p*NA when Nsi » NA » w,
`(2.9)
`A material with added acceptor atoms is said to be a "p-type" material.
`If we dope a material with donor atoms, the number of free electrons in the
`material, n , goes up, as indicated by Eq. (2.8). We would expect, then, the number of free
`holes in the material to go down (some of those free electrons fall easily into the available
`holes reducing the number of holes in the material). The relationship between the number
`of holes, electrons, and intrinsic carrier concentration, is governed by the mass-action law
`pn = n]
`(2.10)
`
`Consider the following example.
`
`Example 2.2
`Suppose silicon is doped with phosphorous having a density, ND , of 1018
`atoms/cm3. Estimate the doped silicon's hole and electron concentration.
`The electron concentration, from Eq. (2.8) is, n= 1018 electrons/cm3 (one electron
`for each donor atom). The hole concentration is found using the mass-action law
`as
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 20 of 36 Page ID
` #:1054
`CMOS Circuit Design, Layout, and Simulation
`42
`
`210 holes/cm3
`
`(14.5 xlQ9)2
`P = -
`1018
`Basically, all of the holes are filled. Note that with a doping density of 1018 there
`is one dopant atom for every 50,000 silicon atoms. If we continue to increase the
`doping concentration, our assumption that NSj» ND isn't valid and the material is
`said to be degenerate (no longer mainly silicon). A degenerate semiconductor
`doesn't follow the mass-action law (or any of the equations for silicon we
`present). ■
`Fermi Energy Level
`To describe the carrier concentration in a semiconductor, the Fermi energy level is often
`used. The Fermi energy level is useful when determining the contact potentials in
`materials. For example, the potential that you have to apply across a diode before it turns
`on is set by the p-type and n-type material contact potential difference. Also, the threshold
`voltage is determined, in part, by contact potentials.
`The Fermi energy level simply indicates the energy level where the probability of
`occupation by a free electron is 50%. Figure 2.12a shows that for intrinsic silicon the
`(intrinsic) Fermi level, Ei is close to the middle of the bandgap. In p-type silicon, the
`Fermi level, Ef, moves towards the valence band, Fig. 2.12b, since the number of free
`electrons, n , is reduced with the abundance of holes. Figure 2.12c shows the location of
`the Fermi energy level in n-type silicon. The Fermi level moves towards Ec with the
`abundance of electrons in the conduction band.
`
`■Ee
`
`■Ei
`
`■Ee
`
`■Ei
`
`■Ev
`(a) Intrinsic silicon
`
`Efp
`Ev
`(b) p-type silicon
`
`(c) n-type silicon
`
`Ec ~Ef„
`Ei
`
`Ev
`
`q-Vu
`
`n-type
`
`p-type
`
`(d) A pn-junction diode
`
`Figure 2.12 The Fermi energy levels in various structures.
`
`
`
`Case 2:17-cv-04273-JVS-JEM Document 76-3 Filed 06/12/18 Page 21 of 36 Page ID
` #:1055
`Chapter 2 The Well
`43
`
`The energy difference between the Ei and E, is given, for a p-type semiconductor,
`
`by
`
`and for an n-type semiconductor by
`
`Ei - Efp = kT ■ In NA
`
`Ef„ - Ei = kT-\n ND_
`
`(2.11)
`
`(2.12)
`
`The band diagram of a pn junction (a diode) is seen in Fig. 2.12d. Note how the Fermi
`energy level is constant throughout the diode. A variation in E, would indicate a
`nonequilibrium situation (the diode has an external voltage applied across it). To get
`current to flow in a diode, we must apply an external potential that approaches the diode's
`contact potential (its built-in potential, Vbl). By applying a potential to forward bia