Trials@uspto.gov
`571-272-7822
`
`
`Paper No. 10
`Entered: February 6, 2018
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Cases IPR2017-01843 and IPR2017-01844
`Patent 7,893,501 B2
`____________
`
`
`Before JUSTIN T. ARBES, MICHAEL J. FITZPATRICK, and
`JENNIFER MEYER CHAGNON, Administrative Patent Judges.
`
`CHAGNON, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`

`

`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
`
`
`I.
`
`Case Number
`
`IPR2017-01843
`
`Petition
`
`Paper 2
`(“Pet.”)
`
`INTRODUCTION
`Taiwan Semiconductor Manufacturing Company, Ltd. (“Petitioner”)
`filed two Petitions for inter partes review of, collectively, claims 1, 4–7,
`9–13, 15–19, 21, and 23–25 (“the challenged claims”) of U.S. Patent
`No. 7,893,501 B2 (Ex. 1201,1 “the ’501 patent”). Petitioner relies on the
`Declarations of Stanley R. Shanfield, Ph.D. (Ex. 1202; -1844 Ex. 1302) to
`support its positions. Godo Kaisha IP Bridge 1 (“Patent Owner”) filed a
`Preliminary Response in each proceeding, as listed in the following chart.
`Challenged
`Preliminary
`Claims
`Response
`1, 4, 5, 7, 9–11,
`Paper 6
`15–18, 23–25
`(“Prelim. Resp.”)
`Paper 7
`(“-1844 Prelim.
`Resp.”)
`
`IPR2017-01844
`
`6, 12, 13, 19, 21 Paper 2
`(“-1844 Pet.”)
`
`We have authority to determine whether to institute inter partes
`review. See 35 U.S.C. § 314(b); 37 C.F.R. § 42.4(a). Upon consideration of
`the Petitions and the Preliminary Responses, and for the reasons explained
`below, we determine that the information presented shows a reasonable
`likelihood that Petitioner would prevail with respect to all of the challenged
`claims. See 35 U.S.C. § 314(a). Accordingly, we institute trial as to the
`challenged claims, based on the grounds set forth in the Petitions. We also
`
`
`1 Unless otherwise specified with the “-1844” prefix, references to exhibits
`and papers herein are to those filed in Case IPR2017-01843.
`
`
`
`2
`
`

`

`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
`
`exercise our authority under 35 U.S.C. § 315(d) to consolidate the two
`proceedings and conduct the proceedings as one trial.2
`The following findings of fact and conclusions of law are not final,
`but are made for the sole purpose of determining whether Petitioner meets
`the threshold for initiating review. Any final decision shall be based on the
`full trial record, including any response timely filed by Patent Owner. Any
`arguments not raised by Patent Owner in a timely-filed response shall be
`deemed waived, even if they were presented in the Preliminary Response.
`
`A. Related Proceedings
`The parties indicate that the ’501 patent is the subject of the following
`ongoing district court proceeding: Godo Kaisha IP Bridge 1 v. Xilinx, Inc.,
`No. 2-17-cv-00100 (E.D. Tex.). Pet. 2; Paper 4, 1. Petitioner has filed two
`additional petitions challenging claims of the ’501 patent—IPR2017-01841
`and IPR2017-01842. Pet. 2; Paper 4, 1.
`
`B. The ’501 Patent
`The ’501 patent relates to a semiconductor device including a
`MISFET (metal-insulator-semiconductor field-effect transistor3) and a
`method of manufacturing the same. Ex. 1201, 1:16–19. In particular,
`the ’501 patent teaches “a first-type internal stress film formed of a silicon
`oxide film over source/drain regions of an nMISFET and a second-type
`
`
`2 As indicated in the Order, all further filings in the consolidated proceeding
`shall be made in Case IPR2017-01843. For clarity in future filings, the
`parties are instructed to cite to papers and exhibits filed only in
`Case IPR2017-01844 using the same -1844 prefix style used herein.
`3 Ex. 1202 ¶ 38.
`
`
`
`3
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`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
`
`internal stress film formed of a TEOS [(tetraethylorthosilicate4)] film over
`source/drain regions of a pMISFET.” Id. at [57]. According to the ’501
`patent, these internal stress films generate tensile or compressive stresses
`that, respectively, allow the mobility of electrons or holes to increase.5 Id.
`Figure 1 of the ’501 patent is reproduced below.
`
`
`Figure 1, above, is a cross-sectional view of a semiconductor device of an
`embodiment of the ’501 patent. Id. at 2:47–49. The semiconductor device
`of Figure 1 includes semiconductor substrate 1, which is divided into active
`regions 1a and 1b by isolation region 2; channel regions 1x, 1y; nMISFET
`formation region Rn and pMISFET formation region Rp; source regions 3a,
`3b and drain regions 4a, 4b; gate insulating film 5; gate electrodes 6a, 6b;
`sidewalls 7; first-type internal stress film 8a (e.g., silicon nitride film);
`
`
`4 See Ex. 1204 (U.S. Patent No. 5,960,270), 5:40; Ex. 1218 (U.S. Patent
`No. 6,509,234 B1), 6:67.
`5 We note that the challenged claims do not recite these stress limitations,
`which are present only in dependent claims 2, 3, and 20. See Pet. 9 n.2.
`
`
`
`4
`
`

`

`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
`
`second-type internal stress film 8b (e.g., TEOS film); interlevel insulating
`film 9; lead electrode 10; and contact 11. Id. at 3:19–64.
`
`C. Illustrative Claim
`Of the challenged claims, claim 1 is independent and claims 4–7,
`9–13, 15–19, 21, and 23–25 depend, directly or indirectly, therefrom.
`Independent claim 1 of the ’501 patent is reproduced below, and is
`illustrative of the challenged claims.
`1. A semiconductor device, comprising a MISFET,
`wherein
`the MISFIT includes:
`an active region made of a semiconductor substrate;
`a gate insulating film formed on the active region;
`a gate electrode formed on the gate insulating film;
`source/drain regions formed in regions of the active
`region located on both sides of the gate electrode; and
`a silicon nitride film formed over from side surfaces of
`the gate electrode to upper surfaces of the source/drain regions,
`wherein:
`the silicon nitride film is not formed on an upper surface
`of the gate electrode, and
`the gate electrode protrudes upward from a surface level
`of parts of the silicon nitride film located at both side surfaces
`of the gate electrode.
`Ex. 1201, 15:42–57.
`
`D. The Applied References
`Petitioner relies on the following references in the asserted grounds.
`Pet. 4; -01844 Pet. 4.
`
`
`
`
`5
`
`

`

`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
`
`Reference
`U.S. Patent No. 5,960,270
`(“Misra”)6
`U.S. Patent No. 6,444,566 B1
`(“Tsai”)7
`U.S. Patent No. 5,472,890
`(“Oda”)8
`U.S. Appl. Pub. 2002/0000611 A1
`(“Hokazono”)9
`
`Date
`
`Sept. 28, 1999
`
`Sept. 3, 2002
`
`Exhibit
`Ex. 1204
`-1844 Ex. 1304
`Ex. 1215
`-1844 Ex. 1315
`
`Dec. 5, 1995
`
`-1844 Ex. 1305
`
`Jan. 3, 2002
`
`-1844 Ex. 1306
`
`E. The Asserted Grounds
`Petitioner sets forth its challenges to claims 1, 4–7, 9–13, 15–19, 21,
`and 23–25 as follows. Pet. 18–72; -1844 Pet. 18–61.
`References
`Basis
`Claims Challenged
`1, 4, 5, 7, 9–11, 15–19,
`Misra and Tsai
`§ 103
`23–25
`Misra, Tsai, and Oda
`§ 103
`6, 21
`Misra, Tsai, and Hokazono
`§ 103
`12, 13
`
`II. ANALYSIS
`A. Claim Construction
`In an inter partes review, claim terms in an unexpired patent are given
`their broadest reasonable construction in light of the specification of the
`
`
`6 Petitioner asserts Misra is prior art under 35 U.S.C. §§ 102(a), 102(b), and
`102(e). Pet. 4; -1844 Pet. 4.
`7 Petitioner asserts Tsai is prior art under 35 U.S.C. §§ 102(a), 102(b), and
`102(e). Pet. 4; -1844 Pet. 4.
`8 Petitioner asserts Oda is prior art under 35 U.S.C. §§ 102(a), 102(b),
`and 102(e). -1844 Pet. 4.
`9 Petitioner asserts Hokazono is prior art under 35 U.S.C. §§ 102(a), 102(b),
`and 102(e). -1844 Pet. 4.
`
`
`
`6
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`

`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
`
`patent in which they appear. See 37 C.F.R. § 42.100(b); Cuozzo Speed
`Techs. LLC v. Lee, 136 S. Ct. 2131, 2144–46 (2016) (upholding the use of
`the broadest reasonable interpretation standard). Under the broadest
`reasonable construction standard, claim terms generally are given their
`ordinary and customary meaning, as would be understood by one of ordinary
`skill in the art in the context of the entire disclosure. See In re Translogic
`Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). The claims, however,
`“should always be read in light of the specification and teachings in the
`underlying patent,” and “[e]ven under the broadest reasonable interpretation,
`the Board’s construction ‘cannot be divorced from the specification and the
`record evidence.’” Microsoft Corp. v. Proxyconn, Inc., 789 F.3d 1292, 1298
`(Fed. Cir. 2015) (citations omitted). Further, any special definition for a
`claim term must be set forth in the specification with reasonable clarity,
`deliberateness, and precision. See In re Paulsen, 30 F.3d 1475, 1480 (Fed.
`Cir. 1994). In the absence of such a definition, however, limitations are not
`to be read from the specification into the claims. In re Van Geuns, 988 F.2d
`1181, 1184 (Fed. Cir. 1993).
`Petitioner asserts that all terms in the challenged claims should be
`given their plain meaning under the broadest reasonable interpretation
`standard. Pet. 17.10
`
`
`10 Petitioner makes a similar statement regarding claim construction in
`the -1844 Petition. -1844 Pet. 17. Likewise, Patent Owner’s arguments with
`respect to claim construction are nearly identical in both Preliminary
`Responses. Compare Prelim. Resp. 40–58, with -1844 Prelim. Resp. 41–60.
`For convenience, we cite only to the Petition and the Preliminary Response
`from IPR2017-01843 in our discussion regarding claim construction.
`
`
`
`7
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`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
`
`
`Patent Owner argues that Petitioner implicitly construes “silicon
`nitride film” more broadly than is reasonable. Prelim. Resp. 40–58.
`Specifically, Patent Owner argues that Petitioner’s implicit construction of
`“silicon nitride film” is inconsistent with the Specification of the ’501
`patent. Id. at 42. Patent Owner asserts that the claimed silicon nitride film
`is not limited to a single layer. Id. at 44. Patent Owner points to the
`Specification of the ’501 patent, which explains that “each of the [silicon
`nitride] stress films 8a and 8b does not have to be a single layer but may
`include multiple layers.” Ex. 1201, 5:60–63; see id. at 3:53–55; Prelim.
`Resp. 44. According to Patent Owner, “Petitioner’s assertion that the
`claimed silicon nitride film must be construed narrowly to read on a single
`‘layer’ of silicon nitride, or to exclude a silicon nitride film formed in two
`‘structures’ using ‘different process steps’” contradicts this clear disclosure
`in the Specification. Prelim. Resp. 45 (citing Pet. 42).
`Patent Owner, however, mischaracterizes Petitioner’s argument.
`Nowhere does Petitioner argue that the claims exclude a silicon nitride film
`having multiple layers. Petitioner simply argues that a silicon nitride film
`need not include every silicon nitride structure in a prior art device. See
`Pet. 42–43. As discussed in more detail below (Section II.E), Petitioner
`relies on Misra’s plasma-enhanced nitride layer 20 (in combination with
`Tsai) as teaching the claimed “silicon nitride film” and relies on Misra’s
`spacers 23 (that Patent Owner alleges must be considered part of the silicon
`nitride film) as teaching the claimed “sidewall formed on the side surface of
`the gate electrode” (claim 7). See Pet. 29, 51–52. Although we agree with
`Patent Owner that the Specification discloses that the claimed silicon nitride
`film may include multiple layers, we disagree that the claim requires that the
`
`
`
`8
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`

`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
`
`silicon nitride film must encompass all silicon nitride structures in a prior art
`device. See Prelim. Resp. 45.
`Patent Owner also argues that Petitioner’s implicit construction of
`“parts of the silicon nitride film located at both side surfaces of the gate
`electrode” is unreasonably broad, asserting that the claim requires the
`electrode to “protrude[] upward” from a surface level of “parts of the silicon
`nitride film located closest to both side surfaces of the gate electrode.” See
`Prelim. Resp. 47–56. In light of our construction of “silicon nitride film,”
`we need not address Patent Owner’s arguments on this point because
`Petitioner’s mapping of the cited references to the “protrudes upward”
`limitation would meet Patent Owner’s proposed construction. The parties,
`however, may further address construction of the term during trial.
`
`B. Principles of Law
`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the subject matter sought to be patented and the prior art are such
`that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of ordinary skill in the art; and (4) objective evidence of
`nonobviousness.11 Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`
`
`11 At this stage of the proceeding, the parties have not directed our attention
`to any objective evidence of non-obviousness.
`
`
`
`9
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`

`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
`
`
`In that regard, an obviousness analysis “need not seek out precise
`teachings directed to the specific subject matter of the challenged claim, for
`a court can take account of the inferences and creative steps that a person of
`ordinary skill in the art would employ.” KSR, 550 U.S. at 418; accord In re
`Translogic Tech., 504 F.3d at 1259.
`We analyze the asserted grounds of unpatentability in accordance with
`these principles to determine whether Petitioner has met its burden to
`establish a reasonable likelihood of success at trial.
`
`C. Level of Ordinary Skill in the Art
`Petitioner asserts that a person of ordinary skill in the art “would have
`had the equivalent of a Master’s degree in electrical engineering, physics,
`chemistry, materials science, or equivalent training, and two years of work
`experience in [the] field of semiconductor manufacturing. Additional
`graduate education could substitute for work experience, and additional
`work experience/training could substitute for formal education.” Pet. 4–5
`(citing Ex. 1202 ¶¶ 34–36); -1844 Pet. 5 (citing Ex. 1302 ¶¶ 34–36). Patent
`Owner does not dispute Petitioner’s proposed level of ordinary skill in the
`art for purposes of its Preliminary Response. See Prelim. Resp. 39–
`40; -1844 Prelim. Resp. 40. For purposes of this Decision, we adopt
`Petitioner’s proposal regarding the level of ordinary skill in the art.
`The level of ordinary skill in the art in this case further is reflected by the
`prior art of record. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed.
`Cir. 2001); In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995); In re
`Oelrich, 579 F.2d 86, 91 (CCPA 1978).
`
`
`
`10
`
`

`

`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
`
`
`D. The Asserted Prior Art
`
`Misra (Ex. 1204)
`Misra relates to a “method for forming a metal gate MOS transistor.”
`Ex. 1204, at [57]. Figure 7 of Misra is reproduced below.
`
`
`Figure 7, above, shows a cross-sectional view of a semiconductor device
`according to an embodiment of Misra. Id. at 2:15–17. Semiconductor
`device 10 of Figure 7 includes semiconductor substrate 12, isolation
`trenches 14, well region 16, silicide layer 18, plasma-enhanced nitride
`layer 20, oxide layer 22, spacer 23, source and drain electrodes 26 and 28,
`thermal gate oxide 27, sacrificial oxide 25, and electrode 28b. Id. at 4:21–
`7:28 (describing the “metal gate MOS process used for forming a
`semiconductor device 10” with respect to Figures 1–7, resulting in the
`structure shown in Figure 7).
`
`Tsai (Ex. 1215)
`Tsai relates to “silicon integrated circuits with particular reference to
`interconnection technology.” Ex. 1215, 1:5–7. Tsai teaches buffer
`insulation layer 21 and silicon nitride layer 28 (which acts as an etch stop
`layer) being formed over a field effect transistor that includes source and
`
`
`
`11
`
`

`

`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
`
`drain regions 14 and 15, gate insulation layer 16, and gate pedestal 17. Id. at
`2:19–31, 2:49–50, Fig. 2.
`
`Oda (-1844 Ex. 1305)
`Oda relates to a method for forming a MOS transistor. -1844
`Ex. 1305, 1:8–10. In relevant part, Oda discloses a transistor including
`source and drain regions including both lightly doped layers 105a, 105b and
`highly-doped N+-type layers 107a, 107b. Id. at 3:45–50, 4:3–13.
`
`Hokazono (-1844 Ex. 1306)
`Hokazono relates to a semiconductor device with a gate electrode
`having a sidewall insulating film. -1844 Ex. 1306, at [57]. In relevant part,
`Hokazono discloses that “gate insulating film 4 [of gate electrode 5] may be
`not only a silicon oxide film but also SiON, SiN, or Ta2O5, high dielectric
`material.” Id. ¶ 59.
`
`E. Petitioner’s Asserted Grounds
`Petitioner asserts that claims 1, 4, 5, 7, 9–11, 15–19, 23–25 are
`unpatentable under 35 U.S.C. § 103 as obvious in view of Misra and Tsai.
`Pet. 18–72; -1844 Pet. 18–44. Petitioner further asserts that claims 6 and 21
`are unpatentable under 35 U.S.C. § 103(a) as obvious in view of Misra, Tsai,
`and Oda (-1844 Pet. 45–54) and that claims 12 and 13 are unpatentable
`under 35 U.S.C. § 103(a) as obvious in view of Misra, Tsai, and Hokazono
`(id. at 54–61). Patent Owner argues that Petitioner’s proposed combination
`does not teach all features of independent claim 1. Prelim. Resp. 10–20,
`58–76; -1844 Prelim. Resp. 11–21, 60–79.
`
`
`
`12
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`

`

`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
`
`
`We have reviewed the parties’ contentions and supporting evidence.
`Given the evidence on this record, and for the reasons explained below, we
`determine that the information presented shows a reasonable likelihood that
`Petitioner would prevail on these asserted grounds.
`
`Independent Claim 1
`
`Petitioner’s Contentions
`Petitioner provides an annotated version of Figure 7 of Misra, which
`illustrates the mapping of the structural elements of the semiconductor
`device of Misra to the claims. Pet. 9–10 (citing Ex. 1202 ¶ 51).12
`Petitioner’s annotated Figure 7 (id. at 10) is reproduced below.
`
`
`
`
`12 Petitioner makes similar arguments regarding independent claim 1 in
`the -1844 Petition. Compare Pet. 18–44, with -1844 Pet. 18–44. Likewise,
`Patent Owner’s arguments with respect to independent claim 1 are nearly
`identical in both Preliminary Responses. Compare Prelim. Resp. 10–20, 58–
`76, with -1844 Prelim. Resp. 11–21, 60–79. For convenience, we cite only
`to the Petition and the Preliminary Response from IPR2017-01843 in our
`analysis of claim 1.
`
`
`
`13
`
`

`

`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
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`Figure 7, above, shows a cross-sectional view of a semiconductor device13
`according to an embodiment of Misra, as annotated by Petitioner. Ex. 1204,
`2:15–17. Petitioner relies on Misra’s semiconductor substrate 12, thermal
`gate oxide 27 (red), gate electrode 28b (orange), source and drain electrodes
`26, 28 and silicide regions 18 formed thereon (green), and plasma-enhanced
`nitride layer 20 (blue), respectively, as teaching the claimed semiconductor
`substrate, gate insulating film, gate electrode, source/drain regions, and
`silicon nitride film. Pet. 9–10, 18–30, 37–42; Ex. 1202 ¶¶ 51, 67–72, 76–90.
`Claim 1 further recites “an active region made of a semiconductor
`substrate.” Petitioner points to disclosure in Misra that “isolation
`trenches 14 are filled with a dielectric material in order to provide field
`isolation between active areas of the semiconductor device 10.” Ex. 1204,
`4:31–33 (emphasis Petitioner’s); see Pet. 21. According to Petitioner, a
`person of ordinary skill in the art would understand that Misra’s active areas
`are “made of” substrate 12 because they are formed in the substrate and
`defined by isolation trenches 14. See Pet. 21–22; Ex. 1202 ¶¶ 73–75.
`As noted above, claim 1 also recites a “silicon nitride film,” for which
`Petitioner relies upon Misra’s plasma-enhanced nitride layer 20. Pet. 29–30;
`Ex. 1202 ¶ 90. Petitioner argues that a person of ordinary skill in the art
`“would have understood that ‘plasma enhanced nitride’ in Misra refers to
`silicon nitride,” because “[i]n the context of MISFET devices, the term
`‘plasma enhanced nitride’ is understood to mean silicon nitride.” Pet. 32–33
`(citing Ex. 1216, 3:56–60; Ex. 1212 ¶ 17); see Ex. 1202 ¶ 96. Petitioner
`
`13 Misra discloses a metal-oxide-semiconductor (MOS) transistor. Ex. 1204,
`2:41–44; Ex. 1202 ¶ 69. Petitioner provides evidence that a MOS transistor
`is a type of MISFET where the insulator is an oxide. Pet. 20 (citing
`Ex. 1225, 59; Ex. 1202 ¶ 69).
`
`
`
`14
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`

`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
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`further relies on Tsai as providing explicit disclosure of a silicon nitride film.
`Pet. 33–34 (citing Ex. 1215, 2:29–32, 2:51–59, Fig. 2); Ex. 1202 ¶¶ 97–98.
`Petitioner provides several reasons why a person of ordinary skill in the art
`would have used a silicon nitride film as disclosed in Tsai as Misra’s
`plasma-enhanced nitride layer. Pet. 34–38. Discussed in more detail in the
`Petition, Petitioner provides the following reasons for its proposed
`combination: Tsai is in the same field of endeavor as Misra, particularly
`with respect to nitride film etch stops14 (Pet. 35–36; Ex. 1202 ¶¶ 101–102);
`the combination would have provided “known benefits, such as high
`selectivity” for etching (Pet. 36–37; Ex. 1202 ¶ 103); the combination “was
`a matter of routine engineering practice that required nothing more than
`routine skill and had a reasonable expectation of success” (Pet. 37–38;
`Ex. 1202 ¶ 104); and the combination “would have involved nothing more
`than using prior art elements according to known methods to yield
`predictable results” (Pet. 38; Ex. 1202 ¶ 105).
`Claim 1 further recites that the silicon nitride film is “formed over
`from side surfaces of the gate electrode to upper surfaces of the source/drain
`regions” and “is not formed on an upper surface of the gate electrode.” As
`seen in Figure 7 of Misra, plasma-enhanced nitride layer 20 “is formed over
`from sides of the gate electrode 28b” and “covers silicide region 18 and
`source/drain electrodes 26 and 28, that is the source drain regions.” See
`Pet. 30–32; Ex. 1202 ¶¶ 91–95. As further seen in Figure 7 of Misra,
`
`
`14 Both plasma-enhanced nitride layer 20 of Misra and silicon nitride layer
`28 of Tsai are used as etch stop layers. See Ex. 1204, 5:24–27; Ex. 1215,
`2:51–59; Pet. 30, 34.
`
`
`
`15
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`

`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
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`plasma-enhanced nitride layer 20 is not formed on an upper surface of gate
`electrode 28b. See Pet. 38–40; Ex. 1202 ¶¶ 107–110.
`Claim 1 further recites that the “gate electrode protrudes upward from
`a surface level of parts of the silicon nitride film located at both side surfaces
`of the gate electrode.” Petitioner provides an annotated version of Figure 7
`of Misra (Pet. 41), reproduced below, illustrating how Misra teaches this
`claim feature.
`
`
`Figure 7, above, shows a cross-sectional view of a semiconductor device
`according to an embodiment of Misra, as annotated by Petitioner. Ex. 1204,
`2:15–17. Petitioner’s mapping of Misra’s transistor to the “protrudes
`upward” claim limitation is consistent with Applicants’ statements during
`prosecution of the application leading to the ’501 patent:
`In the present subject matter, as shown in, for example, FIGS. 1
`and 4A [of the ’501 patent], the gate electrode 6a, 6b protrudes
`upward from a surface level of parts of the silicon nitride film
`8a, 8b located at both side surfaces of the gate electrode 6a, 6b.
`In other words, a height of the gate electrode from the
`surface of the substrate is higher than a height of the silicon
`nitride film disposed at the sides of the gate electrode.
`Ex. 1203 (Amendment dated Aug. 6, 2010), 8 (emphasis Petitioner’s); see
`Pet. 41–43; Ex. 1202 ¶¶ 114–115.
`
`
`
`16
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`Patent 7,893,501 B2
`
`Patent Owner’s Contentions
`Patent Owner argues that Petitioner’s asserted ground “fails” because
`“[e]ven if a [person of ordinary skill in the art] would have been led to
`combine Misra and Tsai in the manner alleged in the Petition, the Misra/Tsai
`combination fails to meet the requirement in all challenged claims of a
`MISFET that includes a ‘gate electrode [that] protrudes upward from a
`surface level of parts of the silicon nitride film located at both side surfaces
`of the gate electrode.’” Prelim. Resp. 10–11.
`According to Patent Owner, “[a]s Figure 7 [of Misra] makes clear, the
`silicon nitride layer 20 and spacers 23 together form a film of silicon nitride
`that covers the transistor’s source/drain region and fully covers the side
`surfaces of the gate electrode.” Id. at 12. Patent Owner provides an
`annotated version of Figure 7 of Misra (id.), reproduced below.
`
`
`Figure 7, above, shows a cross-sectional view of a semiconductor device
`according to an embodiment of Misra, as annotated by Patent Owner.
`Ex. 1204, 2:15–17. Thus, according to Patent Owner, because gate
`electrode 28b does not “protrude[] above” spacers 23, Petitioner’s
`combination does not teach a “gate electrode [that] protrudes upward from a
`
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`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
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`surface level of parts of the silicon nitride film located at both side surfaces
`of the gate electrode” as claimed. Prelim Resp. 12.
`Patent Owner’s arguments in this regard are premised primarily on its
`contention that the claimed “silicon nitride film” must encompass all silicon
`nitride structures in a prior art device. See id. at 12–20, 61–76. For the
`reasons discussed above (supra Section II.A), we are not persuaded based on
`the current record that this is required by the claims. Instead, we are
`persuaded by Petitioner’s showing that gate electrode 28b (i.e., the claimed
`gate electrode) “protrudes upward from a surface level” of plasma-enhanced
`nitride layer 20 (i.e., the claimed silicon nitride film). See Pet. 41–43.
`
`Conclusion Regarding Claim 1
`Based on the record now before us and for the reasons discussed, we
`determine that Petitioner has shown a reasonable likelihood of
`demonstrating that claim 1 would have been obvious in view of Misra and
`Tsai. Accordingly, we institute inter partes review of claim 1.
`
`Dependent Claims 4–7, 9–13, 15–19, 21, and 23–25
`We also have reviewed Petitioner’s contentions and supporting
`evidence regarding claims 4–7, 9–13, 15–19, 21, and 23–25, each of which
`depends directly or indirectly from claim 1. See Pet. 44–72; -1844 Pet. 44–
`61. Other than arguments directed to claim 1, which we have considered
`above, Patent Owner does not present additional arguments as to these
`claims at this stage of the proceeding. See Prelim. Resp. 76; -1844 Prelim.
`Resp. 79–80. Based on the record now before us, we are persuaded that
`Petitioner has shown a reasonable likelihood of demonstrating that claims 4,
`5, 7, 9–11, 15–19, 23–25 would have been obvious in view of Misra and
`
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`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
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`Tsai, that claims 6 and 21 would have been obvious in view of Misra, Tsai,
`and Oda, and that claims 12 and 13 would have been obvious in view of
`Misra, Tsai, and Hokazono. Accordingly, we institute inter partes review of
`claims 4–7, 9–13, 15–19, 21, and 23–25.
`
`III. CONCLUSION
`As discussed above, we institute an inter partes review of claims 1,
`4–7, 9–13, 15–19, 21, and 23–25 of the ’501 patent. At this preliminary
`stage in the proceeding, we have not made a final determination with respect
`to the patentability of any challenged claim or the construction of any claim
`term.
`
`IV. ORDER
`Accordingly, it is
`ORDERED that pursuant to 35 U.S.C. § 314(a), an inter partes
`review is hereby instituted as to claims 1, 4–7, 9–13, 15–19, 21, and 23–25
`of U.S. Patent No. 7,893,501 B2 on the following grounds:
`Whether claims 1, 4, 5, 7, 9–11, 15–19, and 23–25 would have
`been obvious under 35 U.S.C. § 103(a) in view of Misra and Tsai;
`Whether claims 6 and 21 would have been obvious under
`35 U.S.C. § 103(a) in view of Misra, Tsai, and Oda; and
`Whether claims 12 and 13 would have been obvious under
`35 U.S.C. § 103(a) in view of Misra, Tsai, and Hokazono;
`FURTHER ORDERED that no other ground of unpatentability is
`authorized for this inter partes review;
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`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
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`FURTHER ORDERED that pursuant to 35 U.S.C. § 314(c) and
`37 C.F.R. § 42.4, notice is hereby given of the institution of a trial; the trial
`will commence on the entry date of this Decision;
`FURTHER ORDERED that Case IPR2017-01844 is consolidated
`with Case IPR2017-01843, and all further filings in the consolidated
`proceeding shall be made in Case IPR2017-01843;
`FURTHER ORDERED that a copy of this Decision be entered into
`the file of Case IPR2017-01844; and
`FURTHER ORDERED that the case caption in Case IPR2017-01843
`shall be changed to reflect the consolidation in accordance with the
`appended example.
`
`
`
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`IPR2017-01843, IPR2017-01844
`Patent 7,893,501 B2
`
`PETITIONER:
`David L. Cavanaugh
`Dominic E. Massa
`Michael H. Smith
`WILMER CUTLER PICKERING HALE AND DORR LLP
`David.Cavanaugh@wilmerhale.com
`Dominic.Massa@wilmerhale.com
`MichaelH.Smith@wilmerhale.com
`
`
`PATENT OWNER:
`Gerald B. Hrycyszyn
`Richard F. Giunta
`Edmund J. Walsh
`WOLF, GREENFIELD & SACKS, P.C.
`GHrycyszyn-PTAB@wolfgreenfield.com
`RGiunta-PTAB@wolfgreenfield.com
`EWalsh-PTAB@wolfgreenfield.com
`
`
`
`
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`
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`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Cases IPR2017-018431
`Patent 7,893,501 B2
`____________
`
`
`1 Case IPR2017-01844 has been consolidated with this proceeding.
`
`
`
`