`571-272-7822
`
`
`Paper No. 10
`Entered: February 6, 2018
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Cases IPR2017-01841 and IPR2017-01842
`Patent 7,893,501 B2
`____________
`
`
`Before JUSTIN T. ARBES, MICHAEL J. FITZPATRICK, and
`JENNIFER MEYER CHAGNON, Administrative Patent Judges.
`
`CHAGNON, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`IPR2017-01841, IPR2017-01842
`Patent 7,893,501 B2
`
`
`I.
`
`Case Number
`
`IPR2017-01841
`
`Petition
`
`Paper 2
`(“Pet.”)
`
`INTRODUCTION
`Taiwan Semiconductor Manufacturing Company, Ltd. (“Petitioner”)
`filed two Petitions for inter partes review of, collectively, claims 1, 4–7,
`9–19, 21, and 23–25 (“the challenged claims”) of U.S. Patent No. 7,893,501
`B2 (Ex. 1001,1 “the ’501 patent”). Petitioner relies on the Declarations of
`Stanley R. Shanfield, Ph.D. (Ex. 1002; -1842 Ex. 1102) to support its
`positions. Godo Kaisha IP Bridge 1 (“Patent Owner”) filed a Preliminary
`Response in each proceeding, as listed in the following chart.
`Challenged
`Preliminary
`Claims
`Response
`1, 4, 7, 9–11, 14,
`Paper 6
`16–18, 23–25
`(“Prelim. Resp.”)
`Paper 6
`(“-1842 Prelim.
`Resp.”)
`
`IPR2017-01842
`
`5, 6, 12, 13, 15,
`19, 21
`
`Paper 2
`(“-1842 Pet.”)
`
`We have authority to determine whether to institute inter partes
`review. See 35 U.S.C. § 314(b); 37 C.F.R. § 42.4(a). Upon consideration of
`the Petitions and the Preliminary Responses, and for the reasons explained
`below, we determine that the information presented shows a reasonable
`likelihood that Petitioner would prevail with respect to all of the challenged
`claims. See 35 U.S.C. § 314(a). Accordingly, we institute trial as to the
`challenged claims, based on the grounds set forth in the Petitions. We also
`
`
`1 Unless otherwise specified with the “-1842” prefix, references to exhibits
`and papers herein are to those filed in Case IPR2017-01841.
`
`
`
`2
`
`
`
`IPR2017-01841, IPR2017-01842
`Patent 7,893,501 B2
`
`exercise our authority under 35 U.S.C. § 315(d) to consolidate the two
`proceedings and conduct the proceedings as one trial.2
`The following findings of fact and conclusions of law are not final,
`but are made for the sole purpose of determining whether Petitioner meets
`the threshold for initiating review. Any final decision shall be based on the
`full trial record, including any response timely filed by Patent Owner. Any
`arguments not raised by Patent Owner in a timely-filed response shall be
`deemed waived, even if they were presented in the Preliminary Response.
`
`A. Related Proceedings
`The parties indicate that the ’501 patent is the subject of the following
`ongoing district court proceeding: Godo Kaisha IP Bridge 1 v. Xilinx, Inc.,
`No. 2-17-cv-00100 (E.D. Tex.). Pet. 2; Paper 4, 1. Petitioner has filed two
`additional petitions challenging claims of the ’501 patent—IPR2017-01843
`and IPR2017-01844. Pet. 2; Paper 4, 1.
`
`B. The ’501 Patent
`The ’501 patent relates to a semiconductor device including a
`MISFET (metal-insulator-semiconductor field-effect transistor3) and a
`method of manufacturing the same. Ex. 1001, 1:16–19. In particular,
`the ’501 patent teaches “a first-type internal stress film formed of a silicon
`oxide film over source/drain regions of an nMISFET and a second-type
`
`
`2 As indicated in the Order, all further filings in the consolidated proceeding
`shall be made in Case IPR2017-01841. For clarity in future filings, the
`parties are instructed to cite to papers and exhibits filed only in
`Case IPR2017-01842 using the same -1842 prefix style used herein.
`3 Ex. 1002 ¶ 34.
`
`
`
`3
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`IPR2017-01841, IPR2017-01842
`Patent 7,893,501 B2
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`internal stress film formed of a TEOS [(tetraethylorthosilicate4)] film over
`source/drain regions of a pMISFET.” Id. at [57]. According to the ’501
`patent, these internal stress films generate tensile or compressive stresses
`that, respectively, allow the mobility of electrons or holes to increase.5 Id.
`Figure 1 of the ’501 patent is reproduced below.
`
`
`Figure 1, above, is a cross-sectional view of a semiconductor device of an
`embodiment of the ’501 patent. Id. at 2:47–49. The semiconductor device
`of Figure 1 includes semiconductor substrate 1, which is divided into active
`regions 1a and 1b by isolation region 2; channel regions 1x, 1y; nMISFET
`formation region Rn and pMISFET formation region Rp; source regions 3a,
`3b and drain regions 4a, 4b; gate insulating film 5; gate electrodes 6a, 6b;
`sidewalls 7; first-type internal stress film 8a (e.g., silicon nitride film);
`
`
`4 See Ex. 1005 (U.S. Patent No. 5,960,270), 5:40; Ex. 1016 (U.S. Patent
`No. 6,509,234 B1), 6:67.
`5 We note that the challenged claims do not recite these stress limitations,
`which are present only in dependent claims 2, 3, and 20. See Pet. 15 n.2.
`
`
`
`4
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`IPR2017-01841, IPR2017-01842
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`second-type internal stress film 8b (e.g., TEOS film); interlevel insulating
`film 9; lead electrode 10; and contact 11. Id. at 3:19–64.
`
`C. Illustrative Claim
`Of the challenged claims, claim 1 is independent and claims 4–7,
`9–19, 21, and 23–25 depend, directly or indirectly, therefrom. Independent
`claim 1 of the ’501 patent is reproduced below, and is illustrative of the
`challenged claims.
`1. A semiconductor device, comprising a MISFET,
`wherein
`the MISFIT includes:
`an active region made of a semiconductor substrate;
`a gate insulating film formed on the active region;
`a gate electrode formed on the gate insulating film;
`source/drain regions formed in regions of the active
`region located on both sides of the gate electrode; and
`a silicon nitride film formed over from side surfaces of
`the gate electrode to upper surfaces of the source/drain regions,
`wherein:
`the silicon nitride film is not formed on an upper surface
`of the gate electrode, and
`the gate electrode protrudes upward from a surface level
`of parts of the silicon nitride film located at both side surfaces
`of the gate electrode.
`Ex. 1001, 15:42–57.
`
`D. The Applied References
`Petitioner relies on the following references in the asserted grounds.
`Pet. 4–5; -01842 Pet. 4.
`
`
`
`
`5
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`IPR2017-01841, IPR2017-01842
`Patent 7,893,501 B2
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`Reference
`U.S. Appl. Pub. 2002/0145156 A1
`(“Igarashi”)6
`U.S. Patent No. 6,406,963 B2
`(“Woerlee”)7
`U.S. Appl. Pub. 2002/0000611 A1
`(“Hokazono”)8
`
`Date
`
`Oct. 10, 2002
`
`June 18, 2002
`
`Exhibit
`Ex. 1004
`-1842 Ex. 1104
`Ex. 1006
`-1842 Ex. 1109
`
`Jan. 3, 2002
`
`-1842 Ex. 1107
`
`E. The Asserted Grounds
`Petitioner sets forth its challenges to claims 1, 4–7, 9–19, 21, and
`23–25 as follows. Pet. 21–78; -1842 Pet. 20–75.
`References
`Basis
`Claim(s) Challenged
`1, 4–7, 9–12, 14–19,
`Igarashi and Woerlee
`§ 103
`21, 23–25
`Igarashi, Woerlee, and Hokazono
`§ 103
`13
`
`II. ANALYSIS
`A. Claim Construction
`In an inter partes review, claim terms in an unexpired patent are given
`their broadest reasonable construction in light of the specification of the
`patent in which they appear. See 37 C.F.R. § 42.100(b); Cuozzo Speed
`Techs. LLC v. Lee, 136 S. Ct. 2131, 2144–46 (2016) (upholding the use of
`the broadest reasonable interpretation standard). Under the broadest
`reasonable construction standard, claim terms generally are given their
`
`
`6 Petitioner asserts Igarashi is prior art under 35 U.S.C. §§ 102(a), 102(b),
`and 102(e). Pet. 4–5; -1842 Pet. 4.
`7 Petitioner asserts Woerlee is prior art under 35 U.S.C. §§ 102(a), 102(b),
`and 102(e). Pet. 4–5; -1842 Pet. 4.
`8 Petitioner asserts Hokazono is prior art under 35 U.S.C. §§ 102(a), 102(b),
`and 102(e). -1842 Pet. 4.
`
`
`
`6
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`Patent 7,893,501 B2
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`ordinary and customary meaning, as would be understood by one of ordinary
`skill in the art in the context of the entire disclosure. See In re Translogic
`Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). The claims, however,
`“should always be read in light of the specification and teachings in the
`underlying patent,” and “[e]ven under the broadest reasonable interpretation,
`the Board’s construction ‘cannot be divorced from the specification and the
`record evidence.’” Microsoft Corp. v. Proxyconn, Inc., 789 F.3d 1292, 1298
`(Fed. Cir. 2015) (citations omitted). Further, any special definition for a
`claim term must be set forth in the specification with reasonable clarity,
`deliberateness, and precision. See In re Paulsen, 30 F.3d 1475, 1480 (Fed.
`Cir. 1994). In the absence of such a definition, however, limitations are not
`to be read from the specification into the claims. In re Van Geuns, 988 F.2d
`1181, 1184 (Fed. Cir. 1993).
`Petitioner asserts that all terms in the challenged claims should be
`given their plain meaning under the broadest reasonable interpretation
`standard. Pet. 21.9
`Patent Owner argues that Petitioner’s proposed grounds “fail[] to meet
`[the ‘an active region made of a semiconductor substrate’] limitation as
`properly interpreted.” Prelim. Resp. 25. According to Patent Owner,
`“[u]nder the [broadest reasonable interpretation], ‘wherein the MISFET
`includes: an active region made of a semiconductor substrate’ should be
`
`
`9 Petitioner makes a similar statement regarding claim construction in
`the -1842 Petition. -1842 Pet. 20. Likewise, Patent Owner’s arguments with
`respect to claim construction are nearly identical in both Preliminary
`Responses. Compare Prelim. Resp. 24–30, with -1842 Prelim. Resp. 24–30.
`For convenience, we cite only to the Petition and the Preliminary Response
`from IPR2017-01841 in our discussion regarding claim construction.
`
`
`
`7
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`construed to require that the MISFET have ‘a region of a semiconductor
`substrate dedicated to the MISFET and defined by isolation regions that
`isolate the MISFET from other transistors formed in the substrate.’” Id.
`Patent Owner argues that the Specification of the ’501 patent
`“repeatedly refers to a semiconductor substrate being divided by isolation
`regions into a plurality of active regions.” Id. at 26 (citing Ex. 1001, 3:21–
`23, 6:22–26, 9:38–39, 10:53–54, 12:25–28, Figs. 1–9). Patent Owner
`contends that each of the embodiments has “a single MISFET formed
`therein, and where each active region is bounded by isolation regions 2 that
`isolate the single MISFET formed in the active region from other transistors
`formed in the substrate.” Id. at 26–27 (citing Ex. 1001, 3:24–28, Figs. 1–9).
`Patent Owner further argues that this usage is “consistent with the manner in
`which the term is used in the art,” asserting that the Petition and the
`references cited therein state that “a transistor’s ‘active region’ is defined by
`isolation regions,” thus, “mak[ing] clear that a transistor’s ‘active region’
`refers to a region dedicated to a single transistor.” Id. at 29–30 (citing
`Pet. 7, 8, 11; Ex. 1010, 42–43; Ex. 1008, 53, 57, Figs. 2-6–2-9; Ex. 1002
`¶¶ 66, 69, 79).
`We are not persuaded that the Specification of the ’501 patent sets
`forth a special definition for “active region” that limits it to a region
`corresponding to a single transistor, let alone doing so with reasonable
`clarity, deliberateness, and precision. See Paulsen, 30 F.3d at 1480.
`Further, claim 1 does not expressly limit the “active region” in this manner.
`See Van Geuns, 988 F.2d at 1184 (holding that limitations are not to be read
`from the specification into the claims). Contrary to Patent Owner’s
`assertion, the evidence of record does not establish that “a transistor’s
`
`
`
`8
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`IPR2017-01841, IPR2017-01842
`Patent 7,893,501 B2
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`‘active region’ refers to a region that is dedicated to that transistor.” Prelim.
`Resp. 3–4, 29–30. For example, Plummer10 describes that “regions between
`these [isolation] layers, where transistors will be built, are called the ‘active’
`regions of the substrate” (Ex. 1008, 53), and Rabaey11 describes “active
`regions” as “the regions where transistors will be constructed” (Ex. 1010,
`42). Nothing about these descriptions connotes a requirement for a
`one-to-one correspondence of active regions-to-transistors, as Patent Owner
`contends.
`Based on the record now before us, we are not persuaded that the
`claimed “active region” is limited to a region associated with a single
`transistor (i.e., “a region of a semiconductor substrate dedicated to the
`MISFET and defined by isolation regions that isolate the MISFET from
`other transistors formed in the substrate”), as Patent Owner contends. As
`discussed infra, Section II.E, Igarashi includes disclosure of “active element
`regions,” which we find to be within the scope of the plain and ordinary
`meaning of “active region.” Thus, we need not further construe “active
`region” for purposes of this Decision. The parties, however, may address
`further construction of the term during trial.
`
`B. Principles of Law
`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the subject matter sought to be patented and the prior art are such
`
`10 JAMES D. PLUMMER ET AL., SILICON VLSI TECHNOLOGY: FUNDAMENTALS,
`PRACTICE AND MODELING (Charles Sonini ed., Prentice Hall, Inc., 2000)
`(Ex. 1008).
`11 JAN M. RABAEY ET AL., DIGITAL INTEGRATED CIRCUITS: A DESIGN
`PERSPECTIVE (Charles G. Sonini ed., Pearson Educ., Inc., 2d ed. 2003)
`(Ex. 1010).
`
`
`
`9
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`IPR2017-01841, IPR2017-01842
`Patent 7,893,501 B2
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`that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of ordinary skill in the art; and (4) objective evidence of
`nonobviousness.12 Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`In that regard, an obviousness analysis “need not seek out precise
`teachings directed to the specific subject matter of the challenged claim, for
`a court can take account of the inferences and creative steps that a person of
`ordinary skill in the art would employ.” KSR, 550 U.S. at 418; accord In re
`Translogic Tech., 504 F.3d at 1259.
`We analyze the asserted grounds of unpatentability in accordance with
`these principles to determine whether Petitioner has met its burden to
`establish a reasonable likelihood of success at trial.
`
`C. Level of Ordinary Skill in the Art
`Petitioner asserts that a person of ordinary skill in the art “would have
`had the equivalent of a Master’s degree in electrical engineering, physics,
`chemistry, materials science, or equivalent training, and two years of work
`experience in [the] field of semiconductor manufacturing. Additional
`graduate education could substitute for work experience, and additional
`work experience/training could substitute for formal education.” Pet. 5–6
`
`
`12 At this stage of the proceeding, the parties have not directed our attention
`to any objective evidence of non-obviousness.
`
`
`
`10
`
`
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`IPR2017-01841, IPR2017-01842
`Patent 7,893,501 B2
`
`(citing Ex. 1002 ¶¶ 30–32); -1842 Pet. 5 (citing Ex. 1102 ¶¶ 30–32). Patent
`Owner does not dispute Petitioner’s proposed level of ordinary skill in the
`art for purposes of its Preliminary Response. See Prelim. Resp. 24; -1842
`Prelim. Resp. 24. For purposes of this Decision, we adopt Petitioner’s
`proposal regarding the level of ordinary skill in the art. The level of
`ordinary skill in the art in this case further is reflected by the prior art of
`record. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001);
`In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995); In re Oelrich,
`579 F.2d 86, 91 (CCPA 1978).
`
`D. The Asserted Prior Art
`
`Igarashi (Ex. 1004)
`Igarashi relates to a “semiconductor device with reduced parasitic
`capacity in the vicinity of gate electrodes.” Ex. 1004, at [57]. Figure 12 of
`Igarashi is reproduced below.
`
`
`Figure 12, above, is a schematic sectional view of a semiconductor device
`according to an embodiment of Igarashi. Id. ¶ 35. The semiconductor
`device of Figure 12 includes silicon semiconductor substrate 1, gate oxide
`film 2, gate electrodes 3, impurity diffusion layer 4, silicide film 5, contact
`
`
`
`11
`
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`IPR2017-01841, IPR2017-01842
`Patent 7,893,501 B2
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`electrode 6, silicon nitride film 7, silicon nitride film 8 (not labeled in Figure
`12), interlayer insulating film 9, and low-k film 15. Id. ¶¶ 44, 68–69, 117–
`22. Igarashi also discloses that, prior to the manufacturing process of the
`embodiments disclosed therein, “[e]lement isolation is performed using
`methods such as the LOCOS [(LOCal Oxidation of Silicon13)] method or the
`trench method. Thereafter, ion implantation is performed to the active
`element region for forming the well and controlling the threshold value.” Id.
`¶ 68.
`
`Woerlee (Ex. 1006)
`Woerlee relates to a method of manufacturing a semiconductor
`device. Ex. 1006, at [57]. Figure 13 of Woerlee is reproduced below.
`
`
`Figure 13, above, is a cross-sectional view of a semiconductor device
`according to an embodiment of Woerlee. Id. at 4:59–62. The
`semiconductor device of Figure 13 includes, in part, semiconductor body 1,
`oxide field insulating regions 3, active regions 4, 5, source zone 14 and drain
`zone 15, etch stop layer 17 “composed of silicon nitride,” gate structure 21,
`
`
`13 See Ex. 1008, 53.
`
`
`
`12
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`IPR2017-01841, IPR2017-01842
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`and gate dielectric 24. Id. at 4:66–5:8, 6:1–2, 6:12–13, 7:25–27, 8:24–25.
`As described in Woerlee, insulating regions 3 “are at least partly recessed in
`the semiconductor body 1” (id. at 5:2–3) and “are formed in a usual way by
`means of LOCOS (LOCal Oxidation of Silicon) or by means of STI
`(Shallow Trench Isolation)” (id. at 5:19–21).
`
`Hokazono (-1842 Ex. 1107)
`Hokazono relates to a semiconductor device with a gate electrode
`having a sidewall insulating film. -1842 Ex. 1107, at [57]. In relevant part,
`Hokazono discloses that “gate insulating film 4 [of gate electrode 5] may be
`not only a silicon oxide film but also SiON, SiN, or Ta2O5, high dielectric
`material.” Id. ¶ 59.
`
`E. Petitioner’s Asserted Grounds
`Petitioner asserts that claims 1, 4–7, 9–12, 14–19, 21, and 23–25 are
`unpatentable under 35 U.S.C. § 103 as obvious in view of Igarashi and
`Woerlee. Pet. 21–78; -1842 Pet. 20–72. Petitioner asserts that claim 13 is
`unpatentable under 35 U.S.C. § 103(a) as obvious in view of Igarashi,
`Woerlee, and Hokazono. -1842 Pet. 72–75. Patent Owner argues that
`Petitioner provides no motivation to modify Igarashi as asserted, and that
`Petitioner’s proposed combination does not teach all features of independent
`claim 1. Prelim. Resp. 4–17, 31–58; -1842 Prelim. Resp. 4–17, 31–58.
`We have reviewed the parties’ contentions and supporting evidence.
`Given the evidence on this record, and for the reasons explained below, we
`determine that the information presented shows a reasonable likelihood that
`Petitioner would prevail on these asserted grounds.
`
`
`
`13
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`
`Independent Claim 1
`
`Petitioner’s Contentions
`Petitioner provides an annotated version of Figure 12 of Igarashi,
`which illustrates the mapping of the structural elements of the
`semiconductor device of Igarashi to the claims. Pet. 16–17 (citing Ex. 1002
`¶ 47).14 Petitioner’s annotated Figure 12 (id. at 16) is reproduced below.15
`
`
`Figure 12, above, shows a schematic sectional view of a semiconductor
`device16 according to an embodiment of Igarashi, as annotated by Petitioner.
`
`
`14 Petitioner makes similar arguments regarding independent claim 1 in
`the -1842 Petition. Compare Pet. 21–46, with -1842 Pet. 20–45. Likewise,
`Patent Owner’s arguments with respect to independent claim 1 are nearly
`identical in both Preliminary Responses. Compare Prelim. Resp. 4–17, 31–
`58, with -1842 Prelim. Resp. 4–17, 31–58. For convenience, we cite only to
`the Petition and the Preliminary Response from IPR2017-01841 in our
`analysis of claim 1.
`15 Petitioner has added reference numeral 8 to Figure 12. Pet. 17 n.3 (citing
`Ex. 1004 ¶¶ 117–18; Ex. 1002 ¶ 47 n.4). This addition is consistent with the
`disclosure of Igarashi. See, e.g., Ex. 1004, Figs. 11, 13B.
`16 Igarashi discloses a metal-oxide-semiconductor (MOS) transistor.
`Ex. 1004 ¶ 2; Ex. 1002 ¶ 62. Petitioner provides evidence that a MOS
`transistor is a type of MISFET where the insulator is an oxide. Pet. 24
`(citing Ex. 1009, 59; Ex. 1002 ¶ 62).
`
`
`
`14
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`Ex. 1004 ¶ 35. Petitioner relies on Igarashi’s silicon semiconductor
`substrate 1, gate oxide film 2 (red), gate electrode 3 (orange), impurity
`diffusion layers 4 and silicide film 5 of the source/drain (green), and silicon
`nitride film 8 (blue), respectively, as teaching the claimed semiconductor
`substrate, gate insulating film, gate electrode, source/drain regions, and
`silicon nitride film. Pet. 16–17, 22–25, 37–42; Ex. 1002 ¶¶ 47–48, 60, 65,
`82–92.
`Claim 1 further recites “an active region made of a semiconductor
`substrate.” Petitioner argues that a person of ordinary skill in the art “would
`have understood that Igarashi discloses an active region made of the
`semiconductor substrate 1” (Pet. 25), based on at least the following
`disclosure of Igarashi:
`First, an insulating film for isolating elements is formed on a
`silicon semiconductor substrate 1. Element isolation is
`performed using methods such as the LOCOS method or the
`trench method. Thereafter, ion implantation is performed to
`the active element region for forming the well and controlling
`the threshold value.
`Ex. 1004 ¶ 68 (emphasis Petitioner’s); see Pet. 25–27 (arguing that the “use
`of the ‘trench method’ confirms the ‘active element region’ (active region) is
`made of the semiconductor substrate 1 because according to the trench
`method the active region is formed in the substrate and defined by the STI
`regions”); Ex. 1002 ¶ 66.
`Petitioner further relies on Woerlee as providing explicit disclosure of
`the location of the active region within the semiconductor substrate.
`Pet. 27–28; Ex. 1002 ¶¶ 67–68. Petitioner asserts that active region 4 of
`Woerlee is “made of” semiconductor body 1, as required by claim 1. Pet. 29
`(citing Ex. 1006, 4:66–5:5 (disclosing “field insulating regions 3, which are
`
`
`
`15
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`at least partly recessed in the semiconductor body 1 and which define an
`active region 4 in which a transistor . . . is to be manufactured”), 2:61–64
`(disclosing “an oxide field insulating region, which is provided at the surface
`of the semiconductor body to separate active regions in the semiconductor
`body”)); see id. at 29–31; Ex. 1002 ¶¶ 69–71. According to Petitioner,
`“Woerlee would . . . have provided a [person of ordinary skill in the art]
`additional detail on how to use the trench method disclosed in Igarashi to
`form Igarashi’s active element region (active region) in the semiconductor
`substrate 1.” Pet. 31; see id. at 31–32; Ex. 1002 ¶¶ 72–74.
`Petitioner also provides several reasons why a person of ordinary skill
`in the art would have “appl[ied] Woerlee’s teachings to Igarashi by forming
`Igarashi’s active region in the substrate and defining it with STI regions that
`divide the active region.” Pet. 32; Ex. 1002 ¶ 75. Discussed in more detail
`in the Petition, Petitioner provides the following reasons for its proposed
`combination: Woerlee is in the same field of endeavor as Igarashi (Pet. 32–
`33; Ex. 1002 ¶ 76); the combination would have provided “known benefits
`such as preventing leakage current flow” (Pet. 33–34; Ex. 1002 ¶ 77);
`Igarashi’s disclosure that element isolation is performed using the trench
`method (Ex. 1004 ¶ 68) “provides a motivation to look to other MISFET
`references such as Woerlee for additional details on forming and dividing
`the active region” (Pet. 34–35; Ex. 1002 ¶ 78); the combination “would have
`involved nothing more than using prior art elements according to known
`methods to yield predictable results” (Pet. 35–36; Ex. 1002 ¶ 79); and the
`combination “was a matter of routine engineering practice that required
`nothing more than routine skill and had a reasonable expectation of success”
`(Pet. 36–37; Ex. 1002 ¶ 80).
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`Claim 1 further recites that the silicon nitride film is “formed over
`from side surfaces of the gate electrode to upper surfaces of the source/drain
`regions” and “is not formed on an upper surface of the gate electrode.” As
`seen in Figure 12 of Igarashi, silicon nitride film 8 “covers portions of the
`side of the gate electrode 3” (Ex. 1004 ¶ 117) (i.e., is “over from side
`surfaces of the gate electrode”) and is “formed over diffusion layer 4, which
`is part of the source/drain regions and covers silicide film 5, which is also
`part of the source drain regions” (Pet. 42 (citing Ex. 1004 ¶¶ 48, 117))
`(i.e., is “formed . . . to upper surfaces of the source/drain regions”). See
`Pet. 42–44; Ex. 1002 ¶¶ 92–95. As further seen in Figure 12 of Igarashi,
`silicon nitride film 8 is not formed on an upper surface of gate electrode 3.
`See Pet. 44–45; Ex. 1002 ¶¶ 96–98.
`Claim 1 further recites that the “gate electrode protrudes upward from
`a surface level of parts of the silicon nitride film located at both side surfaces
`of the gate electrode.” Petitioner provides an annotated version of Figure 12
`of Igarashi (Pet. 45), reproduced below, illustrating how Igarashi teaches this
`claim feature.
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`Figure 12, above, shows a schematic sectional view of a semiconductor
`device according to an embodiment of Igarashi, as annotated by Petitioner.
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`Ex. 1004 ¶ 35. Petitioner’s mapping of Igarashi’s semiconductor device to
`the “protrudes upward” claim limitation is consistent with Applicants’
`statements during prosecution of the application leading to the ’501 patent:
`In the present subject matter, as shown in, for example, FIGS. 1
`and 4A [of the ’501 patent], the gate electrode 6a, 6b protrudes
`upward from a surface level of parts of the silicon nitride film
`8a, 8b located at both side surfaces of the gate electrode 6a, 6b.
`In other words, a height of the gate electrode from the
`surface of the substrate is higher than a height of the silicon
`nitride film disposed at the sides of the gate electrode.
`Ex. 1003 (Amendment dated Aug. 6, 2010), 8 (emphasis Petitioner’s); see
`Pet. 45–46; Ex. 1002 ¶¶ 99–102.
`
`Patent Owner’s Contentions
`Patent Owner argues that Petitioner’s asserted ground “fails for two
`reasons.” Prelim. Resp. 4, 31. We address each in turn.
`First, Patent Owner argues that Petitioner’s asserted ground “relies
`upon disparate features from different embodiments in Igarashi that Igarashi
`nowhere describes as being used together and arranged in the manner
`required by the claims.” Id. at 4; see id. at 31–32. In this regard, Patent
`Owner argues that the Fifth Embodiment described in Igarashi, itself, does
`not teach STI regions forming an active region. Id. at 7, 38–44. Patent
`Owner asserts that the “active element region” of Igarashi, on which
`Petitioner relies, is related to Igarashi’s “First Embodiment,” whereas
`Petitioner relies on Figure 12 of Igarashi (i.e., the “Fifth Embodiment”) for
`all other features of claim 1. Id. at 5; see also id. at 44–47 (arguing
`Petitioner provides no motivation to modify the fifth embodiment to use
`isolation regions of the first embodiment).
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`Based on the current record, however, we find it is clear from Igarashi
`that the disclosure of “active element region[s]” discussed in paragraph 68
`with respect to the “First Embodiment” is equally applicable to the “Fifth
`Embodiment” upon which Petitioner primarily relies. For example, the
`description of the method for manufacturing the semiconductor device of the
`“Fifth Embodiment” refers back to earlier described embodiments of
`Igarashi, ultimately referencing the discussion of the method for
`manufacturing the semiconductor device of the “First Embodiment.”
`Ex. 1004 ¶ 119 (“FIGS. 13A and 13[B] are schematic sectional views
`sequentially showing the method for manufacturing the semiconductor
`device shown in FIG. 12 [the Fifth Embodiment]. Here, FIG. 13A shows the
`same process as in FIG. 11B . . . .”), ¶¶ 112–13 (“FIGS. 11A to 11C are
`schematic sectional views showing the method for manufacturing the
`semiconductor device shown in FIG. 10 [the Fourth Embodiment]. . . . First,
`as FIG. 11A shows, gate electrodes 3 are formed, and silicon nitride films 7
`and silicon nitride films S are formed so as to cover the gate electrodes 3 in
`the same process as in FIG. 5 . . . .”), ¶ 68 (“[T]he method for manufacturing
`the semiconductor device of First Embodiment will be described. In the
`following description of the manufacturing method, the major process for
`forming the silicon nitride film 7 will be described referring to FIGS. 5A to
`5E, and other processes will be described without referring to drawings.
`First, an insulating film for isolating elements is formed on a silicon
`semiconductor substrate 1. Element isolation is performed using methods
`such as the LOCOS method or the trench method. Thereafter, ion
`implantation is performed to the active element region for forming the well
`and controlling the threshold value.”).
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`Also, contrary to Patent Owner’s assertion (Prelim. Resp. 8–9),
`Petitioner does not ignore the fact that its citations are directed to discussion
`of different embodiments of Igarashi. In fact, Petitioner squarely addresses
`the issue, arguing that a person of ordinary skill in the art “would have
`understood that the disclosure of the features in Igarashi common to
`different illustrations are applicable to the embodiment shown in Figure 12
`because the same reference numerals are used to describe common features
`of Igarashi’s disclosure” and, “[w]here features differ between figures, the
`differences are described in the disclosure of Igarashi.” Pet. 22 (citing
`37 C.F.R. § 1.84(p)(4)). For these reasons, we are not persuaded on this
`record that Petitioner inappropriately relies on different embodiments of
`Igarashi.
`Second, Patent Owner argues that “even if a [person of ordinary skill
`in the art] would have been led to combine the features of Igarashi and
`Woerlee in the manner alleged in the Petition, the resulting semiconductor
`device does not include a MISFET having an active region as claimed.”
`Prelim. Resp. 4; see id. at 32. Patent Owner’s arguments in this regard are
`premised primarily on its contention that an “active region” is limited to
`regions associated with a single transistor. See Prelim. Resp. 9–17, 47–58.
`For the reasons discussed above (supra Section II.A), we are not persuaded
`based on the current record that the claims are so limited. Further, as
`discussed above, we are persuaded on the record now before us that
`Igarashi’s disclosure of “active element region[s]” applies to the
`embodiment described with respect to Figure 12 of Igarashi. Petitioner
`relies on Woerlee for its teaching that “because the isolation regions 3
`formed in the semiconductor substrate 1 define the active region 4 of the
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`substrate body 1 where the transistor is formed,” the active region formed
`therebetween is “made of” the semiconductor substrate as claimed. See
`Pet. 28. For these reasons, Patent Owner’s arguments are not persuasive.
`
`Conclusion Regardin