TPS5210
`PROGRAMMABLE SYNCHRONOUSĆBUCK REGULATOR CONTROLLER
`
`SLVS171A − SEPTEMBER 1998 − REVISED MAY 1999
`
`DW OR PWP PACKAGE
`(TOP VIEW)
`
`28
`27
`26
`25
`24
`23
`22
`21
`20
`19
`18
`17
`16
`15
`
`PWRGD
`VID0
`VID1
`VID2
`VID3
`VID4
`INHIBIT
`IOUTLO
`LOSENSE
`HISENSE
`BOOTLO
`HIGHDR
`BOOT
`VCC
`
`1 2 3 4
`
`
`
`5 6 7 8 9 1
`
`0
`11
`12
`13
`14
`
`IOUT
`DROOP
`OCP
`VHYST
`VREFB
`VSENSE
`ANAGND
`SLOWST
`BIAS
`LODRV
`LOHIB
`DRVGND
`LOWDR
`DRV
`
`D ±1% Reference Over Full Operating
`Temperature Range
`D Synchronous Rectifier Driver for Greater
`Than 90% Efficiency
`D Programmable Reference Voltage Range of
`1.3 V to 3.5 V
`D User−Selectable Hysteretic Type Control
`D Droop Compensation for Improved Load
`Transient Regulation
`D Adjustable Overcurrent Protection
`D Programmable Softstart
`D Overvoltage Protection
`D Active Deadtime Control
`D Power Good Output
`D Internal Bootstrap Schottky Diode
`D Low Supply Current . . . 3-mA Typ
`
`
`description
`
`The TPS5210 is a synchronous-buck regulator controller which provides an accurate, programmable supply
`voltage to microprocessors. An internal 5-bit DAC is used to program the reference voltage to within a range
`of 1.3 V to 3.5 V. The output voltage can be set to be equal to the reference voltage or to some multiple of the
`reference voltage. A hysteretic controller with user-selectable hysteresis and programmable droop
`compensation is used to dramatically reduce overshoot and undershoot caused by load transients. Propagation
`delay from the comparator inputs to the output drivers is less than 250 ns. Overcurrent shutdown and crossover
`protection for the output drivers combine to eliminate destructive faults in the output FETs. The softstart current
`source is proportional to the reference voltage, thereby eliminating variation of the softstart timing when
`changes are made to the output voltage. PWRGD monitors the output voltage and pulls the open-collector
`output low when the output drops 7% below the nominal output voltage. An overvoltage circuit disables the
`output drivers if the output voltage rises 15% above the nominal value. The inhibit pin can be used to control
`power sequencing. Inhibit and undervoltage lockout assures the 12-V supply voltage and system supply voltage
`(5 V or 3.3 V) are within proper operating limits before the controller starts. Single-supply (12 V) operation is
`easily accomplished using a low-current divider for the required 5-V signals. The output driver circuits include
`2-A drivers with internal 8-V gate-voltage regulators. The high-side driver can be configured either as a
`ground-referenced driver or as a floating bootstrap driver. The TPS5210 is available in a 28-pin SOIC package
`and a 28-pin TSSOP PowerPAD package. It operates over a junction temperature range of 0°C to 125°C.
`
`AVAILABLE OPTIONS
`PACKAGES
`
`TJ
`
`SOIC
`(DW)
`
`TSSOP
`(PWP)
`
`0°C to 125°C
`TPS5210PWPR
`TPS5210DW
`The DW package is available taped and reeled. Add R suffix to device
`type (e.g., TPS5210DWR).
`
`Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
`Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
`
`is current as of publication date.
`information
`PRODUCTION DATA
`Products conform to specifications per the terms of Texas Instruments
`standard warranty. Production processing does not necessarily include
`testing of all parameters.
`
`Copyright  1999, Texas Instruments Incorporated
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`1
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1008
`Page 1 of 34
`
`

`

`DRVGND
`
`LOWDR
`
`12
`
`13
`
`BOOTLO
`
`18
`200 kΩ
`
`HIGHDR
`BOOT
`
`17
`16
`
`DRV
`
`BIAS
`
`4
`9 1
`
`SLVS171A − SEPTEMBER 1998 − REVISED MAY 1999
`
`functional block diagram
`
`HIGHDR
`
`Delay
`Edge
`Rising
`
`IOUT
`
`1
`
`2x
`
`−+
`
`Fault
`
`Q
`
`S
`
`R
`
`Shutdown
`
`19
`
`21
`
`20
`
`28
`
`IOUTLOHISENSE
`
`LOSENSE
`
`PWRGD
`
`7
`
`ANAGND
`
`15
`VCC
`
`LODRV
`10
`
`LOHIB
`11
`
`VREFBDROOPVHYSTVSENSE
`
`6
`
`4
`
`2
`
`5
`
`VID0VID1VID2VID3VID4
`23
`
`24
`
`25
`
`26
`
`27
`
`200 kΩ
`
`Shutdown
`
`Comp
`Hysteresis
`
`−+
`
`CM Filters
`
`Setting
`
`Hysteresis
`
`IVREFB
`
`− +
`
`−
`
`+Σ
`
`VREF
`
`Decoder
`
`and
`MUX
`VID
`
`Shutdown
`
`Bandgap
`
`DRV REG
`
`Bias
`Analog
`
`PREREG
`
`Comp
`Slowstart
`
`−+
`
`VCC
`
`HIGHIN
`
`0.93 Vref
`VPGD
`
`IVREFB
`
`5
`
`Analog Bias
`
`VSENSE
`
`1.15 Vref
`VOVP
`
`Deglitch
`
`Deglitch
`
`+−
`
`100 mV
`
`+
`
`UVLO
`
`NOCPU
`
`VCC
`
`10 V
`
`2 V
`
`Decode
`11111
`
`VID4
`VID3
`VID2
`VID1
`VID0
`
`8
`
` SLOWST
`
`3
`
`OCP
`
`22
`
`INHIBIT
`
`2
`
`•
`POST OFFICE BOX 655303 DALLAS, TEXAS 75265
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1008
`Page 2 of 34
`
`

`

`TPS5210
`PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
`
`SLVS171A − SEPTEMBER 1998 − REVISED MAY 1999
`
`Terminal Functions
`
`
`
`I/OI/O
`
`
`
`DESCRIPTIONDESCRIPTION
`
`O
`I
`O
`
`I
`
`O
`
`O
`I
`
`I
`
`O
`
`O
`
`I
`I
`
`I
`
`O
`I
`O
`
`O
`
`I
`
`I
`I
`I
`I
`I
`
`O
`I
`
`Analog ground
`Analog BIAS pin. A 1-µF ceramic capacitor should be connected from BIAS to ANAGND.
`Bootstrap. Connect a 1-µF low-ESR capacitor from BOOT to BOOTLO.
`Bootstrap low. Connect BOOTLO to the junction of the high-side and low-side FETs for floating drive
`configuration. Connect BOOTLO to PGND for ground reference drive configuration.
`
`Droop voltage. Voltage input used to set the amount of output-voltage set-point droop as a function of load
`current. The amount of droop compensation is set with a resistor divider between IOUT and ANAGND.
`Drive regulator for the FET drivers. A 1-µF ceramic capacitor should be connected from DRV to DRVGND.
`Drive ground. Ground for FET drivers. Connect to FET PWRGND.
`High drive. Output drive to high-side power switching FETs
`High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs; for
`optional resistor sensing scheme, connect to power supply side of current-sense resistor placed in series with
`high-side FET drain.
`Disables the drive signals to the MOSFET drivers. Can also serve as UVLO for system logic supply (either 3.3 V
`or 5 V).
`
`Current out. Output voltage on this pin is proportional to the load current as measured across the Rds(on) of the
`high-side FETs. The voltage on this pin equals 2×Rds(on)×IOUT. In applications where very accurate current
`sensing is required, a sense resistor should be connected between the input supply and the drain of the high-side
`FETs.
`Current sense low output. This is the voltage on the LOSENSE pin when the high-side FETs are on. A ceramic
`capacitor should be connected from IOUTLO to HISENSE to hold the sensed voltage while the high-side FETs
`are off. Capacitance range should be between 0.033 µF and 0.1 µF.
`Low drive enable. Normally tied to 5 V. To activate the low-side FETs as a crowbar, pull LODRV low.
`Low side inhibit. Connect to the junction of the high and low side FETs to control the anti-cross-conduction and
`eliminate shoot-through current. Disabled when configured in crowbar mode.
`
`Low current sense. For current sensing across high-side FETs, connect to the source of the high-side FETs; for
`optional resistor sensing scheme, connect to high-side FET drain side of current-sense resistor placed in series
`with high-side FET drain.
`Low drive. Output drive to synchronous rectifier FETs
`Over current protection. Current limit trip point is set with a resistor divider between IOUT and ANAGND.
`Power good. Power Good signal goes high when output voltage is within 7% of voltage set by VID pins.
`Open-drain output.
`
`Slow Start (soft start). A capacitor from SLOWST to ANAGND sets the slowstart time.
`Slowstart current = IVREFB/5
`12-V supply. A 1-µF ceramic capacitor should be connected from VCC to DRVGND.
`HYSTERESIS set pin. The hysteresis is set with a resistor divider from VREFB to ANAGND.
`The hysteresis window = 2 × (VREFB – VHYST)
`Voltage Identification input 0
`Voltage Identification input 1
`Voltage Identification input 2
`Voltage Identification input 3
`Voltage Identification input 4. Digital inputs that set the output voltage of the converter. The code pattern for
`setting the output voltage is located in Table 1. Internally pulled up to 5 V with a resistor divider biased from VCC.
`Buffered reference voltage from VID network
`Voltage sense Input. To be connected to converter output voltage bus to sense and control output voltage. It is
`recommended an RC low pass filter be connected at this pin to filter noise.
`
`TERMINAL
`NAME
`NO.
`ANAGND
`7
`BIAS
`9
`BOOT
`16
`BOOTLO
`18
`
`DROOP
`
`DRV
`DRVGND
`HIGHDR
`HISENSE
`
`INHIBIT
`
`IOUT
`
`IOUTLO
`
`LODRV
`LOHIB
`
`LOSENSE
`
`LOWDR
`OCP
`PWRGD
`
`SLOWST
`
`VCC
`VHYST
`
`VID0
`VID1
`VID2
`VID3
`VID4
`
`VREFB
`VSENSE
`
`2
`
`14
`12
`17
`19
`
`22
`
`1
`
`21
`
`10
`11
`
`20
`
`13
`3
`28
`
`8
`
`15
`4
`
`27
`26
`25
`24
`23
`
`5
`6
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`3
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1008
`Page 3 of 34
`
`

`

`TPS5210
`PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
`
`SLVS171A − SEPTEMBER 1998 − REVISED MAY 1999
`
`detailed description
`
`VREF
`The reference/voltage identification (VID) section consists of a temperature-compensated bandgap reference
`and a 5-bit voltage selection network. The 5 VID terminals are inputs to the VID selection network and are
`TTL-compatible inputs internally pulled up to 5 V by a resistor divider connected to VCC. The VID codes conform
`to the Intel VRM 8.3 DC-DC Converter Specification for voltage settings between 1.8 V and 3.5 V, and they are
`decremented by 50 mV, down to 1.3 V, for the lower VID settings. Voltages higher than VREF can be implemented
`using an external divider. Refer to Table 1 for the VID code settings. The output voltage of the VID network, VREF,
`is within ±1% of the nominal setting over the VID range of 1.3 V to 2.5 V, including a junction temperature range
`of 5°C to +125°C, and a VCC supply voltage range of 11.4 V to 12.6 V. The output of the reference/VID network
`is indirectly brought out through a buffer to the VREFB pin. The voltage on this pin will be within 2% of VREF. It
`is not recommended to drive loads with VREFB, other than setting the hysteresis of the hysteretic comparator,
`because the current drawn from VREFB sets the charging current for the slowstart capacitor. Refer to the
`slowstart section for additional information.
`
`hysteretic comparator
`
`The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
`set by 2 external resistors and is centered on VREF. The 2 external resistors form a resistor divider from VREFB
`to ANAGND, with the output voltage connecting to the VHYST pin. The hysteresis of the comparator will be equal
`to twice the voltage difference between the VREFB and VHYST pins. The propagation delay from the comparator
`inputs to the driver outputs is 250 ns (maximum). The maximum hysteresis setting is 60 mV.
`
`low-side driver
`
`The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
`2 A, source and sink. The bias to the low-side driver is internally connected to the DRV regulator.
`
`high-side driver
`
`The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
`2 A, source and sink. The high-side driver can be configured either as a ground-referenced driver or as a floating
`bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from the DRV
`regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved
`drive efficiency. The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver
`can be referenced to ground by connecting BOOTLO to DRVGND, and connecting BOOT to either DRV or VCC.
`deadtime control
`
`Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
`transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side driver is not allowed
`to turn on until the gate-drive voltage to the low-side FETs is below 2 V; the low-side driver is not allowed to turn
`on until the voltage at the junction of the high-side and low-side FETs (Vphase) is below 2 V.
`
`current sensing
`
`Current sensing is achieved by sampling and holding the voltage across the high-side power FETs while the
`high-side FETs are on. The sampling network consists of an internal 60-Ω switch and an external ceramic hold
`capacitor. Recommended value of the hold capacitor is between 0.033 µF and 0.1 µF. Internal logic controls
`the turn-on and turn-off of the sample/hold switch such that the switch does not turn on until the Vphase voltage
`transitions high, and the switch turns off when the input to the high-side driver goes low. The sampling will occur
`only when the high-side FETs are conducting current. The voltage on the IOUT pin equals 2 times the sensed
`high-side voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can
`be placed in series with the high-side FETs, and the voltage across the sense resistor can be sampled by the
`current sensing circuit.
`
`4
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1008
`Page 4 of 34
`
`

`

`TPS5210
`PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
`
`SLVS171A − SEPTEMBER 1998 − REVISED MAY 1999
`
`detailed description (continued)
`
`droop compensation
`The droop compensation network reduces the load transient overshoot/undershoot on VO, relative to VREF. VO
`is programmed to a voltage greater than VREF by an external resistor divider from VO to VSENSE to reduce the
`undershoot on VO during a low-to-high load transient. The overshoot during a high-to-low load transient is
`reduced by subtracting the voltage on DROOP from VREF. The voltage on IOUT is divided with an external
`resistor divider, and connected to DROOP.
`
`inhibit
`
`INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low, the output drivers
`are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart
`capacitor is released and normal converter operation begins. When the system-logic supply is connected to
`INHIBIT, it also controls power sequencing by locking out controller operation until the system-logic supply
`exceeds the input threshold voltage of the inhibit circuit. The 12-V supply and the system logic supply (either
`5 V or 3.3 V) must be above UVLO thresholds before the controller is allowed to start up. The start threshold
`is 2.1 V and the hysteresis is 100 mV for the INHIBIT comparator.
`VCC undervoltage lockout (UVLO)
`The undervoltage lockout circuit disables the controller while the VCC supply is below the 10-V start threshold
`during power up. When the controller is disabled, the output drivers will be low and the slowstart capacitor is
`discharged. When VCC exceeds the start threshold, the short across the slowstart capacitor is released and
`normal converter operation begins. There is a 2-V hysteresis in the undervoltage lockout circuit for noise
`immunity.
`
`slowstart
`The slowstart circuit controls the rate at which VO powers up. A capacitor is connected between SLOWST and
`ANAGND and is charged by an internal current source. The current source is proportional to the reference
`voltage, so that the charging rate of Cslowst is proportional to the reference voltage. By making the charging
`current proportional to VREF, the power-up time for VO will be independent of VREF. Thus, CSLOWST can remain
`the same value for all VID settings. The slowstart charging current is determined by the following equation:
`Islowstart = I(VREFB) / 5 (amps)
`Where I(VREFB) is the current flowing out of VREFB.
`It is recommended that no additional loads be connected to VREFB, other than the resistor divider for setting the
`hysteresis voltage. The maximum current that can be sourced by the VREFB circuit is 500 µA. The equation for
`setting the slowstart time is:
`tSLOWST = 5 × CSLOWST × RVREFB (seconds)
`Where RVREFB is the total external resistance from VREFB to ANAGND.
`power good
`The power-good circuit monitors for an undervoltage condition on VO. If VO is 7% below VREF, then the PWRGD
`pin is pulled low. PWRGD is an open-drain output.
`
`overvoltage protection
`The overvoltage protection (OVP) circuit monitors VO for an overvoltage condition. If VO is 15% above VREF,
`then a fault latch is set and both output drivers are turned off. The latch will remain set until VCC goes below the
`undervoltage lockout value. A 3-µs deglitch timer is included for noise immunity. Refer to the LODRV section
`for information on how to protect the microprocessor against overvoltages due to a shorted fault across the
`high-side power FET.
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`5
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1008
`Page 5 of 34
`
`

`

`TPS5210
`PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
`
`SLVS171A − SEPTEMBER 1998 − REVISED MAY 1999
`
`detailed description (continued)
`
`overcurrent protection
`
`The overcurrent protection (OCP) circuit monitors the current through the high-side FET. The overcurrent
`threshold is adjustable with an external resistor divider between IOUT and ANAGND, with the divider voltage
`connected to the OCP pin. If the voltage on OCP exceeds 100 mV, then a fault latch is set and the output drivers
`are turned off. The latch will remain set until VCC goes below the undervoltage lockout value. A 3-µs deglitch
`timer is included for noise immunity. The OCP circuit is also designed to protect the high-side power FET against
`a short-to-ground fault on the terminal common to both power FETs.
`
`drive regulator
`
`The drive regulator provides drive voltage to the output drivers. The minimum drive voltage is 7 V. The minimum
`short circuit current is 100 mA. Connect a 1-µF ceramic capacitor from DRV to DRVGND.
`LODRV
`
`The LODRV circuit is designed to protect the microprocessor against overvoltages that can occur if the high-side
`power FETs become shorted. External components to sense an overvoltage condition are required to use this
`feature. When an overvoltage fault occurs, the low-side FETs are used as a crowbar. LODRV is pulled low and
`the low-side FET will be turned on, overriding all control signals inside the TPS5210 controller. The crowbar
`action will short the input supply to ground through the faulted high-side FETs and the low-side FETs. A fuse
`in series with Vin should be added to disconnect the short-circuit.
`
`Table 1. Voltage Identification Codes
`
`VID TERMINALS
`(0 = GND, 1 = floating or pull-up to 5 V)
`VID3
`VID2
`VID1
`1
`1
`1
`1
`1
`1
`1
`1
`0
`1
`1
`0
`1
`0
`1
`1
`0
`1
`1
`0
`0
`1
`0
`0
`0
`1
`1
`0
`1
`1
`0
`1
`0
`0
`1
`0
`0
`0
`1
`0
`0
`1
`0
`0
`0
`0
`0
`0
`1
`1
`1
`1
`1
`1
`1
`1
`0
`1
`1
`0
`1
`0
`1
`1
`0
`1
`1
`0
`0
`
`VID4
`0
`0
`0
`0
`0
`0
`0
`0
`0
`0
`0
`0
`0
`0
`0
`0
`1
`1
`1
`1
`1
`1
`1
`
`VID0
`1
`0
`1
`0
`1
`0
`1
`0
`1
`0
`1
`0
`1
`0
`1
`0
`1
`0
`1
`0
`1
`0
`1
`
`VREF
`
`(Vdc)
`1.30
`1.35
`1.40
`1.45
`1.50
`1.55
`1.60
`1.65
`1.70
`1.75
`1.80
`1.85
`1.90
`1.95
`2.00
`2.05
`No CPU
`2.10
`2.20
`2.30
`2.40
`2.50
`2.60
`
`6
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1008
`Page 6 of 34
`
`

`

`TPS5210
`PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
`
`SLVS171A − SEPTEMBER 1998 − REVISED MAY 1999
`
`Table 1. Voltage Identification Codes (Continued)
`
`VID TERMINALS
`(0 = GND, 1 = floating or pull-up to 5 V)
`VID3
`VID2
`VID1
`1
`0
`0
`0
`1
`1
`0
`1
`1
`0
`1
`0
`0
`1
`0
`0
`0
`1
`0
`0
`1
`0
`0
`0
`0
`0
`0
`
`VID4
`1
`1
`1
`1
`1
`1
`1
`1
`1
`
`VID0
`0
`1
`0
`1
`0
`1
`0
`1
`0
`
`VREF
`
`(Vdc)
`2.70
`2.80
`2.90
`3.00
`3.10
`3.20
`3.30
`3.40
`3.50
`
`absolute maximum ratings over operating virtual junction temperature (unless otherwise noted)†
`
`Supply voltage range, VCC (see Note1)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`−0.3 V to 14 V
`Input voltage range: BOOT to DRVGND (High-side Driver ON)
`. . . . . . . . . . . . . . . . . . . . . . . . .
`−0.3 V to 30 V
`BOOT to HIGHDRV
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`−0.3 V to 15 V
`BOOT to BOOTLO
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`−0.3 V to 15 V
`INHIBIT, VIDx, LODRV
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`−0.3 V to 7.3 V
`PWRGD, OCP, DROOP
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`−0.3 V to 7 V
`LOHIB, LOSENSE, IOUTLO, HISENSE
`−0.3 V to 14 V
`. . . . . . . . . . . . . . . . . . . . . . . . . .
`VSENSE
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`−0.3 V to 5 V
`±0.5 V
`Voltage difference between ANAGND and DRVGND
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Output current, VREFB
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`0.5 mA
`Short circuit duration, DRV
`Continuous
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Continuous total power dissipation
`See Dissipation Rating Table
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`0°C to 125°C
`Operating virtual junction temperature range, TJ
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`−65°C to 150°C
`Storage temperature range, Tstg
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`260°C
`Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds
`. . . . . . . . . . . . . . . . . . . . . . .
`† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
`functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
`implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
`NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND.
`
`PACKAGE
`
`TA ≤ 25°C
`POWER RATING
`
`DW
`PWP
`
`1200 mW
`1150 mW
`
`DISSIPATION RATING TABLE
`DERATING FACTOR
`ABOVE TA = 25°C
`12 mW/°C
`11.5 mW/°C
`
`TA = 70°C
`POWER RATING
`
`TA = 85°C
`POWER RATING
`
`660 mW
`630 mW
`
`480 mW
`460 mW
`
`POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
`
`7
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1008
`Page 7 of 34
`
`

`

`TPS5210
`PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
`
`SLVS171A − SEPTEMBER 1998 − REVISED MAY 1999
`
`recommended operating conditions
`
`Supply voltage, VCC
`Input voltage, BOOT to DRVGND
`Input voltage, BOOT to BOOTLO
`Input voltage, INHIBIT, VIDx, LODRV, PWRGD, OCP, DROOP
`Input voltage, LOHIB, LOSENSE, IOUTLO, HISENSE
`Input voltage, VSENSE
`Voltage difference between ANAGND and DRVGND
`Output current, VREFB†
`† Not recommended to load VREFB other than to set hystersis since IVREFB sets slowstart time.
`
`MIN MAX
`11.4
`13
`0
`28
`0
`13
`0
`6
`0
`13
`0
`4.5
`±0.2
`0
`0
`0.4
`
`UNIT
`V
`V
`V
`V
`V
`V
`V
`mA
`
`electrical characteristics over recommended operating virtual junction temperature range,
`VCC = 12 V, IDRV = 0 A (unless otherwise noted)
`reference/voltage identification
`
`PARAMETER
`
`TEST CONDITIONS
`VCC = 11.4 to 12.6 V, 1.3 V ≤ VREF ≤ 2.5 V
`VCC = 11.4 to 12.6 V, VREF = 2.6 V
`VCC = 11.4 to 12.6 V, VREF = 2.7 V
`VCC = 11.4 to 12.6 V, VREF = 2.8 V
`Reference voltage accuracy, (Includes VCC = 11.4 to 12.6 V, VREF = 2.9 VReference voltage accuracy, (Includes
`
`VCC = 11.4 to 12.6 V, VREF = 3 V
`offset of droop compensation net-
`offset of droop compensation net-
`work)
`work)
`VCC = 11.4 to 12.6 V, VREF = 3.1 V
`VCC = 11.4 to 12.6 V, VREF = 3.2 V
`VCC = 11.4 to 12.6 V, VREF = 3.3 V
`VCC = 11.4 to 12.6 V, VREF = 3.4 V
`VCC = 11.4 to 12.6 V, VREF = 3.5 V
`VREF = 1.3 V, Hysteresis window = 30 mV
`VREF =1.3 V, Hysteresis,
`TJ = 60°C window = 30 mV (see Note 3)
`VREF = 1.9 Vv, Hysteresis,
`TJ = 60°C window = 30 mV (see Note 3)
`VREF = 3.5 V, Hysteresis,
`TJ = 60°C window = 30 mV (see Note 3)
`
`Cumulative reference accuracy
`Cumulative reference accuracy
`(see Note 2)
`
`TYP
`
`MIN
`−0.01
`−0.0104
`−0.0108
`−0.0112
`−0.0116
`−0.0120
`−0.0124
`−0.0128
`−0.0132
`−0.0136
`−0.0140
`−0.011
`
`−0.008
`
`−0.0090
`
`−0.0115
`
`UNIT
`V/V
`V/V
`V/V
`V/V
`V/V
`V/V
`V/V
`V/V
`V/V
`V/V
`V/V
`
`V/V
`
`MAX
`0.01
`0.0104
`0.0108
`0.0112
`0.0116
`0.0120
`0.0124
`0.0128
`0.0132
`0.0136
`0.0140
`0.011
`
`0.008
`
`0.0090
`
`0.0115
`
`
`
`VREFVREF
`
`VIDx
`VIDx
`
`
`
`VIDxVIDx
`
`IVREFB = 50 µA
`10 µA ≤ IO ≤ 500 µA
`VIDx = 0 V
`
`High-level input voltage
`Low-level input voltage
`Output voltage
`VREFB
`VREFB Output regulation
`mV
`kΩ
`95
`73
`36
`Input resistance
`V
`5
`4.9
`4.8
`Input pull-up voltage divider
`NOTES: 2. Cumulative reference accuracy is the combined accuracy of the reference voltage and the input offset voltage of the hysteretic
`comparator. Cumulative accuracy equals the average of the high-level and low-level thresholds of the hysteretic comparator.
`3. This parameter is ensured by design and is not production tested.
`
`2.25
`
`1
`VREF−2% VREF VREF+2%
`2
`
`V
`V
`V
`
`8
`
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`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1008
`Page 8 of 34
`
`

`

`TPS5210
`PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
`
`SLVS171A − SEPTEMBER 1998 − REVISED MAY 1999
`
`electrical characteristics over recommended operating virtual junction temperature range,
`VCC = 12 V, IDRV = 0 A (unless otherwise noted) (continued)
`power good
`
`TEST CONDITIONS
`
`IO = 5 mA
`VPWRGD = 6 V
`
`MIN
`90
`
`1.3
`
`UNIT
`TYP MAX
`93
`95 %VREF
`0.5
`0.75
`V
`µA
`1
`2.9
`4.5 %VREF
`
`PARAMETER
`Undervoltage trip threshold
`Low-level output voltage
`High-level input current
`Hysteresis voltage
`
`VOL
`IOH
`Vhys
`
`slowstart
`
`PARAMETER
`
`Charge current
`
`MIN
`
`TYP MAX
`
`UNIT
`
`10.4
`
`−7.5
`
`MIN
`−2.5
`
`−3.5
`
`13
`
`3
`
`10
`
`15.6
`
`10
`100
`7.5
`
`µA
`
`mA
`mV
`nA
`mV
`
`TYP MAX
`2.5
`500
`3.5
`
`60
`
`UNIT
`mV
`nA
`mV
`
`mV
`
`TEST CONDITIONS
`VSLOWST = 0.5 V,
`VVREFB = 1.3 V,
`IVREFB = 65 µA
`VSLOWST = 1 V
`
`Discharge current
`Comparator input offset voltage
`Comparator input bias current
`Comparator hysteresis
`NOTE 3: This parameter is ensured by design and is not production tested.
`
`See Note 3
`
`hysteretic comparator
`PARAMETER
`Input offset voltage
`Input bias current
`Hysteresis accuracy
`
`TEST CONDITIONS
`VDROOP = 0 V (see Note 3)
`See Note 3
`VREFB – VHYST = 15 mV
`(Hysteresis window = 30 mV)
`VREFB – VHYST = 30 mV
`Maximum hysteresis setting
`NOTE 3: This parameter is ensured by design and is not production tested.
`
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`
`9
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1008
`Page 9 of 34
`
`

`

`TPS5210
`PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
`
`SLVS171A − SEPTEMBER 1998 − REVISED MAY 1999
`
`electrical characteristics over recommended operating virtual junction temperature range,
`VCC = 12 V, IDRV = 0 A (unless otherwise noted) (continued)
`high-side VDS sensing
`PARAMETER
`
`TEST CONDITIONS
`
`MIN
`
`TYP MAX
`2
`
`UNIT
`V/V
`
`Gain
`
`Initial accuracy
`
`IOUTLO
`
`Sink current
`
`IOUT
`
`Source current
`
`IOUT
`
`Sink current
`
`Output voltage swing
`Output voltage swing
`
`VHISENSE = 12 V,
`
`VLOSENSE = 11.9 V,
`VHISENSE = 12 V,
`Differential input to Vds sensing amp = 100 mV
`5 V ≤ VIOUTLO ≤ 13 V
`VIOUT = 0.5 V,
`VIOUTLO = 11.5 V
`VIOUT = 0.05 V, VHISENSE = 12 V,
`VIOUTLO = 12 V
`VHISENSE = 11 V, RIOUT = 10 kΩ
`VHISENSE = 4.5 V, RIOUT = 10 kΩ
`VHISENSE = 3 V, RIOUT = 10 kΩ
`
`LOSENSE
`LOSENSE
`
`High-level input voltage
`Low-level input voltage
`
`194
`
`500
`
`50
`
`0
`0
`0
`2.85
`
`50
`
`60
`
`206
`
`250
`
`2
`1.5
`0.75
`
`2.4
`
`80
`
`62
`
`85
`
`123
`
`mV
`
`nA
`
`µA
`
`µA
`
`V
`V
`V
`V
`V
`
`Ω
`
`67
`
`69
`
`MIN
`1.9
`0.08
`1.85
`
`MIN
`112
`
`95
`
`144
`
`75
`
`dB
`
`TYP MAX
`2.1
`2.35
`0.1
`0.12
`
`UNIT
`V
`V
`V
`
`UNIT
`TYP MAX
`115
`120 %VREF
`10
`mV
`
`MIN
`90
`
`TYP MAX
`100
`110
`100
`
`UNIT
`mV
`nA
`
`VHISENSE = 4.5 V (see Note 3)
`VHISENSE = 4.5 V (see Note 3)
`11.4 V ≤ VHISENSE ≤ 12.6 V,
`LOSENSE connected to HISENSE,
`VHISENSE − VIOUTLO = 0.15 V
`4.5 V ≤ VHISENSE ≤ 5.5 V,
`LOSENSE connected to HISENSE,
`VHISENSE − VIOUTLO = 0.15 V
`3 V ≤ VHISENSE ≤ 3.6 V,
`LOSENSE connected to HISENSE,
`VHISENSE − VIOUTLO = 0.15 V
`VHISENSE = 12.6 V to 3 V,
`VHISENSE − VOUTLO = 100 mV
`NOTE 3. This parameter is ensured by design and is not production tested.
`
`Sample/hold resistance
`
`CMRR
`
`PARAMETER
`
`TEST CONDITIONS
`
`inhibit
`
`Start threshold
`Hysteresis
`Stop threshold
`
`overvoltage protection
`
`PARAMETER
`Overvoltage trip threshold
`Hysteresis
`NOTE 3: This parameter is ensured by design and is not production tested.
`
`TEST CONDITIONS
`
`See Note 3
`
`overcurrent protection
`
`OCP trip threshold
`Input bias current
`
`PARAMETER
`
`TEST CONDITIONS
`
`10
`
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`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1008
`Page 10 of 34
`
`

`

`TPS5210
`PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
`
`SLVS171A − SEPTEMBER 1998 − REVISED MAY 1999
`
`electrical characteristics over recommended operating virtual junction temperature range,
`VCC = 12 V, IDRV = 0 A (unless otherwise noted) (continued)
`deadtime
`
`LOHIB
`LOHIB
`
`PARAMETER
`High-level input voltage
`Low-level input voltage
`High-level input voltage
`Low-level input voltage
`NOTE 3: This parameter is ensured by design and is not production tested.
`
`LOWDR
`LOWDR
`
`LODRV
`
`LODRV
`LODRV
`
`PARAMETER
`High-level input voltage
`Low-level input voltage
`
`TEST CONDITIONS
`
`See Note 3
`See Note 3
`
`TEST CONDITIONS
`
`MIN
`2.4
`
`3
`
`MIN
`1.85
`
`TYP MAX
`
`UNIT
`
`V
`V
`
`V
`V
`
`1.4
`
`1.7
`
`TYP MAX
`
`UNIT
`
`V
`V
`
`0.95
`
`droop compensation
`
`Initial accuracy
`
`drive regulator
`PARAMETER
`Output voltage
`Output regulation
`Short-circuit current
`
`bias regulator
`
`PARAMETER
`
`TEST CONDITIONS
`VDROOP = 50 mV
`
`MIN
`46
`
`TYP MAX
`54
`
`UNIT
`mV
`
`TEST CONDITIONS
`11.4 V ≤ VCC ≤ 12.6 V,
`IDRV = 50 mA
`1 mA ≤ IDRV ≤ 50 mA
`
`MIN
`7
`
`100
`
`TYP MAX
`9
`
`100
`
`UNIT
`V
`mV
`mA
`
`UNIT
`MIN
`TEST CONDITIONS
`PARAMETER
`11.4 V ≤ VCC ≤ 12.6 V,
`V
`6
`See Note 4
`Output voltage
`NOTE 4: The bias regulator is designed to provide a quiet bias supply for the TPS5210 controller. External loads should not be driven by the bias
`regulator.
`
`TYP MAX
`
`input undervoltage lockout
`PARAMETER
`Start threshold
`Hysteresis
`Stop threshold
`
`TEST CONDITIONS
`
`MIN
`9.25
`1.9
`7.5
`
`TYP MAX
`10
`10.75
`2
`2.2
`
`UNIT
`V
`V
`V
`
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`
`11
`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1008
`Page 11 of 34
`
`

`

`TPS5210
`PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
`
`SLVS171A − SEPTEMBER 1998 − REVISED MAY 1999
`
`electrical characteristics over recommended operating virtual junction temperature range,
`VCC = 12 V, IDRV = 0 A (unless otherwise noted) (continued)
`output drivers
`
`TEST CONDITIONS
`tpw < 100 µs,
`Duty cycle < 2%,
`TJ = 125°C,
`VBOOT – VBOOTLO = 6.5 V,
`VHIGHDR = 1.5 V (source) or 6 V (sink),
`See Note 3
`
`MIN
`
`TYP MAX
`
`UNIT
`
`2
`
`2
`
`2
`
`2
`
`A
`A
`
`Ω
`Ω
`
`3
`45
`5.7
`45
`
`PARAMETER
`
`High-side sink
`
`Peak output
`current
`current
`(see Note 5)
`
`High-side source
`
`Low-side sink
`
`Low-side source
`
`Output
`Output
`resistance
`resistance
`(see Note 5)
`(see Note 5)
`
`supply current
`PARAMETER
`Supply voltage
`range
`
`VCC
`
`tpw < 100 µs,
`Duty Cycle < 2%,
`TJ = 125°C,
`VDRV = 6.5 V,
`VLOWDR = 1.5 V (source) or 5 V (sink),
`See Note 3
`TJ = 125°C,
`High-side sink
`VBOOT – VBOOTLO = 6.5 V,
`VBOOT – VBOOTLO = 6.5 V,
`TJ = 125 C,
`VHIGHDR = 6 V (source) or 0.5 V (sink)
`High-side source
`TJ = 125°C,TJ = 125 C,
`
`Low-side sink
`VDRV = 6.5 V,VDRV = 6.5 V,
`
`VLOWDR = 6 V (source) or 0.5 V (sink)
`Low-side source
`NOTES: 3. This parameter is ensured by design and is not production tested.
`5. The pull-up/pull-down circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
`combined current from the bipolar and MOSFET transistors. The output resistance is the Rds(on) of the MOSFET transistor when
`the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
`
`TEST CONDITIONS
`
`MIN
`
`TYP MAX
`
`UNIT
`
`11.4
`
`12
`
`3
`
`5
`
`2
`
`13
`
`10
`
`V
`
`mA
`
`80
`
`µA
`
`mA
`
`VCC
`
`Quiescent
`current
`
`VID code ≠ 11111,
`VINHIBIT = 5 V,
`VBOOTLO = 0 V
`VCC > 10.75 V at startup,
`VID code ≠ 11111,
`VINHIBIT = 5 V,
`VCC > 10.75 V at startup,
`VBOOTLO = 0 V,
`CHIGHDR = 50 pF,
`CLOWDR = 50 pF,
`fSWX = 200 kHz,
`See Note 3
`VINHIBIT = 0 V or VID code = 11111 or VCC < 9.25 V at startup,
`VBOOT = 13 V,
`VBOOTLO = 0 V
`VID code ≠ 11111, VCC > 10.75 V at startup,
`VINHIBIT = 5 V,
`VBOOT = 13 V,
`VBOOTLO = 0 V,
`CHIGHDR = 50 pF,
`fSWX = 200 kHz (see Note 3)
`NOTE 3: This parameter is ensured by design and is not production tested.
`
`High-side
`driver
`driver
`quiescent
`current
`
`12
`
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`
`MICROCHIP TECHNOLOGY INC. EXHIBIT 1008
`Page 12 of 34
`
`

`

`TPS5210
`PROGRAMMABLE SYNCHRONOUS BUCK REGULATOR CONTROLLER
`
`SLVS171A − SEPTEMBER 1998 − REVISED MAY 1999
`
`switching characteristics over recommended operating virtual-junction temperature range,
`VCC = 12 V, IDRV = 0 A (unless otherwise noted)
`PARAMETER
`VSENSE to HIGHDR or
`LOWDR (excluding dead-
`time)
`OCP comparator
`OVP comparator
`PWRGD comparator
`SLOWST comparator
`
`MIN
`
`TYP MAX
`
`UNIT
`
`150
`
`250
`
`1
`1
`1
`560
`
`900
`
`ns
`
`µs
`µs
`
`ns
`
`TEST CONDITIONS
`1.3 V ≤ VVREF ≤ 3.5 V, 10 mV overdrive
`(see Note 3)
`
`See Note 3
`See Note 3
`
`Overdrive = 10 mV (see Note 3)
`CL = 9 nF,
`VBOOT = 6.5 V,
`TJ = 125°C
`VBOOTLO = 0 V,
`CL = 9 nF,
`VDRV = 6.5 V,
`TJ = 125°C
`CL = 9 nF,
`VBOOTLO = 0 V,
`CL = 9 nF,
`TJ = 125°C
`
`VBOOT = 6.5 V,
`TJ = 125°C
`VDRV = 6.5 V,
`
`
`
`Propagation delayPropagation delay
`
`Rise time
`Rise time
`
`Fall time
`Fall time
`
`HIGHDR output
`
`LOWDR output
`
`HIGHDR output
`
`LOWDR output
`
`Deglitch time (Includes
`
`comparator pro