INTEL CORP CUP/PRPHLS)
`
`67E D
`
`•
`
`4826175 0127974 384 •rTL1
`
`infel®
`
`lntel486™ FAMILY OF MICROPROCESSORS
`LOW POWER VERSION
`DATA SHEET
`Low Power lnteI486™ SX CPU/lntel487™ SX MCP
`Low Power lntel486 DX CPU
`■ Lower Power Dissipation
`■ 168-Lead Pin Grid Array for lntel486™ SX
`- Dynamic Frequency Scalability
`Microprocessor
`-
`lcc(max) Reduced to 150 mA at 2 MHz
`■ 196-Lead Plastic Quad Flat Package for
`Improved V cc Rating ( ± 1 Oo/o)
`-
`lntel486™ SX Microprocessor
`■ Binary Compatible with Large Software
`■ 169-Pln Grid Array Package for lntel487™
`Base
`SX Math CoProcessor
`-MS-DOS•, OS/2••, Windows•
`■ High Performance Design
`- UNIX ... System V/386
`-
`lntel486™ One Clock Instruction Core
`-
`IRMX®, IRMK Kernels
`- 16/20/25 MHz Operation for
`■ High Integration Enables On-Chip
`lntel486™ SX
`- 8 KByte Code and Data Cache
`- 25 MHz Operation for lntel486™ DX
`- Floating Point Unit on the lntel486 DX
`- 64 MByte/Sec Burst Bus
`CPU and lntel487™ SX Math
`- CHMOS IV Process Technology
`CoProcessor
`- Dynamic Bus Sizing for 8·, 16- and
`- Paged, Virtual Memory Management
`32-Blt Buses
`■ Easy to Use
`■ Complete 32-Blt Architecture
`- Bullt-ln Self Test
`- Address and Data Buses
`- Hardware Debugging Support
`-Registers
`-
`Intel Software Support
`8-, 16- and 32-Bit Data Types
`-
`- Extensive Third Party Software Support
`■ Multiprocessor Support
`■ 168-Lead Pin Grid Array Package for
`- Multiprocessor Instructions
`lntel486 DX Microprocessor
`- Cache Consistency Protocols
`- Support for Second Level Cache
`The data sheet describes both the Low Power lntel486 SX and the Low Power lntel486 DX microprocessors.
`The lntel487 SX Math CoProcessor will support the low power lnteI486 SX microprocessor as an optional
`upgrade available through the retail channel.
`The Low Power lntel486 family microprocessors meet today's need for high performance portables. Their
`combination of special features like dynamic frequency scaling, lower minimum frequency, improved Vee
`operation and high integration contribute significantly to lower power dissipation and meet the needs of
`portable computing.
`The Low Power capability is achieved by operating the lntel486 microprocessor in the 2X mode. The frequency
`can be varied dynamically between maximum to minimum as needed. The frequency change does not affect
`contents of the registers and data integrity is maintained. Power dissipation is reduced significantly at 2 MHz
`where Ice is only 150 mA compared to 600 mA at 20 MHz. Low power versions are offered for both the
`lntel486 SX and the lntel486 DX microprocessors.
`The Low Power lntel486 microprocessors are 100-percent compatible with all versions of the lntel386™
`microprocessor family, assuring compatibility with the more than $40 billion software base of MS-DOS, Win(cid:173)
`dows, OS/2 and UNIX/System operating system applications. The Low Power lntel486 microprocessor inte(cid:173)
`grates the same RISC-technology, one clock per instruction integer core, on-chip cache, and memory man(cid:173)
`agement unit as the standard lntel486 microprocessor.
`The lntel487 SX Math CoProcessor provides optional math upgrade capability for the lnteI486 SX micro(cid:173)
`processor and supports low power operation; providing end-users increased floating point performance for
`more than 2100 software packages that were designed to use Intel Math CoProcessors. Note that the Intel
`OverDriveTM Processor does not work in systems based on the Low Power lntel486 CPU.
`•MS-DOS and Windows are trademarks of Microsoft Corp .
`.. OS/2 is a trademark of International Business Machines .
`... UNIX is a trademark of UNIX Systems Laboratories.
`
`2-816
`
`December 1992
`Order Number: 241199--002
`
`MICROCHIP TECH. INC. - EXHIBIT 1036
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 001
`
`

`

`INTEL CORP CUP/PRPHLS)
`
`67E D
`
`•
`
`4826175 0127975 21 □ •ITL1
`
`lntel486™ Family of Microprocessors
`Low Power Version
`Data Sheet
`PAGE CONTENTS
`
`CONTENTS
`1.0 INTRODUCTION ................... 2-818
`1.1 Pinout ........................... 2-819
`1.2 Pin Cross Reference
`(lntel486TM DX CPU) .............. 2-824
`1.3 Pin Cross Reference
`(lntel486™ SX CPU) .............. 2-825
`1.4 Pin Cross Reference
`(lntel486™ SX CPU PQFP
`Version) .......................... 2-826
`1.5 Pin Description .................. 2-827
`1.6 Signal Description ............... 2-832
`1. 7 Architecture Overview ........... 2-835
`1.8 Variable CPU Frequency ......... 2-835
`
`PAGE
`
`2.0 D.C./ A.C. SPECIFICATIONS ....... 2-837
`2.1 D.C. Specifications ................. 2-837
`2.2 Power Supply Current vs
`Frequency ........................ 2-840
`2.3 A.C. Specifications .............. 2-840
`
`3.0 MATH UPGRADE FOR LOW
`POWER lntel486™
`MICR~PROCESSOR ................ 2-846
`3.1 Pmout ........................... 2-847
`3.2 Pin Reference of lntel487™ SX
`Math CoProcessor ................ 2-849
`3.3 lntel487™ SX Math CoProcessor
`Pin Description ............... : .... 2-850
`
`4.0 REVISION HISTORY ............... 2-851
`
`El
`
`·N,
`r'}. ·
`
`I
`
`2-817
`
`MICROCHIP TECH. INC. - EXHIBIT 1036
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 002
`
`

`

`INTEL CORP CUP/PRPHLS)
`
`67E D
`
`-
`
`4826175 0127976 157 •ITL1
`
`lntel486™ MICROPROCESSORS
`
`This document should be used In conjunction
`with the lntel486TM DX Microprocessor data
`sheet (order number 240440-004, June 1991) and
`the lntel486™ SX Microprocessor data sheet
`(order number 240950-002, October 1991).
`
`1.0 INTRODUCTION
`
`The Low Power lntel486 microprocessor brings ln(cid:173)
`tel486 technology and performance to the portable
`computer market. The
`low power capability
`is
`achieved by a frequency scalability feature during
`normal operation. The operating frequency can be
`brought down dynamically resulting in lower power
`supply current (lee), This results in minimal power
`dissipation which ensures a longer battery life.
`
`The Low Power lntel486 microprocessor integrates
`the same RISC-technology, one clock per instruc(cid:173)
`tion integer core, on-chip cache, and memory man(cid:173)
`agement unit as the standard lnteI486 microproces(cid:173)
`sor.
`
`The Low Power lntel486 microprocessor has the fol(cid:173)
`lowing special features:
`• Frequency Scalability-This is achieved by op(cid:173)
`erating the lntel486 microprocessor in the 2X
`clock mode. The frequency can be varied dynam(cid:173)
`ically from maximum back to minimum or vice
`versa. The frequency change does not affect the
`register content of the CPU, thus data integrity is
`maintained.
`• Lower Minimum Frequency-The Low Power
`lntel486 microprocessor can be operated at a
`minimum frequency of 2 MHz, at which lec(max)
`is only 150 mA, compared to an lee(max) of 600
`mA at 20 MHz operation. The power dissipation is
`thus drastically reduced ensuring a longer battery
`life.
`• Improved Vee Operation-The Low Power ln(cid:173)
`tel486 microprocessor has an improved Vee rat(cid:173)
`ing of ± 10%. Again this feature makes it ex(cid:173)
`tremely attractive to portable battery powered ap(cid:173)
`plications.
`
`The above three features ensure power savings for
`portable computer systems resulting in prolonged
`battery life.
`
`Besides the above special features, the Low Power
`lntel486 microprocessor has an identical feature set
`to the standard lntel486 CPU. This includes:
`• Binary Compatlbillty-The Low Power lntel486
`CPU is binary compatible with the 8086, 8088,
`80186, 80286, i386TM SX, i386™ DX, lntel486™
`SX and lntel486™ DX CPUs.
`
`2-818
`
`• Full 32-Blt Integer. Processor-The Low Power
`lntel486 CPU performs a complete set of arith(cid:173)
`metic and logical operations on 8-, 16-, and 32-bit
`data types using a full-width ALU and eight gener(cid:173)
`al-purpose registers.
`• Separate 32-Blt Address and Data Paths(cid:173)
`Four gigabytes of physical memory can be ad(cid:173)
`dressed directly.
`• Slngle-Cycle Execution-Many instructions ex(cid:173)
`ecute in a single clock cycle.
`• On-Chip Floating Point Unit-This is available
`on the lntel486 DX CPU. The 32-, 64-, and 80-bit
`formats specified in IEEE standard 754 are sup(cid:173)
`ported. The unit is binary compatible with the
`8087, 80287, i387™, i387™ SX, and lntel487™
`math coprocessors and the lntel486™ CPU.
`• On-Chip Memory Management Unit-Address(cid:173)
`management and memory-space protection
`mechanisms maintain the integrity of memory.
`This is necessary in multitasking and virtual-mem(cid:173)
`ory environments, like those implemented by the
`UNIX and OS/2 operating systems. Both memory
`segmentation and paging are supported.
`• On-Chip Cache with Cache Consistency Sup(cid:173)
`port-The internal write-through cache can hold
`8 KBytes of data or instructions. Cache hits are
`as fast as read accesses to a processor register.
`Bus activity is tracked to detect alterations in the
`memory which internal cache represents. The in(cid:173)
`ternal cache can be invalidated or flushed, so
`that an external cache controller can maintain
`cache consistency in multi-processor environ(cid:173)
`ments.
`• External Cache Control-Write-back and flush
`controls over an external cache are provided so
`that the processor can maintain cache consisten(cid:173)
`cy in multi-processor environments.
`• Instruction Pipelining-The fetching, decoding,
`execution and address translation of instructions
`are overlaped within the Low Power lntel486 mi(cid:173)
`croprocessor. This results in a continuous execu(cid:173)
`tion rate of one clock cycle per instruction, for
`most instructions.
`• Burst Cycles-Burst transfers allow a new dou(cid:173)
`bleword to be read from memory each clock cy(cid:173)
`cle. With this capability the internal cache and in(cid:173)
`struction prefetch buffer can be filled very rapidly.
`• Write Buffers-The processor contains write
`buffers to enhance the performance of consecu(cid:173)
`tive writes to memory. The Low Power lnteI486
`CPU can continue operations internally after a
`write, without waiting for the write to be executed
`on the external bus.
`• Bus Backoff-lf another bus master needs con(cid:173)
`trol of the bus during a Low Power lntel486 micro(cid:173)
`processor initiated bus cycle, the Low Power
`
`I
`
`MICROCHIP TECH. INC. - EXHIBIT 1036
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 003
`
`

`

`INTEL CORP CUP/PRPHLS)
`
`b7E D
`
`-
`
`4826175 0127977 093 •ITL1
`
`lntel486™ MICROPROCESSORS
`
`lntel486 microprocessor will float its bus signals,
`then restart its cycle when the bus becomes avail(cid:173)
`able again.
`• Instruction Reatart-Programs can continue ex(cid:173)
`ecution following an exception generated by an
`
`unsuccessful attempt to access memory. This fea(cid:173)
`ture is important for supporting demand-paged vir(cid:173)
`tual memory applications.
`• Dynamic Bus Sizing-External controllers can
`dynamically alter the effective width of the data
`bus. Bus widths of 8, 16 or 32 bits can be used.
`
`1.1 Plnout
`
`S R Q P N M
`
`L
`
`0
`A27
`
`0
`AZI
`
`0
`A2:S
`
`0
`NC
`
`0
`Al4
`
`2
`
`3
`
`5
`
`6
`
`0
`A:SI
`
`0
`A21
`0
`0
`A25 Vss
`0
`0
`Al7
`
`0
`DO
`0
`A29
`0
`A:SO
`
`0
`02
`
`0
`01
`
`0
`DPO
`
`0
`
`Yss
`0
`
`04
`
`0
`Yss
`
`0
`DI
`
`0
`07
`
`0
`All
`
`0
`A21
`
`Vee
`0
`
`Vss
`0
`All
`0
`
`K
`
`0
`
`Vss
`0
`
`Vee
`0
`
`014
`
`J H G
`
`0
`Yee
`
`0
`05
`
`0
`016
`
`0
`
`Vss
`0
`
`03
`0
`OP2
`
`0
`Vss
`
`0
`Vee
`
`0
`012
`
`f
`
`0
`
`DPI
`0
`D8
`0
`
`015
`
`E D C B A
`
`0
`Vss
`
`0
`Yee
`0
`OTO
`
`0
`
`09
`0
`013
`0
`
`017
`
`0
`011
`
`0
`D18
`
`0
`CLK2
`
`0
`Vee
`
`0
`Vee
`
`0
`D27
`
`0
`D19
`0
`D21
`0
`
`Vss
`0
`
`Vss
`0
`
`Vss
`0
`
`0
`020
`
`0
`D22
`
`0
`CLKSEL
`
`0
`D23
`
`0
`DP3
`
`0
`D24
`
`2
`
`3
`
`4
`
`5
`
`6
`
`El
`
`0
`A24
`
`0
`A22
`
`0
`AZO
`
`0
`All
`
`0
`All
`
`LOW POWER
`168-PIN PGA PINOUT
`lntel486™ DX CPU
`TOP SIDE VIEW
`
`Vee
`0
`Al5
`0
`
`Vee
`0
`
`Vee
`0
`
`Vee
`0
`
`0
`Al
`
`Vee
`0
`0
`0
`Vss Al I A5
`0
`0
`0
`A10
`A7
`Al
`0
`
`0
`PWT
`
`0
`Vee
`
`0
`Vss
`
`0
`BED#
`0
`
`Vee
`0
`
`Vee
`Vee
`0
`0
`Yss
`Yss
`Vss
`P N M L K
`
`0
`ADS•
`
`0
`PCHK#
`
`S R Q
`
`0
`W/R#
`
`0
`v55
`0
`AIZ
`
`0
`Vss
`
`0
`Vss
`
`0
`V55
`
`0
`Vss
`
`0
`Yss
`
`0
`Al
`
`0
`A4
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`I
`
`D25
`0
`Vee
`0
`
`D31
`0
`
`Yee
`0
`NC
`0
`
`Vee
`0
`NC
`0
`NC
`0
`
`0
`v55
`0
`D29
`
`0
`v55
`0
`NC
`
`0
`Vss
`
`0
`NC
`
`0
`NC
`
`0
`NC
`
`0
`D26
`
`0
`028
`
`0
`o:so
`
`0
`NC
`
`0
`NC
`
`0
`NC
`
`0
`NC
`
`0
`FERR#
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`0
`NC
`
`O
`HOLD
`
`O
`IGNN[#
`
`NC
`O
`O
`O
`O
`0
`0
`FLUSH#
`8[2#
`NMI
`A20M#
`KEN#
`BROY#
`0
`0
`0
`0
`0
`0
`0
`0
`0
`Vee ROY# Vee 8S8# RESET NC
`8£1# Vee
`INTR
`0
`0
`0
`0
`0
`0
`0
`0
`0
`PCD
`Vss Vss 8£3# Vss BOFF.9s16# EAOS#AHOLO
`
`___________________ __,
`
`0
`AZ
`
`Vee
`0
`0
`0
`0
`0
`Al BREQ HLDA LOCK# 0/C#
`0
`0
`0
`0
`0
`PLOCK#
`M/10#
`BUST#
`0
`NC
`
`J H G F E D C B A
`241199-1
`
`Figure 1-1. Low Power lntel486™ DX CPU Plnout (Top Side View)
`
`2-819
`
`MICROCHIP TECH. INC. - EXHIBIT 1036
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 004
`
`

`

`INTEL CORP CUP/PRPHLS)
`
`b7E D
`
`-
`
`4826175 0127978 T2T •ITL1
`
`intel®
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`lntel486™ MICROPROCESSORS
`
`A B C D E F G H
`
`J K
`
`L M N
`
`0
`09
`0
`013
`0
`017
`
`0
`Yss
`
`0
`Yee
`
`0
`010
`
`0
`DPI
`0
`08
`0
`015
`
`0
`Yss
`
`0
`Yee
`
`0
`012
`
`0
`
`Yss
`0
`03
`0
`DP2
`
`0
`Vee
`
`0
`05
`
`0
`DIii
`
`0
`
`Vss
`0
`
`Vee
`0
`014
`
`0
`Yss
`
`0
`06
`
`0
`07
`
`0
`
`Yss
`0
`
`Vee
`0
`04
`
`0
`02
`
`0
`DI
`
`0
`DPO
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`0
`020
`
`0
`022
`
`0
`eLKSEL
`
`0
`023
`
`0
`OP3
`
`0
`D24
`
`0
`Yss
`
`0
`029
`
`0
`011
`
`0
`018
`
`0
`CLK2
`
`0
`Vee
`
`0
`Vee
`
`0
`027
`
`0
`026
`
`0
`028
`
`0
`019
`0
`021
`0
`
`Yss
`0
`
`Yss
`0
`
`Vss
`0
`025
`0
`
`Vee
`0
`031
`0
`
`0
`A31
`
`0
`Yss
`
`0
`Al7
`
`0
`A19
`
`0
`A2I
`
`0
`A24
`
`0
`A22
`
`0
`A20
`
`p Q R s
`0
`0
`A27
`DO
`0
`A29
`0
`A30
`
`0
`A29
`0
`A25
`0
`
`Yee
`0
`
`Yss
`0
`Al8
`0
`
`Vee
`0
`A15
`0
`
`0
`A26
`
`0
`A23
`
`0
`NC
`
`0
`A14
`
`0
`Yss
`
`0
`A12
`
`0
`Vss
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`2-820
`
`0
`D30
`
`0
`NC
`
`LOW POWER
`168-PIN PGA PINOUT
`lntel486™ DX CPU
`PIN SIDE VIEW
`
`Vee
`0
`NC
`0
`
`0
`Vss
`
`0
`NC
`
`0
`Yss
`
`0
`NC
`
`0
`NC
`
`0
`NC
`
`0
`IGNNE#
`
`0
`INTR
`
`0
`NC
`
`0
`NC
`
`0
`NC
`
`0
`FERR#
`
`0
`RESET
`
`0
`HOLD
`
`Vee
`0
`NC
`0
`NC
`0
`NC
`0
`0
`0
`FLUSH#
`A20M#
`NMI
`0
`0
`0
`esa• Vee
`NC
`0
`0
`0
`0
`0
`BS16# BOff# V55
`AHOLD
`EADS#
`
`0 w?ii• 0
`Yss
`p
`
`Vee
`0
`
`Vee
`0
`
`Vee
`0
`
`Yee
`0
`A11
`0
`A8
`0
`
`0
`A16
`
`0
`A13
`
`0
`A9
`
`0
`AS
`
`0
`A7
`
`0
`A2
`
`0
`BRED
`
`0
`Yss
`
`0
`Yss
`
`0
`Yss
`
`0
`Vss
`
`0
`A10
`
`0
`Yss
`
`0
`All
`
`0
`A4
`
`0
`PCHK#
`
`0
`ADS#
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`Vee
`0
`A3
`0
`0
`PLOCK#
`BLAST#
`0
`NC
`
`0
`HLDA
`0
`Vee
`
`0
`KEN#
`0
`ROY#
`0
`BE3#
`
`0
`NC
`
`0
`Yee
`
`0
`Yss
`
`0
`BROY#
`0
`
`Vee
`0
`
`Yss
`
`0
`BE2#
`
`0
`BEi#
`
`0
`PCD
`
`0
`BEO#
`0
`
`Yee
`0
`
`Yss
`
`0
`PWT
`
`0
`Vee
`
`0
`Vss
`
`0
`0
`LOCK#
`0/C#
`0
`
`0
`M/10#
`
`Vee
`
`Yss
`
`A B C D E F G H
`
`J K
`
`L M N
`
`Q R s
`
`241199-2
`
`Figure 1-2. Low Power lntel486™ DX CPU Pinout (Pin Side View)
`
`I
`
`MICROCHIP TECH. INC. - EXHIBIT 1036
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 005
`
`

`

`INTEL CORP CUP/PRPHLS)
`
`67E D
`
`•
`
`4826175 0127979 966 •ITL1
`
`lntel486™ MICROPROCESSORS
`
`s R Q
`
`p N M
`
`L K
`
`J H G
`
`f"
`
`E D C B A
`
`0
`DO
`0
`A29
`0
`A30
`
`0
`D2
`
`0
`01
`
`0
`DPO
`
`0
`
`V55
`0
`
`Vee
`0
`04
`
`0
`V55
`
`0
`D8
`
`0
`07
`
`0
`
`V55
`0
`
`Vee
`0
`014
`
`0
`Vee
`
`0
`D5
`
`0
`018
`
`0
`
`V55
`0
`D3
`0
`DP2
`
`0
`Vss
`
`0
`Vee
`
`0
`D12
`
`0
`DP1
`0
`D11
`0
`D15
`
`0
`V55
`
`0
`Vee
`
`0
`D10
`
`0
`D9
`0
`D13
`0
`017
`
`t
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`0
`A31
`
`0
`Vss
`
`0
`A17
`
`0
`A19
`
`0
`A2I
`
`0
`A24
`
`0
`A22
`
`0
`A27
`
`0
`A28
`
`0
`A23
`
`0
`NC
`
`,.,,
`
`0
`
`0
`Yss
`
`0
`Al2
`
`0
`A2II
`0
`A25
`0
`
`Vee
`0
`
`Vss
`0
`AUi
`0
`
`Vee
`0
`A15
`0
`
`0
`011
`
`0
`018
`
`0
`CLK2
`
`0
`Vee
`
`0
`Vee
`
`0
`D27
`
`0
`D28
`
`0
`D19
`0
`D21
`0
`
`Vss
`0
`
`Vss
`0
`
`Vss
`0
`D25
`0
`
`0
`020
`
`0
`D22
`
`0
`CLKSEL
`
`0
`D23
`
`0
`OP3
`
`0
`D24
`
`0
`Vss
`
`0
`D29
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`0
`A20
`
`0
`Al&
`
`0
`A13
`
`0
`A9
`
`0
`AS
`
`0
`A7
`
`0
`A2
`
`Vee
`0
`
`Vee
`0
`
`Vee
`0
`
`Yee
`0
`A11
`0
`All
`0
`
`0
`BREO
`
`0
`HLDA
`0
`
`Vee
`0
`A3
`0
`0
`PLOCK•
`BLAST#
`0
`0
`0
`ADS#
`PCHK#
`NC
`s R Q
`
`Vee
`
`0
`LOCK#
`
`0
`M/10#
`
`0
`D/C•
`0
`
`Vee
`
`0
`BED#
`0
`
`Vee
`0
`
`0
`PWT
`
`0
`Vee
`
`0
`Vss
`
`Vss
`L K
`
`0
`BE2#
`
`0
`9E1#
`
`0
`PCD
`
`0
`BROY#
`0
`
`Vee
`0
`
`Vss
`
`0
`NC
`
`0
`Vee
`
`0
`Vss
`
`0
`KEN#
`0
`ROY#
`0
`9E3#
`
`J H G
`
`f"
`
`0 w?ii• 0
`V55
`Vss
`p N M
`
`0
`Vss
`
`0
`V55
`
`0
`V55
`
`0
`Vss
`
`0
`Yss
`
`0
`A10
`
`0
`V55
`
`0
`A8
`
`0
`
`,.,
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`I
`
`LOW POWER
`168-PIN PGA PINOUT
`lntel486TM SX CPU
`TOP SIDE VIEW
`
`0
`D28
`
`0
`D30
`
`0
`NC
`
`Vee
`0
`D31
`0
`
`Vee
`0
`NC
`0
`
`0
`Vss
`
`0
`NC
`
`0
`Vss
`
`0
`NC
`
`0
`NC
`
`0
`NC
`
`0
`NMI
`
`0
`INTR
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`0
`NC
`
`0
`NC
`
`0
`NC
`
`0
`NC
`
`0
`HOLD
`
`Vee
`0
`NC
`0
`NC
`0
`NC
`0
`0
`0
`FLUSH#
`A20M#
`NC
`0
`0
`0
`0
`Vee 858# RESET
`NC
`0
`0
`0
`0
`0
`Vss BOfF• 8516#
`AHOLD
`EADS#
`
`E D C B A
`241199-3
`
`Figure 1-3. Low Power lntel486™ SX CPU Plnout (Top Side View)
`
`2-821
`
`MICROCHIP TECH. INC. - EXHIBIT 1036
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 006
`
`

`

`INTEL CORP CUP/PRPHLS>
`
`b7E D
`
`-
`
`4826175 0127980 b88 •rTL1
`
`lntel486TM MICROPROCESSORS
`
`A B C D E
`
`f' G H
`
`J K
`
`L M N
`
`1
`
`2
`
`3
`
`-4
`
`5
`
`6
`
`7
`
`8
`
`0
`020
`
`0
`D22
`
`0
`CLKSEL
`
`0
`023
`
`0
`DP3
`
`0
`D24
`
`0
`Vss
`
`0
`029
`
`0
`019
`0
`021
`0
`
`Vss
`0
`
`Vss
`0
`
`Vss
`0
`D25
`0
`
`Vee
`0
`031
`0
`
`0
`011
`
`0
`D18
`
`0
`CLK2
`
`0
`09
`0
`013
`0
`017
`
`0
`Vss
`
`0
`Vee
`
`0
`D10
`
`0
`DP1
`0
`oe
`0
`D15
`
`0
`Vss
`
`0
`Vee
`
`0
`012
`
`0
`
`Vss
`0
`D3
`0
`DP2
`
`0
`Vee
`
`0
`05
`
`0
`D16
`
`0
`
`Vss
`0
`
`Vee
`0
`014
`
`0
`Vss
`
`0
`06
`
`0
`D7
`
`0
`
`Vss
`0
`
`v<X:
`0
`D4
`
`0
`02
`
`0
`D1
`
`0
`DPO
`
`0
`Vee
`
`0
`Vee
`
`0
`027
`
`0
`D26
`
`0
`028
`
`p Q R s
`0
`0
`0
`A3I
`A27
`A28
`0
`A25
`0
`
`0
`DO
`0
`A29
`0
`A3O
`
`0
`Vss
`
`0
`A17
`
`0
`A19
`
`0
`A2I
`
`0
`A24
`
`0
`A22
`
`0
`A2O
`
`1
`
`2
`
`3
`
`-4
`
`5
`
`6
`
`7
`
`8
`
`0
`A26
`
`0
`A23
`
`0
`NC
`
`0
`A14
`
`0
`Vss
`
`0
`A12
`
`0
`V55
`
`Vee
`0
`
`Vss
`0
`A18
`0
`
`Vee
`0
`AIS
`0
`
`Vee
`0
`
`9
`
`10
`
`11
`
`12
`
`13
`
`1-4
`
`15
`
`16
`
`17
`
`2-822
`
`0
`D30
`
`0
`NC
`
`LOW POWER
`168-PIN PGA PINOUT
`lntel486TM SX CPU
`PIN SIDE VIEW
`
`Vee
`0
`NC
`0
`
`0
`V55
`
`0
`NC
`
`0
`Vss
`
`0
`NC
`
`0
`NC
`
`0
`NC
`
`0
`NMI
`
`0
`INTR
`
`0
`NC
`
`0
`NC
`
`0
`NC
`
`0
`NC
`
`0
`RESET
`
`0
`HOLD
`
`Vee
`0
`NC
`0
`NC
`0
`NC
`0
`0
`0
`FLUSH•
`A2OM#
`NC
`0
`0
`0
`asa• Vee
`NC
`0
`0
`0
`0
`0
`BS16#
`AHOLD
`BOFF# Vss
`EADS#
`
`Vee
`0
`
`Vee
`0
`
`Vee
`0
`A11
`0
`AB
`0
`
`0
`All
`
`0
`A13
`
`0
`A9
`
`0
`AS
`
`0
`A7
`
`0
`A2
`
`0
`BREQ
`
`0
`Vss
`
`0
`Vss
`
`0
`Vss
`
`0
`Vss
`
`0
`A10
`
`0
`Vss
`
`0
`A8
`
`0
`A4
`
`0
`PCHK#
`
`0
`ADS#
`
`Vee
`0
`A3
`0
`0
`PLOCK#
`BLAST#
`0
`NC
`
`9
`
`10
`
`11
`
`12
`
`13
`
`1-4
`
`15
`
`16
`
`17
`
`0
`KEN#
`0
`ROY#
`0
`8[3#
`
`0
`NC
`
`0
`Vee
`
`0
`V55
`
`0
`BROY#
`0
`
`Vee
`0
`
`Vss
`
`0
`8[2#
`
`0
`8[1#
`
`0
`PCD
`
`0
`BEO#
`0
`
`Vee
`0
`
`Vss
`
`0
`PWT
`
`0
`Vee
`
`0
`Vss
`
`0
`0
`LOCK#
`D/C#
`0
`
`0
`M/10#
`
`v<X:
`0
`
`Vss
`
`w?R#
`
`0
`HLDA
`0
`Vee
`0
`
`Vss
`
`A B C D E
`
`F G H
`
`J K
`
`L M N
`
`p Q R s
`
`241199-4
`
`Figure 1-4. Low Power lnteI486™ SX CPU Plnout (Pin Side View)
`
`I
`
`MICROCHIP TECH. INC. - EXHIBIT 1036
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 007
`
`

`

`INTEL CORP CUP/PRPHLS)
`
`b7E D
`
`•
`
`4826175 0127981 514 •ITL1
`
`lntel486™ MICROPROCESSORS
`
`Low Power lntel486TM SX CPU
`PIHtlc Quad Flat Package (PQFP)
`(Top View)
`
`~S~i~2¥iJ;~~,~¥~1!~i~aj¥~~~~¥~§~¥i1¥J¥¥¥~¥¥~¥f~¥1
`241199-14
`
`Figure 1-5. Low Power lntel486™ SX CPU 196-Lead PQFP Plnout
`
`I
`
`2-823
`
`MICROCHIP TECH. INC. - EXHIBIT 1036
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 008
`
`

`

`INTEL CORP CUP/PRPHLS)
`
`b7E D
`
`•
`
`4826175 0127982 450 •rTL1
`
`lntel486™ MICROPROCESSORS
`
`A2
`A3
`~
`As
`As
`A7
`As
`Ag
`A10
`A11
`A12
`A13
`A14
`A15
`A1e
`A17
`A1e
`A19
`A20
`A21
`A22
`A23
`A24
`A25
`A2s
`A27
`A2e
`A29
`A30
`A31
`
`1.2 Pin Cross Reference (lntel486™ DX CPU)
`Data
`Control
`Address
`014
`A20M#
`R15
`ADS#
`S16
`AHOLD
`012
`BEO#
`S15
`BE1#
`013
`BE2#
`R13
`BE3#
`011
`BLAST#
`S13
`BOFF#
`BROY#
`R12
`S7
`BREO
`010
`858#
`8516#
`55
`R7
`CLK2
`09
`CLKSEL
`03
`DIC#
`RS
`DPO
`04
`DP1
`DP2
`08
`DP3
`05
`EADS#
`07
`FERR#
`53
`FLUSH#
`06
`R2
`HLDA
`S2
`HOLD
`IGNNE#
`S1
`INTR
`R1
`KEN#
`P2
`LOCK#
`P3
`M/10#
`01
`NMI
`PCD
`PCHK#
`PWT
`PLOCK#
`ROY#
`RESET
`W/R#
`
`Do
`D1
`D2
`~
`04
`D5
`D5
`07
`De
`D9
`010
`011
`012
`013
`014
`D15
`015
`017
`019
`D19
`D20
`D21
`D22
`D23
`024
`D25
`D2s
`D27
`D2e
`D29
`030
`D31
`
`P1
`N2
`N1
`H2
`M3
`J2
`L2
`L3
`F2
`01
`E3
`C1
`G3
`02
`K3
`F3
`J3
`03
`C2
`81
`A1
`82
`A2
`A4
`AS
`86
`C7
`C6
`C8
`AS
`C9
`88
`
`N/C
`A10
`A12
`A13
`A14
`810
`812
`813
`814
`816
`C10
`C11
`C12
`C13
`G15
`R17
`54
`
`Yee
`87
`89
`811
`C4
`cs
`E2
`E16
`G2
`G16
`H16
`J1
`K2
`K16
`L16
`M2
`M16
`P16
`R3
`RS
`RB
`R9
`R10
`R11
`R14
`
`Yss
`A7
`A9
`A11
`83
`84
`85
`E1
`E17
`G1
`G17
`H1
`H17
`K1
`K17
`L1
`L17
`M1
`M17
`P17
`02
`R4
`S6
`S8
`S9
`StO
`S11
`S12
`S14
`
`015
`S17
`A17
`K15
`J16
`J15
`F17
`R16
`017
`H15
`015
`016
`C17
`C3
`A3
`M15
`N3
`F1
`H3
`AS
`817
`C14
`C15
`P15
`E15
`A15
`A16
`F15
`N15
`N16
`815
`J17
`017
`L15
`016
`F16
`C16
`N17
`
`2-824
`
`I
`
`MICROCHIP TECH. INC. - EXHIBIT 1036
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 009
`
`

`

`INTEL CORP CUP/PRPHLS)
`
`67E D
`
`-
`
`4826175 0127983 397 •ITL1
`
`A2
`A3
`A.t
`As
`As
`A7
`As
`A9
`A10
`A11
`A12
`A13
`A14
`Ats
`Ate
`A17
`A1e
`A19
`A20
`A21
`A22
`A23
`A24
`A2s
`A2s
`A27
`A2e
`A29
`A30
`A31
`
`1.3 Pin Cross Reference (lntel486™ SX CPU)
`Address
`Data
`Control
`014
`A20M#
`R15
`ADS#
`S16
`AHOLD
`012
`BEO#
`S15
`BE1#
`013
`8E2#
`R13
`8E3#
`011
`t BLAST#
`S13
`BOFF#
`R12
`BADY#
`S7
`8REO
`8S8#
`010
`8S16#
`S5
`R7
`CLK2
`09
`CLKSEL
`0/C#
`03
`RS
`DPO
`DP1
`04
`08
`DP2
`05
`DP3
`07
`EADS#
`FLUSH#
`S3
`HLDA
`Q6
`R2
`HOLD
`S2
`INTR
`KEN#
`S1
`LOCK#
`R1
`M/10#
`P2
`P3
`NMI
`01
`PCD
`PCHK#
`PWT
`PLOCK#
`ROY#
`RESET
`W/R#
`
`Do
`Dt
`D2
`D3
`D4
`Ds
`De
`~
`Da
`09
`D10
`D11
`D12
`013
`014
`015
`D1e
`017
`D1e
`D19
`020
`D21
`D22
`D23
`024
`025
`D2e
`027
`D2e
`029
`D30
`D31
`
`P1
`N2
`N1
`H2
`M3
`J2
`L2
`L3
`F2
`01
`E3
`C1
`G3
`02
`K3
`F3
`J3
`D3
`C2
`81
`A1
`82
`A2
`A4
`A6
`86
`C7
`C6
`ca
`A8
`C9
`88
`
`lntel486™ MICROPROCESSORS
`
`N/C
`A10
`A12
`A13
`A14
`810
`812
`813
`814
`815
`816
`C10
`C11
`C12
`C13
`C14
`G15
`R17
`S4
`
`Vee
`87
`89
`811
`C4
`C5
`E2
`E16
`G2
`G16
`H16
`J1
`K2
`K16
`L16
`M2
`M16
`P16
`R3
`R6
`R8
`R9
`R10
`R11
`R14
`
`Vss
`A7
`A9
`A11
`83
`84
`85
`E1
`E17
`G1
`G17
`H1
`H17
`K1
`K17
`L1
`L17
`M1
`M17
`P17
`02
`R4
`56
`S8
`S9
`S10
`S11
`S12
`S14
`
`D15
`S17
`A17
`K15
`J16
`J15
`F17
`R16
`017
`H15
`015
`D16
`C17
`C3
`A3
`M15
`N3
`F1
`H3
`AS
`817
`C15
`P15
`E15
`A16
`F15
`N15
`N16
`815
`J17
`017
`L15
`016
`F16
`C16
`N17
`
`I
`
`2-825
`
`MICROCHIP TECH. INC. - EXHIBIT 1036
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 010
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`

`

`INTEL CORP CUP/PRPHLS)
`
`67E D
`
`•
`
`4826175 0127984 223 •ITL1
`
`lntel486™ MICROPROCESSORS
`
`infel.
`
`Vee
`6
`19
`24
`28
`36
`49
`54
`62
`70
`84
`93
`98
`107
`112
`119
`125
`131
`147
`164
`170
`175
`179
`184
`196
`
`Vss
`1
`11
`21
`22
`33
`40
`50
`58
`66
`86
`95
`96
`99
`109
`114
`121
`126
`141
`148
`167
`168
`177
`182
`194
`
`Do
`D1
`02
`D3
`04
`05
`05
`07
`De
`Og
`010
`011
`012
`013
`D14
`015
`D15
`D17
`D1e
`D19
`D20
`021
`022
`023
`D24
`025
`025
`027
`D2e
`D29
`D30
`D31
`
`17
`18
`20
`23
`25
`26
`27
`29
`31
`32
`35
`37
`38
`39
`41
`42
`44
`45
`46
`47
`48
`51
`53
`55
`59
`61
`63
`65
`67
`69
`71
`74
`
`1.4 Pin Cross Reference by Signal Type (lntel486™ SX PQFP CPU)
`Address
`N/C
`Control
`Data
`146
`A20M#
`15
`A2
`ADS#
`150
`A3
`34
`152
`AHOLD
`52
`~
`BEO#
`154
`As
`56
`· BE1#
`As
`158
`60
`BE2#
`159
`64
`A7
`BE3#
`As
`161
`68
`Ag
`163
`BLAST#
`72
`165
`BOFF#
`73
`A10
`BROY#
`172
`75
`A11
`174
`BREQ
`76
`A12
`176
`8S8#
`A13
`77
`178
`BS16#
`78
`A14
`180
`CLK2
`79
`A15
`181
`CLKSEL
`81
`A1e
`183
`82
`DIC#
`A17
`189
`DPO
`83
`A1e
`191
`DP1
`85
`A19
`193
`DP2
`87
`A20
`2
`DP3
`A21
`88
`EADS#
`89
`3
`A22
`4
`FLUSH#
`90
`A23
`5
`HLDA
`91
`A24
`7
`HOLD
`92
`A25
`8
`INTR
`94
`A25
`KEN#
`9
`97
`A27
`10
`LOCK#
`124
`A2e
`M/10#
`12
`134
`A29
`13
`NMI
`140
`A30
`14
`PCD
`149
`A31
`PCHK#
`151
`PWT
`153
`PLOCK#
`155
`ROY#
`157
`RESET
`160
`TCK
`162
`TOI
`166
`166
`TOO
`TMS
`169
`UP#
`171
`W/R#
`173
`186
`188
`190
`192
`195
`
`104
`145
`129
`117
`116
`115
`113
`' 144
`137
`138
`118
`135
`136
`123
`127
`110
`16
`30
`43
`57
`105
`102
`122
`130
`101
`132
`142
`111
`100
`106
`139
`108
`143
`133
`103
`128
`185
`80
`187
`156
`120
`
`2-826
`
`I
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`MICROCHIP TECH. INC. - EXHIBIT 1036
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 011
`
`

`

`INTEL CORP CUP/PRPHLS)
`
`67E])
`
`•
`
`4826175 □ 127985 16T •ITL1
`
`lntel486™ MICROPROCESSORS
`
`1.5 Pin Description
`
`The following table provides brief pin descriptions.
`
`Symbol
`
`Type
`
`CLK2
`
`CLKSEL
`
`I
`
`I
`
`Name and Function
`CLK2 provides the fundamental timing for the Low Power lntel486 microprocessor.
`This is twice the internal frequency of the CPU.
`
`Clock Select pin selects the 2X mode required for the Low Power lntel486 CPU. A well
`defined pulse on this pin establishes the phase relationship of the 2X clock. With the
`exception of a pulse during cold reset, this pin should be driven low all the time and
`must be free of spikes or glitches.
`
`A31-A4
`A3-A2
`
`ADDRESS BUS
`1/0 A31-A2 are the address lines of the microprocessor. A31-A2, together with the byte
`enables SEO# -BE3#, define the physical area of memory or input/output space
`0
`accessed. Address lines A31-A4 are used to drive addresses into the microprocessor
`to perform cache line invalidations. Input signals must meet setup and hold times t22
`and t23. A31-A2 are not driven during bus or address hold.
`
`BE0-3#
`
`0
`
`DATA BUS
`
`D31-DO
`
`1/0
`
`DATA PARITY
`
`The byte enable signals indicate active bytes during read and write cycles. During the
`first cycle of a cache fill, the external system should assume that all byte enables are
`active. BE3# applies to 024-031, BE2# applies to 016-023, BE1 # applies to 08-
`015 and BEO# applies to 00-07. BEO#-BE3# are active LOW and are not driven
`during bus hold.
`
`These are the data lines for the Low Power lntel486 micrprocessor. Lines 00-07
`define the least significant byte of the data bus while lines 024-031 define the most
`significant byte of the data bus. These signals must meet setup and hold times t22 and
`t23 for proper operation on reads. These pins are driven during the second and
`subsequent clocks of write cycles.
`
`OPO-DP3
`
`1/0 There is one data parity pin for each byte of the data bus. Data parity is generated on
`all write data cycles with the same timing as the data driven by the Low Power lntel486
`microprocessor. Even parity information must be driven back into the microprocessor
`on the data parity pins with the same timing as read information to insure that the
`correct parity check status is indicated by the Low Power lntel486 microprocessor. The
`signals read on these pins do not affect program execution. Input signals must meet
`setup and hold times t22 and t23. DPO-DP3 should be connected to Vee through a
`pullup resistor in systems which do not use parity. DPO-DP3 are active HIGH and are
`driven during the second and subsequent clocks of write cycles.
`
`PCHK#
`
`0
`
`Parity Status is driven on the PCHK# pin the clock after ready for read operations.
`The parity status is for data sampled at the end of the previous clock. A parity error is
`indicated by PCHK # being LOW. Parity status is only checked for enabled bytes as
`indicated by the byte enable and bus size signals. PCHK # is valid only in the clock
`immediately after read data is returned to the microprocessor. At all other times
`PCHK # is inactive (HIGH). PCHK # is never floated.
`
`I
`
`2-827
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`MICROCHIP TECH. INC. - EXHIBIT 1036
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 012
`
`

`

`INTEL CORP CUP/PRPHLS)
`
`67E D
`
`•
`
`4826175 0127986 OT6 •ITL1
`
`lntel486™ MICROPROCESSORS
`
`1.5 Pin Description (Continued)
`Symbol Type
`
`BUS CYCLE DEFINITION
`
`Name and Function
`
`M/I0#
`DIC#
`W/R#
`
`0
`0
`0
`
`The memory/Input-output, data/control and write/read lines are the primary
`bus definitions signals. These signals are driven valid as the ADS# signal is asserted.
`
`M/10# 0/C# W/R#
`
`Bus Cycle Initiated
`
`0
`0
`0
`0
`1
`1
`1
`1
`
`0
`0
`1
`1
`0
`0
`1
`1
`
`0
`1
`0
`1
`0
`1
`0
`1
`
`Interrupt Acknowledge
`Halt/Special Cycle
`1/0 Read
`I/0Write
`Code Read
`Reserved
`Memory Read
`Memory Write
`
`LOCK#
`
`0
`
`PLOCK#
`
`0
`
`BUS CONTROL
`
`ADS#
`
`ROY#
`
`0
`
`I
`
`The bus definition signals are not driven during bus hold and follow the timing of the
`address bus.
`The bus lock pin indicates that the current bus cycle is locked. The Low Power lntel486
`microprocessor will not allow a bus hold when LOCK# is asserted (but address holds
`are allowed). LOCK# goes active in the first clock of the first locked bus cycle and goes
`inactive after the last clock of the last locked bus cycle. The last locked cycle ends
`when ready is returned. LOCK# is active LOW and is not driven during bus hold. Locked
`read cycles will not be transformed into cache fill cycles if KEN # is returned active.
`
`The pseudo-lock# pin indicates that the current bus transaction requires more than
`one bus cycle to complete. Examples of such operations are segment table reads (64
`bits), cache line fills (128 bits). The Low Power lntel486 microprocessor will drive
`PLOCK# active until the addresses for the last bus cycle of the transaction have been
`driven regardless of whether ROY# or BADY# have been returned.
`Normally PLOCK# and BLAST# are inverse of each other. PLOCK# is a function of
`the 8S8 #, BS 16 # and KEN# inputs. PLOCK# should be sampled only if the clock
`ready is returned. PLOCK# is active LOW and is not driven during bus hold.
`
`The address status output indicates that a valid bus cycle definition and address are
`available on the cycle definition lines and address bus. ADS# is driven active in the
`same clock as the addresses are driven. ADS# is active LOW and is not driven during
`bus hold.
`The non-burst Ready input indicates that the current bus cycle is complete. ADY#
`indicates that the external system has presented valid data in response to a read or that
`the external system has accepted data in response to a write. ROY# is ignored when
`the bus is idle and at the end of the first clock in a bus cycle.
`ROY# is active during address hold. Data can be returned to tne processor while
`AHOLD is active. ROY# is active LOW and is provided with a small pullup resistor.
`ROY# must satisfy the setup and hold times t16 and t17 for proper chip operation.
`
`2-828
`
`I
`
`MICROCHIP TECH. INC. - EXHIBIT 1036
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 013
`
`

`

`INTEL CORP (UP/PRPHLS)
`
`67E D
`
`•
`
`4826175 0127987 T32 •ITL1
`
`lntel486™ MICROPROCESSORS
`
`1.5 Pin Description (Continued)
`Symbol Type
`
`BURST CONTROL
`
`Name and Function
`
`BROY#
`
`I
`
`BLAST#
`
`0
`
`INTERRUPTS
`
`RESET
`
`I
`
`INTR
`
`I
`
`NMI
`
`I
`
`The burst ready input performs the same function during a burst cycle that ROY#
`performs during a non-burst cycle. BROY# indicates that the external system has
`presented valid data in response to a read for that the external system has accepted
`data in response to a write. BROY# is ignored when the bus is idle and at the end of the
`first clock in a bus cycle. BROY# is sampled in the second and subsequent clocks of a
`burst cycle. The data presented on the data bus will be strobed into the microprocessor
`when BROY# is sampled active. If ROY# is returned simultaneously with BROY#,
`BADY# is ignored and the burst cycle is prematurely aborted. BADY# is active LOW
`and is provided with a small pullup resistor. BROY# must satisfy the setup and hold
`times t1s and t17.
`
`The burst last signal indicates that the next time BROY# is returned the burst bus cycle
`is complete. BLAST# is active for both burst and non-burst bus cycles. BLAST# is
`active LOW and is not driven during bus hold.
`
`The reset input forces the Low Power lntel486 microprocessor to begin execution at a
`known state. The microprocessor cannot begin execution of instructions until at least
`1 ms after Vee and CLK2 have reached their proper D.C. and A.G. specifications.
`The RESET pin should remain active during this time to insure proper microprocessor
`operation. However, for warm boot-ups RESET should remain active for at least 30
`CLK2 periods. RESET is active HIGH. RESET is asynchronous but must meet setup and
`hold times t20 and 121 for recognition in any specific clock.
`The maskable interrupt indicates that an external interrupt has been generated. If the
`internal interrupt flag is set in EFLAGS, active interrupt processing will be initiated. The
`Low Power lntel486 microprocessor will generate two locked interrupt acknowledge bus