G522-0330-00
`
`MPC604EUM/AD
`3/98
`
`PowerPC 604e™
`
`RISC Microprocessor User's Manual
`with Supplement for PowerPC 604™ Microprocessor
`
`™
`
`MICROCHIP TECH. INC. - EXHIBIT 1025
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 001
`
`

`

`.
`
`This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
`Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or
`implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this
`document.
`
`The PowerPC 604e microprocessor embodies the intellectual property of IBM and of Motorola. However, neither party assumes any responsibility or
`liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party. Neither party is to be
`considered an agent or representative of the other party, and neither has granted any right or authority to the other to assume or create any express or
`implied obligations on its behalf. Information such as data sheets, as well as sales terms and conditions such as prices, schedules, and support, for the
`microprocessor may vary as between IBM and Motorola. Accordingly, customers wishing to learn more information about the products as marketed by a
`given party should contact that party.
`Both IBM and Motorola reserve the right to modify this manual and/or any of the products as described herein without further notice. Nothing in this
`manual, nor in any of the errata sheets, data sheets, and other supporting documentation, shall be interpreted as conveying an express or implied
`warranty, representation, or guarantee regarding the suitability of the products for any particular purpose. The parties do not assume any liability or
`obligation for damages of any kind arising out of the application or use of these materials. Any warranty or other obligations as to the products described
`herein shall be undertaken solely by the marketing party to the customer, under a separate sale agreement between the marketing party and the customer.
`In the absence of such an agreement, no liability is assumed by the marketing party for any damages, actual or otherwise.
`“Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals,” must be validated for each customer
`application by customer’s technical experts. Neither IBM nor Motorola convey any license under their respective intellectual property rights nor the rights
`of others. The products described in this manual are not designed, intended, or authorized for use as components in systems intended for surgical implant
`into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation
`where personal injury or death may occur. Should customer purchase or use the products for any such unintended or unauthorized application, customer
`shall indemnify and hold IBM and Motorola and their respective officers, employees, subsidiaries, affiliates, and distributors harmless against all claims,
`costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with
`such unintended or unauthorized use, even if such claim alleges that Motorola or IBM was negligent regarding the design or manufacture of the part.
`
` are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
`Motorola and
`The PowerPC name, the PowerPC logotype, PowerPC 601, PowerPC 603, PowerPC 603e, PowerPC 604, and PowerPC 604e are trademarks of
`International Business Machines Corporation used by Motorola under license from International Business Machines Corporation.
`
`© Motorola Inc. 1998. All rights reserved.
`Portions hereof © International Business Machines Corp. 1991–1998. All rights reserved.
`
`MICROCHIP TECH. INC. - EXHIBIT 1025
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`

`Paragraph
`Number
`
`CONTENTS
`
`Title
`
`About This Book
`
`Page
`Number
`
`Audience ............................................................................................................ xxiv
`Organization.........................................................................................................xxv
`Suggested Reading............................................................................................. xxvi
`General Information xxvi
`PowerPC Documentation xxvi
`Conventions ..................................................................................................... xxviii
`Acronyms and Abbreviations ............................................................................ xxix
`Terminology Conventions ................................................................................ xxxii
`
`Chapter 1
`Overview
`
`Overview.............................................................................................................. 1-1
`PowerPC 604e Microprocessor Features ............................................................. 1-2
`PowerPC Architecture Implementation ............................................................... 1-8
`Features............................................................................................................ 1-9
`PowerPC 604e Processor Programming Model............................................. 1-10
`Implementation-Specific Registers............................................................ 1-10
`Support for Misaligned Little-Endian Accesses.................................... 1-12
`Instruction Set............................................................................................ 1-13
`Cache and Bus Interface Unit Operation ....................................................... 1-14
`Instruction Cache ....................................................................................... 1-14
`Data Cache................................................................................................. 1-15
`Additional Changes to the Cache .............................................................. 1-15
`Exceptions...................................................................................................... 1-16
`Memory Management.................................................................................... 1-21
`Instruction Timing ......................................................................................... 1-21
`Signal Descriptions ........................................................................................ 1-24
`System Interface Operation .......................................................................... 1-27
`Performance Monitor..................................................................................... 1-28
`
`Chapter 2
`Programming Model
`
`Register Set .......................................................................................................... 2-1
`Register Set ...................................................................................................... 2-2
`PowerPC 604e-Specific Registers ................................................................... 2-8
`Instruction Address Breakpoint Register (IABR)........................................ 2-9
`
`iii
`
`1.1
`1.2
`1.3
`1.3.1
`1.3.2
`1.3.2.1
`1.3.2.2
`1.3.2.3
`1.3.3
`1.3.3.1
`1.3.3.2
`1.3.3.3
`1.3.4
`1.3.5
`1.3.6
`1.3.7
`1.3.8
`1.3.9
`
`2.1
`2.1.1
`2.1.2
`2.1.2.1
`
`Contents
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`MICROCHIP TECH. INC. - EXHIBIT 1025
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`Number
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`2.1.2.2
`2.1.2.3
`2.1.2.4
`2.1.2.5
`2.1.2.5.1
`2.1.2.5.2
`2.1.2.5.3
`2.1.2.5.4
`2.1.2.5.5
`2.1.3
`2.2
`2.2.1
`2.2.2
`2.2.3
`2.2.4
`2.2.5
`2.2.6
`2.3
`2.3.1
`2.3.1.1
`2.3.1.2
`2.3.1.3
`2.3.1.4
`2.3.2
`2.3.2.1
`2.3.2.2
`2.3.2.3
`2.3.2.4
`2.3.2.4.1
`2.3.2.4.2
`2.3.2.4.3
`2.3.3
`2.3.4
`2.3.4.1
`2.3.4.1.1
`2.3.4.1.2
`2.3.4.1.3
`2.3.4.1.4
`2.3.4.2
`2.3.4.2.1
`2.3.4.2.2
`2.3.4.2.3
`2.3.4.2.4
`
`iv
`
`Processor Identification Register (PIR) ....................................................... 2-9
`Hardware Implementation-Dependent Register 0 ..................................... 2-10
`Hardware Implementation-Dependent Register 1 (HID1) ........................ 2-12
`Performance Monitor Registers................................................................. 2-12
`Monitor Mode Control Register 0 (MMCR0) ....................................... 2-13
`Monitor Mode Control Register 1—MMCR1....................................... 2-14
`Performance Monitor Counter Registers (PMC1–PMC4) .................... 2-15
`Sampled Instruction Address Register (SIA) ........................................ 2-20
`Sampled Data Address Register (SDA)................................................. 2-21
`Reset Settings................................................................................................. 2-21
`Operand Conventions......................................................................................... 2-22
`Floating-Point Execution Models—UISA..................................................... 2-22
`Data Organization in Memory and Data Transfers........................................ 2-23
`Alignment and Misaligned Accesses............................................................. 2-23
`Support for Misaligned Little-Endian Accesses........................................ 2-23
`Floating-Point Operand.................................................................................. 2-24
`Effect of Operand Placement on Performance .............................................. 2-26
`Instruction Set Summary.................................................................................... 2-26
`Classes of Instructions ................................................................................... 2-28
`Definition of Boundedly Undefined .......................................................... 2-28
`Defined Instruction Class .......................................................................... 2-28
`Illegal Instruction Class ............................................................................. 2-29
`Reserved Instruction Class ........................................................................ 2-30
`Addressing Modes ......................................................................................... 2-30
`Memory Addressing .................................................................................. 2-30
`Memory Operands ..................................................................................... 2-30
`Effective Address Calculation ................................................................... 2-31
`Synchronization ......................................................................................... 2-31
`Context Synchronization ....................................................................... 2-31
`Execution Synchronization.................................................................... 2-32
`Instruction-Related Exceptions.............................................................. 2-32
`Instruction Set Overview ............................................................................... 2-33
`PowerPC UISA Instructions .......................................................................... 2-33
`Integer Instructions .................................................................................... 2-33
`Integer Arithmetic Instructions.............................................................. 2-33
`Integer Compare Instructions ................................................................ 2-35
`Integer Logical Instructions................................................................... 2-35
`Integer Rotate and Shift Instructions ..................................................... 2-36
`Floating-Point Instructions ........................................................................ 2-37
`Floating-Point Arithmetic Instructions.................................................. 2-37
`Floating-Point Multiply-Add Instructions ............................................. 2-38
`Floating-Point Rounding and Conversion Instructions ......................... 2-38
`Floating-Point Compare Instructions..................................................... 2-39
`
`PowerPC 604e RISC Microprocessor User’s Manual
`
`MICROCHIP TECH. INC. - EXHIBIT 1025
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`Paragraph
`Number
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`2.3.4.2.5
`2.3.4.2.6
`2.3.4.3
`2.3.4.3.1
`2.3.4.3.2
`2.3.4.3.3
`2.3.4.3.4
`2.3.4.3.5
`2.3.4.3.6
`2.3.4.3.7
`2.3.4.3.8
`2.3.4.3.9
`2.3.4.4
`2.3.4.4.1
`2.3.4.4.2
`2.3.4.4.3
`2.3.4.4.4
`2.3.4.5
`2.3.4.6
`2.3.4.6.1
`2.3.4.6.2
`2.3.4.7
`2.3.5
`2.3.5.1
`2.3.5.2
`2.3.5.3
`2.3.5.3.1
`2.3.5.4
`2.3.6
`2.3.6.1
`2.3.6.2
`2.3.6.3
`2.3.6.3.1
`2.3.6.3.2
`2.3.6.3.3
`2.3.7
`
`CONTENTS
`
`Title
`
`Page
`Number
`
`Floating-Point Status and Control Register Instructions ....................... 2-39
`Floating-Point Move Instructions.......................................................... 2-40
`Load and Store Instructions ....................................................................... 2-40
`Self-Modifying Code............................................................................. 2-41
`Integer Load and Store Address Generation.......................................... 2-41
`Register Indirect Integer Load Instructions ........................................... 2-42
`Integer Store Instructions....................................................................... 2-43
`Integer Load and Store with Byte Reverse Instructions ........................ 2-44
`Integer Load and Store Multiple Instructions........................................ 2-44
`Integer Load and Store String Instructions............................................ 2-45
`Floating-Point Load and Store Address Generation.............................. 2-47
`Floating-Point Store Instructions........................................................... 2-48
`Branch and Flow Control Instructions....................................................... 2-50
`Branch Instruction Address Calculation................................................ 2-50
`Branch Instructions................................................................................ 2-50
`Condition Register Logical Instructions................................................ 2-51
`Trap Instructions.................................................................................... 2-51
`System Linkage Instruction—UISA.......................................................... 2-52
`Processor Control Instructions—UISA ..................................................... 2-52
`Move to/from Condition Register Instructions...................................... 2-52
`Move to/from Special-Purpose Register Instructions (UISA)............... 2-53
`Memory Synchronization Instructions—UISA ......................................... 2-53
`PowerPC VEA Instructions ........................................................................... 2-54
`Processor Control Instructions—VEA ...................................................... 2-55
`Memory Synchronization Instructions—VEA .......................................... 2-55
`Memory Control Instructions—VEA ........................................................ 2-56
`User-Level Cache Instructions—VEA .................................................. 2-57
`Optional External Control Instructions...................................................... 2-59
`PowerPC OEA Instructions ........................................................................... 2-59
`System Linkage Instructions—OEA ......................................................... 2-59
`Processor Control Instructions—OEA ...................................................... 2-59
`Memory Control Instructions—OEA ........................................................ 2-61
`Supervisor-Level Cache Management Instruction—(OEA) ................. 2-61
`Segment Register Manipulation Instructions (OEA)............................. 2-61
`Translation Lookaside Buffer Management Instructions—(OEA) ....... 2-62
`Recommended Simplified Mnemonics.......................................................... 2-63
`
`Chapter 3
`Cache and Bus Interface Unit Operation
`
`3.1
`3.2
`
`Data Cache Organization ..................................................................................... 3-4
`Instruction Cache Organization ........................................................................... 3-5
`
`Contents
`
`v
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`MICROCHIP TECH. INC. - EXHIBIT 1025
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`Paragraph
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`CONTENTS
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`3.3
`3.4
`3.4.1
`3.4.2
`3.5
`3.5.1
`3.5.2
`3.5.3
`3.6
`3.6.1
`3.6.2
`3.6.3
`3.6.4
`3.6.5
`3.6.6
`3.7
`3.8
`3.8.1
`3.8.2
`3.8.3
`
`3.8.4
`3.8.5
`3.8.6
`3.8.7
`3.9
`3.9.1
`3.9.2
`3.9.3
`3.9.4
`3.9.5
`3.9.6
`3.9.7
`3.9.8
`3.9.9
`3.10
`3.11
`
`4.1
`4.2
`
`vi
`
`MMUs/Bus Interface Unit ................................................................................... 3-6
`Memory Coherency Actions ................................................................................ 3-9
`PowerPC 604e-Initiated Load and Store Operations....................................... 3-9
`General Comments on Snooping ................................................................... 3-10
`Sequential Consistency ...................................................................................... 3-11
`Sequential Consistency Within a Single Processor ....................................... 3-11
`Weak Consistency between Multiple Processors .......................................... 3-11
`Sequential Consistency Within Multiprocessor Systems .............................. 3-12
`Memory and Cache Coherency.......................................................................... 3-12
`Data Cache Coherency Protocol .................................................................... 3-13
`Coherency and Secondary Caches................................................................. 3-15
`Page Table Control Bits................................................................................. 3-15
`MESI State Diagram...................................................................................... 3-15
`Coherency Paradoxes in Single-Processor Systems ...................................... 3-16
`Coherency Paradoxes in Multiple-Processor Systems................................... 3-17
`Cache Configuration .......................................................................................... 3-17
`Cache Control Instructions ................................................................................ 3-18
`Instruction Cache Block Invalidate (icbi)...................................................... 3-18
`Instruction Synchronize (isync)..................................................................... 3-19
`Data Cache Block Touch (dcbt) and
`Data Cache Block Touch for Store (dcbtst).............................................. 3-19
`Data Cache Block Set to Zero (dcbz)............................................................ 3-19
`Data Cache Block Store (dcbst) .................................................................... 3-20
`Data Cache Block Flush (dcbf) ..................................................................... 3-20
`Data Cache Block Invalidate (dcbi) .............................................................. 3-20
`Basic Cache Operations ..................................................................................... 3-20
`Cache Reloads................................................................................................ 3-20
`Cache Cast-Out Operation ............................................................................. 3-21
`Cache Block Push Operation ......................................................................... 3-21
`Atomic Memory References.......................................................................... 3-21
`Snoop Response to Bus Operations ............................................................... 3-22
`Cache Reaction to Specific Bus Operations .................................................. 3-22
`Enveloped High-Priority Cache Block Push Operation ................................ 3-25
`Bus Operations Caused by Cache Control Instructions................................. 3-26
`Cache Control Instructions ............................................................................ 3-26
`Cache Actions .................................................................................................... 3-27
`Access to Direct-Store Segments....................................................................... 3-48
`
`Chapter 4
`Exceptions
`
`PowerPC 604e Microprocessor Exceptions......................................................... 4-2
`Exception Recognition and Priorities .................................................................. 4-5
`
`PowerPC 604e RISC Microprocessor User’s Manual
`
`MICROCHIP TECH. INC. - EXHIBIT 1025
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`Paragraph
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`4.3
`4.3.1
`4.3.2
`4.3.3
`4.3.4
`4.4
`4.5
`4.5.1
`4.5.2
`4.5.2.1
`4.5.2.2
`4.5.3
`4.5.4
`4.5.5
`4.5.6
`4.5.7
`4.5.8
`4.5.9
`4.5.10
`4.5.11
`4.5.12
`4.5.13
`4.5.14
`4.5.15
`4.5.16
`
`5.1
`5.1.1
`5.1.2
`5.1.3
`5.1.4
`5.1.5
`5.1.6
`5.1.6.1
`5.1.6.2
`5.1.6.2.1
`5.1.6.2.2
`5.1.7
`5.1.8
`
`Contents
`
`Exception Processing ........................................................................................... 4-6
`Enabling and Disabling Exceptions................................................................. 4-9
`Steps for Exception Processing...................................................................... 4-10
`Setting MSR[RI] ............................................................................................ 4-11
`Returning from an Exception Handler........................................................... 4-11
`Process Switching .............................................................................................. 4-11
`Exception Definitions ........................................................................................ 4-12
`System Reset Exception (0x00100)............................................................... 4-13
`Machine Check Exception (0x00200) ........................................................... 4-14
`Machine Check Exception Enabled (MSR[ME] = 1)................................ 4-15
`Checkstop State (MSR[ME] = 0) .............................................................. 4-16
`DSI Exception (0x00300) .............................................................................. 4-16
`ISI Exception (0x00400)................................................................................ 4-16
`External Interrupt Exception (0x00500) ........................................................ 4-16
`Alignment Exception (0x00600) ................................................................... 4-17
`Program Exception (0x00700)....................................................................... 4-18
`Floating-Point Unavailable Exception (0x00800) ......................................... 4-19
`Decrementer Exception (0x00900)................................................................ 4-19
`System Call Exception (0x00C00) ................................................................ 4-19
`Trace Exception (0x00D00)........................................................................... 4-19
`Floating-Point Assist Exception (0x00E00) .................................................. 4-20
`Performance Monitoring Interrupt (0x00F00)............................................... 4-20
`Instruction Address Breakpoint Exception (0x01300) .................................. 4-21
`System Management Interrupt (0x01400) ..................................................... 4-21
`Power Management ....................................................................................... 4-21
`
`Chapter 5
`Memory Management
`
`MMU Overview................................................................................................... 5-2
`Memory Addressing ........................................................................................ 5-4
`MMU Organization.......................................................................................... 5-4
`Address Translation Mechanisms.................................................................... 5-9
`Memory Protection Facilities......................................................................... 5-11
`Page History Information............................................................................... 5-12
`General Flow of MMU Address Translation................................................. 5-12
`Real Addressing Mode and Block Address Translation Selection............ 5-12
` Page and Direct-Store Interface Address Translation Selection............... 5-14
`Selection of Page Address Translation.................................................. 5-16
`Selection of Direct-Store Interface Address Translation....................... 5-16
`MMU Exceptions Summary .......................................................................... 5-16
`MMU Instructions and Register Summary.................................................... 5-18
`
`vii
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`MICROCHIP TECH. INC. - EXHIBIT 1025
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`5.1.9
`5.2
`5.3
`5.4
`5.4.1
`5.4.1.1
`5.4.1.2
`5.4.1.3
`5.4.2
`5.4.3
`5.4.3.1
`5.4.3.2
`5.4.4
`5.4.5
`5.4.6
`5.4.7
`5.5
`5.5.1
`5.5.2
`5.5.3
`5.5.4
`5.5.5
`
`6.1
`6.2
`6.2.1
`6.2.1.1
`6.2.1.1.1
`6.2.1.1.2
`6.2.1.1.3
`6.2.1.1.4
`6.2.1.1.5
`6.2.1.1.6
`6.3
`6.3.1
`6.3.2
`6.3.3
`6.3.4
`6.3.4.1
`6.3.4.2
`
`viii
`
`TLB Entry Invalidation.................................................................................. 5-20
`Real Addressing Mode....................................................................................... 5-20
`Block Address Translation................................................................................. 5-20
`Memory Segment Model ................................................................................... 5-20
`Page History Recording ................................................................................. 5-21
`Referenced Bit ........................................................................................... 5-22
`Changed Bit ............................................................................................... 5-22
`Scenarios for Referenced and Changed Bit Recording ............................. 5-23
`Page Memory Protection ............................................................................... 5-24
`TLB Description ............................................................................................ 5-24
`TLB Organization...................................................................................... 5-25
`TLB Invalidation ....................................................................................... 5-26
`Page Address Translation Summary.............................................................. 5-28
`Page Table Search Operation......................................................................... 5-30
`Page Table Updates ....................................................................................... 5-34
`Segment Register Updates ............................................................................. 5-35
`Direct-Store Interface Address Translation ....................................................... 5-35
`Direct-Store Interface Accesses..................................................................... 5-35
`Direct-Store Segment Protection ................................................................... 5-36
`Instructions Not Supported in Direct-Store Segments................................... 5-36
`Instructions with No Effect in Direct-Store Segments .................................. 5-36
`Direct-Store Segment Translation Summary Flow........................................ 5-37
`
`Chapter 6
`Instruction Timing
`
`Terminology and Conventions............................................................................. 6-1
`Instruction Timing Overview............................................................................... 6-3
`Pipeline Structures ........................................................................................... 6-5
`Description of Pipeline Stages..................................................................... 6-7
`Fetch Stage .............................................................................................. 6-8
`Decode Stage ........................................................................................... 6-8
`Dispatch Stage ......................................................................................... 6-9
`Execute Stage .......................................................................................... 6-9
`Complete Stage...................................................................................... 6-10
`Write-Back Stage................................................................................... 6-11
`Memory Performance Considerations ............................................................... 6-11
`MMU Overview............................................................................................. 6-12
`Cache Overview............................................................................................. 6-12
`Bus Interface Overview ................................................................................. 6-14
`Memory Operations ....................................................................................... 6-14
`Write-Back Mode ...................................................................................... 6-14
`Write-Through Mode................................................................................. 6-15
`
`PowerPC 604e RISC Microprocessor User’s Manual
`
`MICROCHIP TECH. INC. - EXHIBIT 1025
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`6.3.4.3
`6.4
`6.4.1
`6.4.2
`6.4.2.1
`6.4.2.2
`6.4.3
`6.4.4
`6.4.4.1
`6.4.4.1.1
`6.4.4.1.2
`6.4.4.1.3
`6.4.4.1.4
`6.4.5
`6.4.6
`6.4.6.1
`6.4.6.2
`6.4.7
`6.4.7.1
`6.4.7.2
`6.4.7.3
`6.4.7.4
`6.4.7.5
`6.5
`6.5.1
`6.5.2
`6.5.3
`6.5.4
`6.5.5
`6.6
`6.6.1
`6.6.2
`6.7
`
`7.1
`7.2
`7.2.1
`7.2.1.1
`7.2.1.2
`
`Contents
`
`Cache-Inhibited Mode ............................................................................... 6-15
`Timing Considerations....................................................................................... 6-16
`General Instruction Flow ............................................................................... 6-16
`Instruction Fetch Timing ............................................................................... 6-17
`Cache Hit Timing Example ....................................................................... 6-17
`Cache Miss Timing Example..................................................................... 6-21
`Cache Arbitration........................................................................................... 6-23
`Branch Prediction .......................................................................................... 6-23
`Branch Timing Examples .......................................................................... 6-24
`Timing Example—Branch Timing for a BTAC Hit.............................. 6-24
`Timing Example—Branch with BTAC Miss/Decode Correction......... 6-25
`Timing Example—Branch with BTAC Miss/Dispatch Correction....... 6-27
`Timing Example—Branch with BTAC Miss/Execute Correction ........ 6-27
`Speculative Execution.................................................................................... 6-28
`Instruction Dispatch and Completion Considerations ................................... 6-29
`Rename Register Operation....................................................................... 6-30
`Execution Unit Considerations .................................................................. 6-32
`Instruction Serialization................................................................................. 6-32
`Dispatch Serialization Mode...................................................................... 6-33
`Execution Serialization Mode.................................................................... 6-33
`Postdispatch Serialization Mode................................................................ 6-33
`Serialization of String/Multiple Instructions ............................................. 6-34
`Serialization of Input/Output ..................................................................... 6-34
`Execution Unit Timings