(12) United States Patent
`Dai et al.
`
`USOO634.7379B1
`(10) Patent No.:
`US 6,347,379 B1
`(45) Date of Patent:
`Feb. 12, 2002
`
`(54) REDUCING POWER CONSUMPTION OF AN
`ELECTRONIC DEVICE
`
`(75) Inventors: Xia Dai, Santa Clara; Borys S. Senyk,
`San Jose, both of CA (US)
`
`(73) ASSignee: Intel Corporation, Santa Clara, CA
`(US)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/161,076
`(22) Filed:
`Sep. 25, 1998
`(51) Int. Cl. ................................................ G06F 13/24
`(52) U.S. Cl. ........................ 713/320; 713/322; 713/340
`(58) Field of Search ................................. 710/800, 310,
`710/320, 323,324, 330,340; 365/207;
`327/538,540, 544
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,189.647 A * 2/1993 Suzuki et al.
`
`5,481,731 A * 1/1996 Conary et al. .............. 711/141
`5,511,203 A * 4/1996 Wisor et al. ................ 713/322
`5,530.932 A * 6/1996 Carmean et al.
`5,581,500 A * 12/1996 D’Souza ..................... 365/156
`5,712,589 A * 1/1998 Afek et al. ................. 327/538
`5,761,715. A
`6/1998 Takahashi ................... 711/128
`5,970.007 A 10/1999 Shiratake .................... 365/207
`6,031,782. A
`2/2000 Kobashi et al. ............. 365/228
`6,069,519 A * 5/2000 Song .......................... 327/536
`
`* cited by examiner
`
`Primary Examiner Robert BeauSoleil
`ASSistant Examiner R Phan
`(74) Attorney, Agent, or Firm Trop, Pruner & Hu, P.C.
`(57)
`ABSTRACT
`Leakage power consumption may be reduced in computers
`and other devices by providing a State where clocks are off
`and a low Supply Voltage is provided to the processor. This
`Voltage may be Sufficiently low to prevent adverse conse
`quences while dramatically reducing leakage current. In
`addition, caches may be flushed to reduce the Soft error rate.
`
`17 Claims, 4 Drawing Sheets
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`START
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`116
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`SLEEP
`TRANSITION
`p
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`RESTART CLOCK
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`FLUSH CACHES
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`STOP CLOCK
`SHUTOFFPLLS
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`REDUCESUPPLY
`WOLIAGE
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`120
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`122
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`124
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`126
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`

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`U.S. Patent
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`Feb. 12, 2002
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`Sheet 1 of 4
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`US 6,347,379 B1
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`CONTROL LOGIC
`WCC DETECTOR
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`14
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`F.G. 1
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`VOLTAGE
`REGULATOR
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`CACHE &
`PREFETCH
`BUFFERS
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`INTRUCTIONS
`&
`DATA PATH
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`U.S. Patent
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`US 6,347,379 B1
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`U.S. Patent
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`Feb. 12, 2002
`
`Sheet 4 of 4
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`US 6,347,379 B1
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`START
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`116
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`SLEEP
`TRANSITION
`2
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`YES
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`RESTART CLOCK
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`FLUSH CACHES
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`STOP CLOCK
`SHUTOFFPLLS
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`REDUCE SUPPLY
`VOLTAGE
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`120
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`122
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`124
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`126
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`FIG. 5
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`STOP & GRANT/
`AUTO HALT
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`110
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`TART
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`114
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`FIG. 4
`(PRIOR ART)
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`/ 154
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`SLEEP
`TRANSITION
`2
`YES
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`INCREASE SUPPLY
`VOLTAGE
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`RESTART PLL &
`LOCK TO EXTERNAL
`BUS
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`156
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`158
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`START CLOCK
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`END
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`FIG. 6
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`1
`REDUCING POWER CONSUMPTION OF AN
`ELECTRONIC DEVICE
`
`BACKGROUND
`This invention relates generally to reducing the amount of
`power consumed in a reduced dynamic power consumption
`State by a variety of electronic devices including those that
`use battery power Sources, Such as portable computers.
`In devices Such as computers that may be operated from
`a battery, it is important to reduce the power consumption to
`the greatest possible extent. The usefulness of battery oper
`ated devices is reduced if the battery must be recharged
`frequently. A variety of techniques are known for reducing
`the dynamic power consumption. For example the Advanced
`Configuration and Power Interface (ACPI) Specification,
`(Rev. 1.0, Dec. 22, 1996) sets forth information about how
`to reduce the dynamic power consumption of portable and
`other computer Systems.
`With respect to the microprocessors used in computer
`Systems, four processor power consumption States (CO-C3)
`are defined in the ACPI Specification. When the processor is
`executing instructions it is in a CO State. There are three
`non-executing States (C1-C3). In a working computer
`System, the operating System dynamically transitions idle
`processors into the appropriate power consumption State.
`State C1 is the processor power state with the lowest
`latency. Basically, aside from putting the processor in a
`non-executing power State, the C1 State has no other Soft
`ware visible effects.
`The C2 power State offers improved power Savings Over
`the C1 State. Like the C1 State, aside from putting the
`processor in a non-executing power State, the State has no
`other software visible effects. In the C2 power state, the
`processor is still able to maintain the context of the System
`caches.
`The C3 power state offers still lower dynamic power
`consumption compared to the C1 and C2 states. While in the
`C3 State, the processor's caches are maintained but Snoops
`are ignored. The operating System Software is responsible
`for ensuring that cache coherency is maintained. In the C3
`State, the processor may not be able to maintain coherency
`of the processor caches with respect to other System activi
`ties. The C3 power consumption State uses less power but
`has a higher exit latency than the C2 power State.
`Generally, the C3 State uses one of two mechanisms to
`maintain cache coherency. The operating System may flush
`and invalidate the caches prior to entering the C3 State. The
`flushing of the caches may be provided through predefined
`ACPI mechanisms. Alternatively hardware mechanisms
`may be provided to prevent bus masters from writing to
`memory. In processors that use hardware mechanisms, the
`bus masters may be disabled prior to entering the C3 State.
`When a bus master requests an access, the processor awak
`ens from the C3 State and re-enables bus master access.
`While the reduced power consumption states outlined by
`the ACPI Specification and known techniques have many
`advantages, there are instances where greater power con
`Sumption reductions may be desired. Thus, there is a con
`tinuing need for ways to further reduce the power consump
`tion of computer Systems and other components including
`devices which are operated from batteries.
`SUMMARY
`In accordance with one embodiment, a method of reduc
`ing the power consumed by an electronic device using a
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`clock signal includes disabling the clock signal and reducing
`the leakage power consumption of the device.
`DESCRIPTION OF THE DRAWING
`FIG. 1 is a block diagram showing a processor core in
`accordance with one embodiment of the present invention;
`FIG. 2 is a block diagram of a computer System including
`the processor illustrated in FIG. 1;
`FIG. 3 shows a block diagram of a power management
`control circuit in accordance with one embodiment of the
`present invention;
`FIG. 4 is a chart showing the different prior art power
`consumption States,
`FIG. 5 shows a flow for reducing leakage power con
`Sumption; and
`FIG. 6 shows a methodology for transitioning from a
`reduced leakage power consumption State.
`DETAILED DESCRIPTION
`The power consumption of an electronic device may be
`made up of two components. The dynamic power consump
`tion relates to the power that is consumed when the device
`is operating. In connection with processors, the dynamic
`power consumption occurs when the processor's clocks are
`operating. The leakage power consumption may occur when
`the device is not operating and power continues to be
`consumed based on the leakage current which flows through
`the transistors, in the off State, that make up the electronic
`device.
`Leakage power consumption may derive from weak
`inversion and the finite impedance between the Source and
`drain of complementary metal oxide semiconductor
`(CMOS) transistors when the transistors are in the off state.
`This leakage current, which is Sometimes also called Sub
`threshold leakage, has an exponential dependency on thresh
`old voltage divided by thermal energy (kT).
`The threshold voltage may be determined by process
`conditions, temperature and channel length. As a rule of
`thumb, the leakage current doubles for every 15 C. increase
`in temperature. Moreover, as process technologies continue
`to Scale, the threshold Voltage and channel length become
`Smaller. As a result, the leakage current, and thus the leakage
`power consumption, increases for each process generation.
`Due to the short channel effect with Sub-micron channel
`lengths, leakage current may have a Sub-linear dependency
`on Supply Voltage. In other words, the leakage current
`decreases Sub-linearly as Supply Voltage decreases.
`Gate leakage due to a tunneling effect may also cause
`leakage current. The tunneling current has an exponential
`dependency on Supply Voltage.
`In portable computers with battery operation, the
`increased leakage power consumption may have a direct
`impact on battery life. Leakage current may be a limiting
`factor for threshold Voltage Scaling in battery operated
`devices.
`Referring now to FIG. 1, an architecture for one illustra
`tive embodiment of a microprocessor 12 implementing an
`embodiment of the present invention includes a clock gen
`erator 30 and a bus interface unit (BIU) 14. The BIU 14 is
`coupled to cache and prefetch buffers 16 which may include
`a branch target buffer (BTB). The caches may store instruc
`tions and data for execution by the processor 12. Prefetch
`bufferS may be coupled to a cache to enable prefetching of
`data and instructions from the cache or from the BIU 14 for
`execution by the processor 12.
`
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`3
`The cache and prefetch buffers 16 may be coupled to an
`instruction and data path Section 18. The instruction and data
`path Section 18 may include an instruction decoder that
`decodes the incoming instructions. A microcode unit may
`contain a memory which Stores the microcode instructions
`for the processor. The data path is the main execution path
`for the processor. It may contain an arithmetic logic unit
`register file, barrel shifter, constant read only memory and
`flags. The processor may also include a floating point unit
`(not shown).
`The clock unit 30 generates the clock signals for the
`processor 12. The clock unit 30 may, for example, generate
`the clock signals in response to an external frequency clock
`input. The clock unit 30 supplies the clock signals to the BIU
`14 and to the remaining units of the processor as well.
`The clock unit 30 also includes control logic 22 for
`controlling the operation of the clock unit 50. The control
`logic 22 may include a Vcc detector 24 which monitors the
`Supply Voltage level and issues a reset signal if the Voltage
`level becomes too low. The clock generator 12 also includes
`the phase locked loop (PLL) 42 which communicates with
`the BIU 14.
`The frequency of the internal clock may be controlled
`through Signals generated by an external clock 50 Such as the
`bus clock signal BCLK in processors made by Intel Corpo
`ration. That is, the internal clock may be sped up or slowed
`down based on the input clock signal from the clock 26.
`In addition a Voltage regulator 52 Selectively provides one
`of two supply voltage levels to the clock unit 30 and the rest
`of the processor 12. The Voltage regulator 52 may receive
`two reference Voltages. The higher reference Voltage may be
`a conventional external Supply Voltage in accordance with
`the particular technology being utilized. The lower reference
`Voltage may be the low power Supply Voltage to reduce
`leakage power consumption.
`Referring to FIG. 2, an example computer system 10
`includes a processor 12 (e.g., an 80x86 or Pentium(R) pro
`cessor from Intel Corporation) that receives an external
`clock BCLK (from a clock generator 50) and a supply
`voltage (from a Voltage regulator 52). The Voltage regulator
`52 and the clock generator 50 are both controllable to adjust
`the core Voltage levels as well as the core clock frequencies
`in the processor 12, as further described below.
`The main power Supply Voltages in the computer System
`10 are provided by a power supply circuit 56 that is coupled
`to a battery 60 and an external power source port 50. When
`the external power Source (not shown) is plugged in or
`removed, an interrupt (e.g., System management interrupt or
`SMI) may be generated to notify system software of the
`external power Source insertion or removal. In addition,
`docking the computer System 10 to a docking base unit may
`also indicate a power Source transition. In one embodiment,
`a device driver may detect power Source transitions and
`docking events by registering with the operating System for
`power and plug-and-play notifications, for example.
`The processor 12 may be coupled to a cache memory 54
`as well as to a host bridge 58 that includes a memory
`controller for controlling system memory 55. The host
`bridge 58 may also by coupled to a system bus 72, which
`may in one embodiment be a peripheral component inter
`connect (PCI) bus, as defined in the PCI Local Bus
`Specification, Production Version, Rev. 2.1, published on
`Jun. 1, 1995. The system bus 72 may couple other
`components, including a Video controller 64 coupled to a
`display 66 and peripheral Slots 68. A Secondary or expansion
`bus may be coupled by system bridge 74 to the system bus
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`72. The system bridge includes interface circuits to different
`ports, including a universal serial bus (USB) port 76 and
`mass Storage ports connectable to mass Storage devices Such
`as a hard disk drive.
`Other components coupled to the secondary bus 86
`include an input/output (I/O) circuit 90 that may couple to a
`parallel port, Serial port, floppy drive, and infrared port. A
`non-volatile memory 82 for Storing basic input/output Sys
`tem (BIOS) routines may be located on the bus 86, as may
`a keyboard device 92 and an audio control device 94, as
`examples.
`Referring to FIG. 3, an illustrative power management
`control logic according to an embodiment for controlling the
`core clock frequency and the Supply Voltage level to the
`processor 12 may be separated into a first portion 100 and a
`second portion 102. However, the first control logic portion
`100 may be included in the host bridge 58 and the second
`control logic portion 102 may be included in the system
`bridge 74. Alternatively, the first and second control logic
`portions may be implemented as Separate chips.
`The control logic 100, 102 provide control signals to the
`Voltage regulator 52 to adjust its Voltage levels and to the
`processor 12 to adjust the processor's internal clock fre
`quency. In addition, the power management control logic
`100, 102 may transition the processor 12 into a reduced
`power consumption State.
`A brief description of the interface Signals between the
`power management control logic 100, 102 and the other
`components of the system follows. The signal LO/HI#
`provided by the control logic 100 to the processor 12
`determines if a core clock frequency of the processor 12 is
`at a high or low level. As an example, the core clock
`frequency may vary between 350 MHz and 450 MHz
`depending on whether LO/HI# is active or not. Additional
`bits may be used to adjust the core clock frequency to more
`than two levels.
`A signal VR LO/HI# is provided by the control logic
`portion 100 to the voltage regulator 52 to adjust the voltage
`level Supplied by the voltage regulator 52. Additional bits
`other than VR LO/HI# may also be used to provide addi
`tional Voltage levels.
`A signal G STPCLK# may be provided to the processor
`12 and a signal G CPU STPH may be provided to the
`clock generator 50 to place the processor 12 in a reduced
`dynamic power consumption state (e.g., deep sleep, stop
`grant, C2, or C3 State) So that the clock frequency and Supply
`Voltage level of the processor 12 may be varied.
`A signal VRCHGNG# is provided by the control logic
`100 to system electronics circuitry 101 (e.g., the host bridge
`58 and system bridge 74) to indicate that the voltage level
`from the Voltage regulator 52 is changing. A signal VRP
`WRGD from the control logic portion 100 to system elec
`tronic circuitry (e.g., the host bridge 58 and System bridge
`74) indicates when the output from the voltage regulator 52
`is within Specification.
`According to one embodiment of the invention, when the
`voltage regulator on signal (VR ON) is active (which is
`true whenever the System is on), the voltage regulator 52
`settles to the output selected by VR LO/HI# (a low level or
`a high level). When the outputs of the regulator 52 are on
`and within Specification, the Voltage regulator 52 asserts a
`signal VGATE, which in turn controls the state of the signal
`VRPWRGD provided by the control logic portion 100 to
`System electronics circuitry.
`Referring to FIG. 4, the conventional processor power
`management modes for an Intel architecture processor are
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`S
`illustrated. The blocks 110-114 correspond to the ACPI
`Specification processor power consumption States C1-C3
`respectively. In the Intel architecture processors, the C1
`mode is called the Stop and grant/autohalt mode. In this State
`most functional blocks of the processor are turned off by
`disabling clocks. The phase locked loop (PLL) and the
`global clock Spine are left running. Some functional blockS
`are left running to Support bus activity and Snooping.
`In block 112, called “sleep” mode in desktops and “quick
`Start” in mobile computer Systems using Intel architecture,
`all the functional blocks and most of the input/output
`devices are turned off. The PLL, global clock spine and a
`few I/O devices are kept running.
`In block 114 the ACPI processor power consumption state
`C3 (also called the deep sleep State in the Intel architecture)
`is illustrated. In this state, the PLL is off. All the functional
`blockS Stop running, but the registers and caches maintain
`their contents.
`Referring now to FIG. 5, the transition to a modified deep
`sleep state corresponding to a modified state C3 of the ACPI
`Specification is illustrated. Initially a check at diamond 116
`determines whether a transition to the C3 State is appropri
`ate. This may occur based on inactivity or other triggering
`events as set forth for example in the ACPI Specification.
`Normally the transition to the C3 state would occur in a
`device which is already in the C2 state. When the transition
`occurs, the processor clock may be restarted, as indicated in
`block 120. This may be accomplished by asserting
`G STPCLK#. Since the clock was stopped before entering
`the C3 state, it is restarted to flush the caches. Next the
`caches, Such as the L2, L1 and BTB caches, are flushed as
`indicated in block 122.
`The reason for flushing the caches is to reduce the Soft
`error rate (SER). A Soft error occurs as a result of particles,
`Such as alpha particles, which cause charges to be formed in
`Semiconductor devices. With relatively low Supply Voltages,
`the rate of Soft errors increases dramatically. Therefore a
`flush instruction is used to flush caches Such as the L2 cache,
`the L1 cache and the BTB. After the caches are flushed, as
`indicated in block 122, the clock may then be stopped and
`the PLL is shut off, as indicated in block 124. This may be
`accomplished by deasserting G STPCLK#.
`Next the Supply Voltage transitions to a low Supply
`voltage as indicated in block 126. This may be done by
`asserting the low level of VR LO/HI#. Generally the Sup
`ply voltage of the device is lowered to 100 mV to 150 mV
`above the threshold voltage (including an adjustment for
`process variation) at room temperature of the n-type metal
`oxide semiconductor (NMOS) or p-type metal oxide semi
`conductor (PMOS) transistors, whichever is larger. The
`Supply Voltage transitions in response to a signal that imple
`ments the transition to the C3 processor State. This transition
`Signal causes the low reference Signal to control the Voltage
`regulator 52.
`The exact level of the low Supply Voltage depends on the
`threshold Voltage spread and the process control with a
`particular technology. A low Supply Voltage is used that is
`Sufficient to maintain all the internal registers of the device
`So that they retain their contents while avoiding floating
`nodes.
`Thus, an adjustment due to proceSS Variations may be
`added to the threshold Voltage. Agate overdrive Voltage may
`be added to that Voltage to avoid floating nodes. Finally a
`guard band Voltage for the power Supply may be included,
`which in an exemplary embodiment may be 10% of the sum
`of the threshold Voltage, the threshold Voltage adjustment
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`for proceSS Variations and the gate overdrive Voltage. The
`low Supply Voltage level may then be made up of the Sum of
`the threshold Voltage, the process variation adjustment, the
`gate overdrive Voltage and the guard band Voltage for the
`power Supply. In one exemplary embodiment, the threshold
`voltage may be 350 mV, the threshold voltage variation may
`be 50 mV, the gate overdrive voltage may be 100 mV and the
`guard band Voltage may be 50 mV, resulting in a low Supply
`voltage of approximately 550 mV.
`In general, the low Supply Voltage is less than twice a
`transistor threshold Voltage. In one advantageous embodi
`ment the low Supply Voltage may be less than or equal to
`about 600 mV. In another advantageous embodiment, the
`low Supply voltage is about 200 mV above a transistor
`threshold voltage. Also it may be advisable in some embodi
`ments to reduce the leakage power consumption to less than
`or equal to 25% of what it would be at a conventional supply
`Voltage level for a given technology.
`In Some processors, including Intel architecture
`processors, when the internal processor Voltage falls below
`a certain level, the CPUPWRGD signal is deasserted. When
`the CPUPWRGD signal is asserted again, the processor
`automatically starts a reset Sequence. It is desirable to avoid
`the reset Sequence because reset destroys the processor
`register contents.
`The power good (PWRGOOD) signal generated in Intel
`architecture processors is the logical AND of the external
`power good and the internal power good Signals. There is a
`power good input pin on Intel architecture processors. The
`power good Signal is not latched and enables the PLL
`circuitry. The internal power good Signal, generated from
`Voltage detection circuitry 24, trips when the internal Supply
`voltage (Vcc) is below a certain voltage level, which then
`shuts off the PLL. Since the internal Supply voltage (Vcc) is
`raised before the PLL starts to lock to the external clock, the
`power good signal will be normal before the PLL starts to
`lock to the external clock.
`There are at least two ways to prevent glitching of the
`power good signal during the modified deep sleep State. The
`internal power good may be gated by a signal which is the
`logical AND of a signal indicating whether the computer has
`a modified deep sleep State and a Signal indicating that the
`modified deep sleep State has been entered.
`Alternatively, the Vcc detector 24 may be disabled (for
`example by asserting the PLLIDDQ pin 22 in Intel(R)
`processors) during the modified deep sleep State. A disable
`signal (e.g., PLLIDDQ) may be used to disable the Vcc
`detector during a D.C. current test for shorts, called an
`IDDQ test. This Vcc detector disable signal may also be
`used to disable the Vcc detector to avoid the reset when the
`Voltage is deliberately lowered to reduce leakage power
`consumption. Once the Vcc detector is disabled, the reset is
`not generated when the Voltage level is decreased.
`Some I/O circuitry may need to use a separate power rail
`in order to avoid triggering a false signal event when the
`Supply Voltage is lowered. I/O Signals like data and address
`do not need to have a separate power rail because they are
`not sampled during the modified deep sleep State.
`Through the techniques described herein leakage power
`consumption may be reduced through reduced leakage cur
`rent and Supply Voltage, Since leakage power is a function of
`leakage current times Supply Voltage. Due to the Sublinear
`dependency of leakage current on Voltage, the leakage
`power consumption has a Square power dependency on
`Voltage. Thus at Sufficiently low Supply Voltages, the reduc
`tion of Supply Voltages during the modified deep sleep State
`may significantly reduce power consumption.
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`7
`Latency may be minimized compared to a Suspend to
`RAM State. Exiting the modified deep sleep State may take
`about 1 to 2 milliseconds while the latency of exiting the
`suspend to RAM state may be 10 to 20 seconds.
`In addition, the Soft error rate is reduced because caches
`are flushed before entering the modified deep sleep State.
`Since pipelines are drained before entering the modified
`deep sleep State, latches and domino circuits may be free of
`Soft errors. In at least Some embodiments, the only Storage
`elements that are still Susceptible to Soft errors in the
`modified deep Sleep State are the registers. Thus the Soft
`error rate may be reduced.
`Referring now to FIG. 6, the processor may exit the deep
`Sleep State in response to a Sleep transition signal, indicated
`at diamond 154. In response to the transition Signal, for
`example triggered as Set forth in the ACPI Specification, the
`Supply Voltage may be increased using the higher Voltage
`reference, as indicated in block 156, for example by assert
`ing the high level of VR LO/HI#. The PLL may be restarted
`and locked to the external clock as indicated in block 158 for
`example by asserting G STPCLK#. Once the PLL is locked
`to the external clock, the internal clock 30 may be started as
`indicated in block 160.
`While the present invention has been described with
`respect to a limited number of embodiments, those skilled in
`the art will appreciate numerous modifications and varia
`tions. It is intended that the appended claims cover all Such
`variations and modifications as fall within the true Spirit and
`Scope of the present invention.
`What is claimed is:
`1. A method for operating an electronic device, Said
`device using a clock signal, consuming power, having a
`Supply Voltage and having a transistor having a threshold
`Voltage, Said method comprising:
`disabling the clock signal; and
`reducing the leakage power consumption of the device
`comprising reducing the Supply Voltage to about 200
`mV over a transistor threshold voltage.
`2. The method of claim 1 wherein reducing the leakage
`power consumption includes reducing a voltage of at least
`one component to lower leakage power consumption of the
`device.
`3. The method of claim 1 wherein reducing the leakage
`power consumption includes flushing at least one cache.
`4. The method of claim 3 wherein said device includes a
`clock and wherein reducing the leakage power consumption
`includes restarting the clock before flushing a cache.
`5. The method of claim 4 wherein reducing the leakage
`power consumption includes disabling the clock signal after
`flushing a cache.
`6. The method of claim 1 wherein reducing the leakage
`power consumption includes reducing a processor Supply
`Voltage.
`7. The method of claim 1 wherein reducing the leakage
`power consumption includes reducing the Supply Voltage to
`a level low enough to prevent Substantial leakage current.
`8. The method of claim 7 further including reducing time
`Supply Voltage from a first level to a Second level, Such that
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`8
`the leakage power consumption at Said Second level is 25%
`or less of that at the first level.
`9. The method of claim 1 wherein said device includes a
`processor and wherein reducing the leakage power con
`Sumption includes reducing the Supply Voltage to less than
`twice the threshold Voltage of a transistor in Said processor.
`10. The method of claim 1 wherein the step of reducing
`the leakage power consumption includes reducing the Sup
`ply voltage to 600 mV or less.
`11. The method of claim 1 wherein said device is a
`processor and wherein Said processor has a Supply Voltage,
`Said method further including preventing the processor from
`undergoing a reset Sequence when the Supply Voltage is
`increased.
`12. A method for implementing a reduced processor
`power consumption mode in a processor including System
`caches and including transistors with threshold Voltages,
`Said processor further including a processor clock and a
`processor Supply Voltage, Said method comprising:
`flushing the System caches,
`Stopping the processor clock, and
`reducing the processor Supply Voltage to less than or equal
`to approximately 600 mV.
`13. The method of claim 12 wherein reducing the pro
`ceSSor Supply Voltage includes reducing Said Voltage to leSS
`than or equal to approximately 600 mV.
`14. The method of claim 12 wherein reducing the pro
`ceSSor Supply Voltage includes reducing the Supply Voltage
`to about 200 mV above said transistor threshold voltage.
`15. A method for operating an electronic device, Said
`device using a clock signal, consuming power, having a
`Supply Voltage and having a transistor having a threshold
`Voltage, Said method comprising:
`disabling the clock signal;
`reducing the leakage power consumption of the device
`comprising reducing the Supply Voltage to about 200
`mV over a transistor threshold Voltage, and
`increasing the Supply Voltage then restarting the processor
`phase locked loop and then restarting the processor
`clock.
`16. A method for implementing a reduced processor
`power consumption mode and a processor including System
`caches and including transistors with threshold Voltages,
`Said processor further including a processor clock and a
`processor Supply Voltage, Said method comprising:
`flushing the System caches,
`Stopping the processor clock,
`reducing the processor Supply Voltage to less than twice
`the threshold Voltage of one of the transistors, and
`increasing the Supply Voltage, restarting the processor
`phase locked loop and restarting the processor clock.
`17. The method of claim 16 further including preventing
`the processor from undergoing a reset Sequence when the
`Supply Voltage is increased.
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`k
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`k
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`k
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`k
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`k
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`MICROCHIP TECH. INC. - EXHIBIT 1022
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 009
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