United States Patent
`McLaughlin et al.
`
`1191
`
`(S4] REDUCING POWER CONSUMPTION IN
`CALCULATORS
`(75 I Inventors: Donald L. McLaughlin, Newtown
`Square; Ronald W. Streiber,
`Norristown, both of Pa.
`[73] Assignee: MOS Technology, Inc., Norristown,
`Pa.
`Dec. 13, 1974
`[22) Filed:
`(21 I Appl. No.: 532,596
`
`I S2 J U.S. CL. ......... 235/156; 340/172.5; 340/324 R
`(511 lnt.Cl. 2
`G06F7/38;G06F 1/04
`I 58 I Field of Search ...... 235/156; 340/324 R; 445/ I
`
`........................
`
`I 56 J
`
`3,453,60 I
`3,781,852
`3,812,489
`
`References Cited
`UNITED STATES PATENTS
`Bogert et al. .................... 340/172.5
`7/1969
`White et al. .................... 340/324 R
`12/1973
`5/ 1974
`Hirano et al. ................... 340/324 R
`
`3,941,989
`I 11 l
`[451 Mar. 2, 1976
`
`Primary Examiner-R. Stephen Dildine, Jr.
`Attorney, Agent. or Firm-Cooper, Dunham. Clark.
`Griffin & Moran
`
`(57]
`ABSTRACT
`Continuous power and a high rate clock are supplied
`to a calculator while it is in an execute mode and is
`actually decoding and processing input information,
`but lower duty cycle power and lower duty cycle clock
`pulses are supplied during
`the subsequent display
`mode, when the only requirement is to maintain and
`display selected information resulting from the exe(cid:173)
`cute cycle, so as to reduce the power consumption
`rate as compared to the rate during the execute mode.
`If there is no new execute mode within a selected time
`interval, the display is turned off and the duty cycle of
`the power and the clock supplied to the calculator are
`lowered still further so as to maintain (without dis(cid:173)
`playing) selected stored information but to further re(cid:173)
`duce the rate of power consumption.
`15 Claims, 3 Drawing Figures
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`MICROCHIP TECH. INC. - EXHIBIT 1015
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 001
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`MICROCHIP TECH. INC. - EXHIBIT 1015
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 002
`
`

`

`U.S. Patent March 2, 1976
`
`Sheet 2 of 3
`
`3,941,989
`
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`MICROCHIP TECH. INC. - EXHIBIT 1015
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 003
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`MICROCHIP TECH. INC. - EXHIBIT 1015
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 004
`
`

`

`1
`
`3,941,989
`
`REDUCING POWER CONSUMPTION IN
`CALCULATORS
`
`BACKGROUND OF THE INVENTION
`
`2
`intervention. In accordance with the
`without operator
`invention, the power supplied to the calculator during
`each execute mode operation
`is at a high duty cycle
`(e.g., continuous power) and the calculator is continu-
`5 ously clocked with a high rate clock, so as to minimize
`The invention is in the field of calculators employing
`the duration of the execute mode operation and quicky
`dynamic storage of information and dynamic display of
`provide the information sought by the operator.
`stored information, and specifically relates to calcula-
`During the display enable mode operation which
`tors of this type in which the rate of power consump-
`tion is of concern, such as in hand-held calculators 10 follows each execute mode operation, the decoding or
`results are displayed dynamically. If cer-
`which are battery powered.
`calculations
`Calculators of this type typically have three alternate
`tain new information
`is keyed in during the display
`operating modes. There
`is an execute mode during
`enable mode operation, the calculator goes into a new
`which input information
`is decoded and is arithmeti-
`execute mode operation, which is followed by a new
`cally and logically processed in accordance with either 15 display enable mode operation. If no such new informa-
`input or stored commands
`to provide selected pro-
`tion is keyed in for a certain period of time during the
`cessed information. The execute mode operation
`is
`display enable mode operation, the calculator automat-
`typically followed automatically, without operator
`in-
`ically goes into a display inhibit mode operation, with-
`tervention, by a display mode in which selected pro-
`out any operator intervention. In accordance with the
`cessed information
`is displayed. When selected new 20 invention, the duty cycle of the power supplied to the
`information
`is entered,
`there is a new execute mode
`calculator during each display enable mode operation
`operation followed by a new display mode operation. If
`is lower than the duty cycle of the power supplied dur-
`there is no new execute mode operation within a cer-
`ing the execute mode operation, e.g., the calculator is
`tain time interval,
`the calculator automatically goes
`supplied with a chopped voltage at a one-fourth duty
`into a display inhibit mode (alternately called blank- 25 cycle. Further, the duty cycle of the clock pulses sup-
`ing), in which the relevant
`information
`is no longer
`plied during the display enable mode is lower than the
`J k
`J
`1· d d
`·
`h
`displayed, but is maintained in storage so that it can be
`d
`I
`f h
`.
`• d" 1
`uty eye e o t e c oc puses supp 1e urmg t e exe-
`agam
`isp ayed if needed.
`cute mode e.g. the same width clock pulses are sup-
`A typical calculator of this type (disclosed in White
`plied duri~g th~ display enable mode operation but
`et ~I. U.S. Pat. No. 3,781,852) o~erates at full power 30 only while power is being supplied to the calcula~or.
`dunng all three modes of operation,
`the only power
`Wh
`th
`I
`·
`d.
`I
`· h"b"
`d
`isp ay ~n-I I! mo e
`I
`reducing scheme being that the display is not driven
`e~
`e ca c_u ator_goes mto a
`operatton, the display 1s blanked out, but 1t 1s still nec-
`· h·b·t
`d
`f
`t" A
`durl·ng the d"s 1
`1 p ay m 1 1 mo e o opera ton.
`some-
`.
`.
`.
`what different approach
`is disclosed in Bo
`t
`essary to preserve certain dynamically stored mforma-
`t
`I
`U .S. Pat. No. 3 453 601 where a calculator f:~1o:k:d
`35 tion. In accordance with the invention, during each
`at a high frequ~nc/during
`its arithmetic mode opera-
`di~play _inhibit mode operation
`the ~alc~lator is sup-
`tion to ensure high calculating speed but is clocked at
`phed with. power _at a duty_ cycle which 1s lower than
`a lower frequency and low duty cycle during its subse-
`t~at supphe~ durmg the display enable ~ode opera-
`tton, e.g., with a chopped voltage at one-eighth of the
`quent display mode operation in order to reduce power
`consumption. However, the Bogert et al. system has no 40 duty cycle of the voltage supplied during the execute
`display inhibit mode of operation and has no special
`mode operation. Further, the duty cycle of the clock
`provisions for applying power to the calculator at dif-
`supplied to the calculator is lower than that supplied
`ferent duty cycles during different modes of operation.
`during the display enable mode, e.g. the same width
`clock pulses are supplied but only while power is being
`45 applied to the calculator.
`Typically, a calculator of this type is in an execute
`mode for only a small fraction of its operating time, and
`most of the operating time is spent in the display enable
`mode. The display inhibit mode occurs rarely (for ex-
`SO ample, when the operator forgets to turn off the calcu(cid:173)
`lator) but when it occurs, and no provisions are made
`to reduce power consumption,
`it is likely to continue
`for a substantial period of time and to drain a substan-
`55 tial amount of battery power.
`In accordance with the invention, both the power
`supply duty cycle and the clock duty cycle are con(cid:173)
`trolled to reduce power consumption without sacrific(cid:173)
`ing speed or accuracy, since both are optimized for
`60 each of the three different operating modes of the cal(cid:173)
`culator. Further in accordance with the invention, both
`the calculator logic array and the necessary logic and
`circuit elements for carrying out this invention are
`parts of the same integrated circuit, to thereby improve
`65 the reliability of the calculator, and to reduce the cost
`of implementing the invention as compared to imple(cid:173)
`menting the invention in a circuit composed of discrete
`components or in a separate integrated circuit.
`
`SUMMARY OF THE INVENTION
`An object of the invention is to reduce the power
`consumption of calculators, and particularly of hand(cid:173)
`held calculators which are battery powered, by supply(cid:173)
`ing to the calculator only as much power as actually
`needed for each different mode of operation and by
`clocking the calculator at a rate which is only as high as
`actually needed for each different mode of operation.
`The invention is applicable to calculators which have
`three different modes of operation: an execute mode in
`which input information is decoded and is processed to
`derive and dynamically store selected processed infor(cid:173)
`mation, a display enable mode in which selected stored
`information
`is maintained
`in dynamic storage and is
`concurrently dynamically displayed, and a display in(cid:173)
`hibit mode during which selected information is main(cid:173)
`tained in dynamic storage but is not displayed. Each
`execute mode operation
`is typically initiated by infor(cid:173)
`mation keyed by an operator
`through a keyboard and
`includes decoding the keyed information, any calcula(cid:173)
`tions such as addition, multiplication, etc. and storing
`of any resulting information in dynamic storage. Once
`the execute mode operation is completed, the calcula(cid:173)
`tor automatically goes into a display enable mode,
`
`MICROCHIP TECH. INC. - EXHIBIT 1015
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 005
`
`

`

`3,941,989
`
`5
`
`3
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a simplified block and logic diagram of a
`calculator embodying the invention.
`FIG. 2 is a detailed logic and circuit diagram illustrat(cid:173)
`ing an embodiment of the invention.
`FIG. 3 is a timing diagram illustrating the duty cycle
`of the power and of the clock pulses supplied in accor(cid:173)
`dance with the invention to a calculator during each of
`three different operating modes thereof.
`
`4
`mittent output of AND-gate 32 is applied through an
`OR-gate 34 to enable AND-gate 36 and turn on transis(cid:173)
`tor switch 38 intermittently, at the same duty cycle, to
`thereby intermittently apply power to the power supply
`input 16 and to apply clock pulses to the clock input 18
`of calculator array 10 at a duty cycle corresponding to
`one-eighth the frequency F of oscillator 14.
`When an execute mode operation starts, e.g. in re(cid:173)
`sponse to information keyed in bt__ an operator through
`10 keyboard 10, the control signal DI goes high, thereby
`disabling AND-gate 32, but control signal EX also goes
`DETAILED DESCRIPTION
`high, thereby enabling AND-gate 28 to apply a contin-
`to AND-gate 36 and switch 38
`uous high output
`The invention is described as applied to a hand-held,
`through OR-gate 34,
`thereby applying continuous
`battery powered calculator of the type disclosed
`in
`White et al. U.S. Pat. No. 3,781,852, which uses dy- 15 power to the power supply input 16 of calculator array
`10 and applying clock pulses to the calculator array
`namic storage of the type described in the White et al.
`clock input 18 at the frequency F of oscillator 14.
`patent or in Bogert et al. U.S. Pat. No. 3,453,60 I and a
`dynamic display of the type described in the White et
`Meanwhile, the control signal DE remains low and gate
`30 remain.s disabled.
`al. patent. However, it should be clear that the inven-
`tion is applicable
`to other calculators using dynamic 20 When the execute mode operation ends, control
`storage and display in which the rate of power con-
`signal DE goes high, while control signal EX goes low
`sumption is of concern and in which it is desirable to
`and control signal DI remains high. Therefore, AND-
`gate 28 is disabled and AND-gate 32 remains disabled,
`reduce power consumption.
`Referring to FIG. 1, a calculator logic 10, a keyboard
`but AND-gate 30 is enabled intermittently at a duty
`l Oa and a display l Ob are generally of the type shown 25 cycle corresponding
`to one-fourth the frequency F of
`oscillator 14, to thereby enable AND-gate 36 and turn
`in the White et al. patent, supra, or calculator logic 10
`on switch 38 intermittently. Therefore, power is ap-
`may be of the type manufactured by MOS Technology,
`plied to the calculator power supply input 16 and clock
`Inc., under the name Calculator Array 2521. However,
`pulses are applied to the clock input 18 of the calcula-
`power and clock are not supplied directly to the power
`supply input J6 and the clock input 18 of calculator 30 tor 10 intermittently, at a rate corresponding
`to one-
`logic 10 as in the prior art, but are supplied under the
`fourth the duty cycle of the frequency F of oscillator
`control of a power and control logic 12 which forms a
`14.
`part of this invention and which, in accordance with the
`If a new execute mode operation occurs while the
`invention, is formed on the same IC chip 15 with calcu-
`control signal DE is high, control signal EX goes high,
`lator logic 10.
`35 while control signal DE goes low and control signal DI
`Calculator logic 10 provides at its output 20 a control
`remains high, and the power and clock applied to cal-
`culator array 10 are at a high duty cycle. If no new
`signal EX while the calculator
`is operating in an exe-
`cute mode, provides at its output 22 a control signal DE
`execute mode operation occurs within a certain time
`while the calculator
`is operating
`in a display enable
`inter~I after control signal DE goes high, control sig-
`mode and provides at its output 24 a control signal Di 40 nals DI and DE go low, while control signal EX remains
`which is high when the calculator is either in the exe-
`low, and the lowest duty cycle power and clock are
`applied to calculator array 10.
`cute mode or in the display enable mode and is low
`otherwise. Since the control signals ( or their equiv a-
`As a result, full power and a high duty cycle clock are
`lents) provided at the output 20, 22 and 24 of calcula-
`applied to calculator 10 during an execute mode opera-
`tor 10 are provided by prior art calculators of the type 45 tion, to thereby minimize the time needed to do the
`described in the White et al. patent, supra and by the
`necessary processing of input information, but the duty
`Inc. Calculator Array 2521, and
`cycle of both the power applied to calculator 10 and
`MOS Technology,
`the clock with which the calculator 10 is clocked are
`such calculators do not form a part of this invention, no
`detailed description is given of the circuits necessary to
`lowered during the display enable mode of operation,
`generate these control signals.
`50 where great processing speed is not of the essence and
`The operation of a calculator in accordance with the
`the need is only to clock the calculator at a sufficient
`invention is described briefly and in a simplified form in
`speed and with sufficient power so as to preserve cer-
`connection with FIG. 1, and the detailed construction
`tain dynamically stored information and to clock dis-
`and operation of a calculator embodying the invention
`play 10b with sufficient power and speed to prevent
`55 visible flicker and maintain sufficient brightness. Fur-
`is described in connection with FIGS. 2 and 3.
`Referring to FIG. 1, when an ON/OFF switch 13 is
`thermore, if the calculator enters into a display inhibit
`closed manually by an operator, power supply 11 is
`mode of operation,
`the duty cycle of the power sup-
`connected to turn on clock oscillator 14 and provide at
`plied to it and the duty cycle of the clock with which it
`the oscillator output a clock signal at a frequency F.
`is clocked are further reduced, since brightness and
`This clock signal is applied to a time divider 26 which 60 visible flicker are no longer of concern, nor is speed of
`outputs clock signals at one-fourth and at one-eighth
`arithmetic and logic operations, the only concern being
`the frequency F of oscillator 14. Assuming that the
`the preservation of certain dynamically stored informa-
`ON/OFF switch 13 has just been closed but no informa-
`tion.
`tion has yet been entered through ~eyboard 10a, each
`For simplicity, the description of FIG. 1 does not take
`of the control signals EX, DE and DI is low. As a result, 65 into account the fact that immediately upon the closing
`AND-gates 28 and 30 remain disabled, but AND-gate
`of switch 13, calculator array 10 goes into a "power on
`32 is intermittently enabled at a rate corresponding
`to
`clear" routine, which is an execute mode operation and
`one-eighth the frequency F of oscillator 14. The inter-
`typically lasts for a small fraction of a second, and then
`
`MICROCHIP TECH. INC. - EXHIBIT 1015
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 006
`
`

`

`3,941,989
`
`6
`5
`flop 54, as provided at the output of a gate 56. Flip-flop
`goes into a display enable mode operation, displaying
`54 is set by the output of a gate 58 when control signal
`at display 10b a selected symbol such as a O and there-
`DE is high but control signal DI is low (for the time
`after goes into a display inhibit mode if no new execute
`being, the nature and function of a control signal DO
`mode has been initiated by an operator
`through key-
`5 are disregarded). When flip-flop 54 is set, the logical
`board 10a. Also for the sake of simplicity, clock oscilla-
`tor 14 is shown as providing a clock signal at a fre-
`low signal at
`its complementary
`output
`is applied
`through gate 56 to gate 52, so that the signal applied to
`quency F, while in fact, as discussed in connection with
`Power Control flip-flop 48 through gates 52 and 47 is
`FIGS. 2 and 3, there are two complementary
`clock
`the logical AND function of time divided signals B and
`pulse
`trains. With respect
`to the
`terms "high" and
`"low" as applied to the control signals EX, DE and DI, 10 C. As a result, power control flip-flop 48 is set and reset
`it should be clear that the reference
`is to logical levels
`in timed relation to that AND function, as illustrated in
`and not to voltage levels of signals. Further, it should be
`FIG. 3. There is a time delay equal to one-half the cycle
`of the clocks c/Ji' and cf,/ because of the way the rele-
`clear that the duty cycle of the power applied to calcu-
`lator array 10 can be other
`than as described above,
`vant flip-flops are clocked, as explained
`later.
`e.g., full power or high duty cycle power during an 15 At the end of a display enable mode of operation and
`execute mode, one-third duty cycle during a display
`the beginning of a display inhibit mode of operation,
`enable mode, one-sixth duty cycle during a display
`control signal DE goes low and control signal DI goes
`high. As a result, flip-flop 54 is reset by the output of
`inhibit mode, etc., and it should be clear that the term
`gate 58, and the logical high at the complementary
`"high duty cycle power" may mean
`less than
`I 00%
`20 output of flip-flop 54 no longer provides a logical high
`duty cycle.
`Referring to FIG. 2, which shows in greater detail an
`signal at the output of gate 56. Now gate 52 is enabled
`embodiment
`of the invention whose principles were
`only at the coincidence of time divided signals A, B,
`in simplified form in connection with FIG. 1,
`and C, and Power Control flip-flop 48 is enabled and
`described
`a clock generator 40 corresponds
`to oscillator 14 of
`disabled in time relationship
`to this logical AND func-
`FJG. 1, but provides clock signals c/Ji' and cf,2 ' rather 25 tion of the time divided signals A, B, and C. Again, note
`than a single signal F. Clock oscillator 40 comprises a
`that the power provided at the output of circuit 50 is
`conventional configuration of a flip-flop whose set and
`delayed with respect
`to the AND function of control
`reset inputs are interconnected
`as shown by a series of
`signals A, B, and C by one-half the cycle of the clock
`signals c/Ji' and cf,2 '.
`inverters, and the two clock signals provided at the
`to FIG. 3, the power applied
`to the con-
`outputs of the flip-flops are at the ame frequency but 30 Referring
`1800 out of phase. The clock signals c/Ji' and cf,z' are
`input 16 of calculator
`array 10 from
`trolled power
`to a time divider 42 to clock each of its flip-
`applied
`circuit 38 during an execute mode operation
`is continu-
`flops labelled A, Band C, which are interconnected
`in
`ous power, the power applied during a display enable
`a conventional
`time-divider configuration
`through suit-
`mode operation
`is intermittent
`power, at 25% duty
`35 cycle, and the power applied during the display inhibit
`able gating.
`to FIG. 3, where the top two lines show the
`Referring
`mode of operation
`is intermittent power, at a 12½%
`clock signals q,1 ' and cf,2 ' in idealized form, the next
`duty cycle. Of course, other suitable duty cycles may be
`three lines from top to bottom show the signals at the Q
`chosen in practicing
`this invention.
`outputs of the correspondingly
`labelled
`flip-flops of
`In order to control the duty cycle of the clock applied
`time divider 42. As shown in FIG. 3, the output of 40 to clock input 18 of calculator 10 so as to maintain
`flip-flop C is at one-half
`the frequency of the clock
`synchronization between the power on and off cycles of
`calculator array 10 and the clock applied to its input
`signals, the output of flip-flop B as at one-quarter
`the
`18, the output of gate 47 is combined with the clock cf,2 '
`frequency of the clock signals and the output of flip-
`at a gate 60, and the output of gate 60 sets and resets a
`flop A is at one-eighth
`the frequency of the clock sig-
`nals from clock oscillator 40.
`45 flip-flop 62 whose two outputs provide the two comple-
`mentary clocks cf,1 and cf,2 for the controlled clock input
`starts unconditionally
`An execute mode operation
`upon the receipt of a key validation signal KEY from a
`18 of calculator array 10. As a result, flip-flop 62 is set
`circuit 44 (which is described
`and reset at the frequency of clock cf,/ only while
`in detail in Arnold and
`power is being applied to the controlled power input 16
`McLaughlin U.S. Pat. No. 3,792,466). At this time
`control signals DE and DI are low. A key validation 50 of calculator 10 from circuit 38.
`signal KEY from circuit 44 sets a Full Power flip-flop
`Referring to FIG. 3, the clock signals cf,1 and c/,2 from
`46 through a gate 45, and the resulting output of flip-
`the output of flip-flop 62 are applied to the clock input
`flop 46 sets a Power Control flip-flop 48 through a gate
`18 of calculator 10 at the frequency of clocks c/,1' and
`47. The resulting output of flip-flop 48 turns on switch
`cf,2 ', concurrently with the continuous power applied to
`38 through a switch 50, to thereby apply controlled 55 the power supply input 16 of calculator 10 during an
`power (at
`this time continuously)
`to the controlled
`execute mode operation. However, during a display
`power input 16 of calculator array 10 (FIG. 1 ).
`enable mode operation, only one clock pulse c/,1 and
`one clock pulse cf,2 are applied to calculator array 10
`At the end of an execute mode operation and the
`beginning of a display enable mode operation, control
`each time power is applied thereto,
`i.e. during a display
`signal DE goes high, control signal KEY is low, and 60 enable mode operation calculator array 10 is clocked
`control signal DI remains low. Full Power flip-flop 46 is
`at one-fourth
`the frequency at which it is clocked dur-
`therefore
`reset, and can no longer set Power Control
`ing an execute mode operation. During a display inhibit
`flip-flop 48. However, Power Control flip-flop 48 can
`mode operation, again a single clock pulse cf,1 and a
`single clock pulse q,2 are applied to the clock input 18
`now be set through gate 47 from the output of gate 52,
`two inputs - one is the AND function 65 of calculator array 10 each time power is applied to the
`which receives
`of the signals B and C from time divider 42, and the
`input 16 thereof,
`power supply
`i.e. the frequency at
`which calculator array 10 is clocked during a display
`other
`is either
`the complement of the signal A from
`time divider 42 or the complementary output of a flip-
`inhibit mode operation
`is one-eighth
`the frequency at
`
`MICROCHIP TECH. INC. - EXHIBIT 1015
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 007
`
`

`

`7
`which it is clocked during an execute mode operation.
`the control signal DO was not dis(cid:173)
`For simplicity,
`cussed in the above description of FIG. 2. This control
`signal is high periodically during operation of the calcu(cid:173)
`lator in either of its three modes to provide for periodic 5
`accessing of a dynamic readonly memory which forms
`a part of calculator array 10 and is used as a program
`ROM. Thus, when the control signal DO is high, the
`program ROM and the associated control logic for the
`next instruction are being set up in calculator array 10, 10
`but all other memories forming a part of array 10 are
`inhibited. The control signal DO, or its equivalent,
`is
`generated
`in prior art calculator arrays, e.g., the MOS
`Inc. Calculator Array 2521, and the cir(cid:173)
`Technology,
`cuits for its generation need not be discussed here. In 15
`the referenced
`calculator
`array,
`the period of the
`clocks tf,1 and tf,2 is about 6 microseconds, and the DO
`signal is high for about 36 microseconds once every
`approximately 330 microseconds.
`It should be clear
`that different
`time
`intervals can be chosen, and
`it 20
`should be clear that where a static program ROM is
`used in different calculator arrays, there would be no
`need for a control signal corresponding
`to DO.
`Referring to FIG. 2, when the control signal DO goes
`high, Power Control flip-flop 48 is set through gate 47, 25
`to apply full power to calculator array 10, and gate 60
`to continuously apply clocks tf,1 and tf,2 to
`is enabled
`calculator array 10. Furthermore,
`the setting and _reset(cid:173)
`ting of flip-flops 46 and 54 is related to the same con(cid:173)
`trol signal DO. Thus, the AND function of control 30
`signal DO and the complement of control signal DE as
`provided by a gate 43, is applied to the inputs of Full
`Power flip-flop 46 through gate 45 as shown in FIG. 2,
`and flip-flop 46 is clocked with the NANO function of
`the clock tf,1' and either the control signal KEY or the 35
`control signal DO, as provided by gates 64 and 66.
`the set and reset inputs of flip-flop 54 are
`Furthermore,
`controlled by gate 58 which provides the AND function
`of control signals DO, DE and the negation of control
`signal DI, and flip-flop 54 is clocked with the NANO 40
`function of clock signal tJ,i' and the control signal DO.
`However, as discussed above, the invention is equally
`applicable
`to a calculator array which has a static pro(cid:173)
`gram ROM and does not need a control signal of the
`type of control signal DO.
`In summary, the rate of power consumption of calcu(cid:173)
`lators embodying the invention is substantially reduced
`because only as much power is supplied to the calcula-
`tor as needed for each of the several different modes of
`operation. Specifically, high duty cycle power is ap- 50
`plied during an execute mode, when speed of operation
`is of the essence,
`intermediate
`duty cycle power
`is
`applied during a display mode, when maintaining dy(cid:173)
`namically stored
`information and preventing visible
`flicker of the display are of primary concern, and lower 55
`yet duty cycle power is applied during a display inhibit
`mode, when the only primary concern
`is the mainte(cid:173)
`nance of certain dynamically stored information. Any
`suitable duty cycles can be chosen for each of the three
`different operating modes, for example 100%, 25%, 60
`and 12½% duty cycles, or any other suitable combina(cid:173)
`tion of duty cycles. The high duty cycle need not be
`continuous power. Further
`in accordance with the in(cid:173)
`vention,
`the clocking of the calculator
`is maintained
`synchronous with
`the power duty cycles applied 65
`thereto. Still further in accordance with the invention,
`both
`the calculator array and the power and clock
`control array are parts of the same integrated circuit, to
`
`45
`
`3,941,989
`
`8
`ensure reliability and to lower the cost of implementing
`the invention.
`We claim:
`1. A method of reducing the power consumption rate
`of a calculator alternately operative
`in an execute
`mode in which new input information
`is processed
`in
`accordance with selected commands and is dynami(cid:173)
`cally stored
`in the calculator,
`in a display mode in
`which selected stored information
`is dynamically dis(cid:173)
`played, and in a display inhibit mode in which selected
`stored
`information
`is maintained
`in dynamic storage
`but is not displayed, a display mode operation following
`an execute mode operation and continuing either until
`a new execute mode operation or the elapsing of a
`selected time interval from its start, whichever occurs
`first, and a display inhibit mode operation occurring in
`the absence of an execute or a display mode operation,
`comprising
`the steps of: supplying the calculator with
`high duty cycle power concurrently with the operation
`thereof in the execute mode; supplying the calculator
`with an intermediate duty cycle power concurrently
`with the operation
`thereof
`in the display mode; and
`supplying the calculator with a low duty cycle power
`concurrently with the operation
`thereof in the display
`inhibit mode.
`2. A method as in claim 1 including the steps of:
`clocking the calculator at a high duty cycle clock rate
`during
`the operation
`thereof
`in the execute mode;
`clocking the calculator at an intermediate duty cycle
`clock rate during the operation
`thereof in the display
`mode; and clocking the calculator at a low duty cycle
`clock rate during the operation
`thereof in the display
`inhibit mode.
`3. A method as in claim 2 wherein the calculator
`is
`clocked with clock pulses which have substantially the
`same width for each of the operative modes of the
`calculator but which occur only while power is being
`supplied to the calculator during each of its different
`operative modes.
`4. A method as in claim 1 wherein the calculator
`is
`supplied with power at substantially 100% duty cycle
`during the operation thereof in the execute mode, 25%
`duty cycle during the operation
`thereof in the display
`mode and 12½% duty cycle during
`the operation
`thereof in the display inhibit mode.
`5. A calculator alternately operative
`in an execute
`mode in which input information is processed in accor(cid