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`Advanced Configuration and Power
`Interface Specification
`
`Intel
`Microsoft
`Toshiba
`Revision 1.0
`December 22, 1996
`
`Intel/Microsoft/Toshiba
`
`MICROCHIP TECH. INC. - EXHIBIT 1006
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 001
`
`

`

`Advanced Configuration and Power Management Specification
`
`ii
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`Copyright © 1996, Intel Corporation, Microsoft Corporation, Toshiba Corp.
`All rights reserved.
`
`INTELLECTUAL PROPERTY DISCLAIMER
`THIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER INCLUDING ANY
`WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY
`OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE.
`NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL
`PROPERTY RIGHTS IS GRANTED OR INTENDED HEREBY.
`INTEL, MICROSOFT, AND TOSHIBA, DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR
`INFRINGEMENT OF PROPRIETARY RIGHTS, RELATING TO IMPLEMENTATION OF INFORMATION IN
`THIS SPECIFICATION. INTEL, MICROSOFT, AND TOSHIBA, DO NOT WARRANT OR REPRESENT THAT
`SUCH IMPLEMENTATION(S) WILL NOT INFRINGE SUCH RIGHTS.
`
`
`
`Microsoft, Win32, Windows, and Windows NT are registered trademarks of Microsoft Corporation.
` I2C is a trademark of Phillips Semiconductors.
` All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.
`
`Intel/Microsoft/Toshiba
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`MICROCHIP TECH. INC. - EXHIBIT 1006
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`

`

`Introduction
`
`Contents
`
`1. INTRODUCTION
`
`1.1 Principal Goals
`
`1.2 Power Management Rationale
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`1.3 Legacy Support
`
`1.4 OEM Implementation Strategy
`
`1.5 Power and Sleep Buttons
`
`1.6 ACPI Specification and the Structure Of ACPI
`
`1.7 Minimum Requirements for OSPM/ACPI Systems
`
`1.8 Target Audience
`
`1.9 Document Organization
`1.9.1 ACPI Overview
`1.9.2 Programming Models
`1.9.3 Implementation Details
`1.9.4 Technical Reference
`
`1.10 Related Documents
`
`2. DEFINITION OF TERMS
`
`2.1 General ACPI Terminology
`
`2.2 Global System State Definitions
`
`2.3 Device Power State Definitions
`
`2.4 Sleeping State Definitions
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`2.5 Processor Power State Definitions
`
`3. OVERVIEW
`
`3.1 System Power Management
`
`3.2 Power States
`3.2.1 New Meanings for the Power Button
`3.2.2 Platform Power Management Characteristics
`3.2.2.1 Mobile PC
`3.2.2.2 Desktop PCs
`3.2.2.3 Multiprocessor and Server PCs
`
`3.3 Device Power Management
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`1-1
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`1-1
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`1-1
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`1-2
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`1-3
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`1-3
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`1-3
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`1-5
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`1-5
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`1-5
`1-6
`1-6
`1-6
`1-6
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`1-7
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`2-8
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`2-8
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`2-12
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`2-14
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`2-15
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`2-15
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`3-17
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`3-17
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`iv
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`Advanced Configuration and Power Management Specification
`
`3.3.1 Power Management Standards
`3.3.2 Device Power States
`3.3.3 Device Power State Definitions
`
`3.4 Controlling Device Power
`3.4.1 Getting Device Power Capabilities
`3.4.2 Setting Device Power States
`3.4.3 Getting Device Power Status
`3.4.4 Waking the Computer
`3.4.5 Example: Modem Device Power Management
`3.4.5.1 Getting the Modem‘s Capabilities
`3.4.5.2 Setting the Modem‘s Power State
`3.4.6 Getting the Modem‘s Power Status
`3.4.6.1 Waking the Computer
`
`3.5 Processor Power Management
`
`3.6 Plug and Play
`3.6.1 Example: Configuring the Modem
`
`3.7 System Events
`
`3.8 Battery Management
`3.8.1 CMBatt Diagram
`3.8.2 Battery Events
`3.8.3 Battery Capacity
`3.8.4 Battery Gas Gauge
`
`3.9 Thermal Management
`3.9.1 Active and Passive Cooling
`3.9.2 Performance vs. Silence
`3.9.2.1 Cooling Mode: Performance
`3.9.2.2 Cooling Mode: Silence
`3.9.3 Other Thermal Implementations
`3.9.4 Multiple Thermal Zones
`
`4. ACPI HARDWARE SPECIFICATION
`
`4.1 Fixed Hardware Programming Model
`
`4.2 Generic Programming Model
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`4.3 Diagram Legends
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`4.4 Register Bit Notation
`
`4.5 The ACPI Hardware Model
`4.5.1 Hardware Reserved Bits
`4.5.2 Hardware Ignored Bits
`4.5.3 Hardware Write-Only Bits
`4.5.4 Cross Device Dependencies
`4.5.4.1 Example 1
`4.5.4.2 Example 2
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`3-21
`3-21
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`3-22
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`3-23
`3-24
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`3-25
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`3-26
`3-26
`3-26
`3-27
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`3-29
`3-29
`3-30
`3-31
`3-31
`3-32
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`

`

`Introduction
`
`4.6 ACPI Features
`
`4.7 ACPI Register Model
`4.7.1 ACPI Register Summary
`4.7.1.1 PM1 Event Registers
`4.7.1.2 PM1 Control Registers
`4.7.1.3 PM2 Control Register
`4.7.1.4 PM Timer Register
`4.7.1.5 Processor Control Block
`4.7.1.6 General-Purpose Event Registers
`4.7.2 Required Fixed Features
`4.7.2.1 Power Management Timer
`4.7.2.2 Buttons
`4.7.2.3 Sleeping/Wake Control
`4.7.2.4 Real Time Clock Alarm
`4.7.2.5 Legacy/ACPI Select and the SCI Interrupt
`4.7.2.6 Processor Power State Control
`4.7.3 Fixed Feature Space Registers
`4.7.3.1 PM1 Event Grouping
`4.7.3.2 PM1 Control Grouping
`4.7.3.3 Power Management Timer (PM_TMR)
`4.7.3.4 Power Management 2 Control (PM2_CNT)
`4.7.3.5 Processor Register Block (P_BLK)
`4.7.4 Generic Address Space
`4.7.4.1 General-Purpose Register Blocks
`4.7.4.2 Example Generic Devices
`4.7.4.3 General-Purpose Register Blocks
`4.7.4.4 Specific Generic Devices
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`v
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`4-41
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`4-42
`4-45
`4-45
`4-46
`4-46
`4-46
`4-46
`4-46
`4-46
`4-46
`4-47
`4-51
`4-52
`4-53
`4-54
`4-59
`4-59
`4-62
`4-63
`4-64
`4-64
`4-65
`4-67
`4-68
`4-70
`4-72
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`5. ACPI SOFTWARE PROGRAMMING MODEL
`
`5-74
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`5.1 Overview of the System Description Table Architecture
`
`5.2 Description Table Specifications
`5.2.1 Reserved Bits and Fields
`5.2.1.1 Reserved Bits and Software Components
`5.2.1.2 Reserved Values and Software Components
`5.2.1.3 Reserved Hardware Bits and Software Components
`5.2.1.4 Ignored Hardware Bits and Software Components
`5.2.2 Root System Description Pointer
`5.2.3 System Description Table Header
`5.2.4 Root System Description Table
`5.2.5 Fixed ACPI Description Table
`5.2.6 Firmware ACPI Control Structure
`5.2.6.1 Global Lock
`5.2.7 Definition Blocks
`5.2.7.1 Differentiated System Description Table
`5.2.7.2 Secondary System Description Table
`5.2.7.3 Persistent System Description Table
`5.2.8 Multiple APIC Description Table
`5.2.8.1 Processor Local APIC
`5.2.8.2 IO APIC
`5.2.8.3 Platforms with APIC and Dual 8259 Support
`5.2.9 Smart Battery Table
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`Intel/Microsoft/Toshiba
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`5-74
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`5-76
`5-76
`5-76
`5-77
`5-77
`5-77
`5-77
`5-77
`5-78
`5-79
`5-84
`5-86
`5-87
`5-87
`5-88
`5-88
`5-88
`5-89
`5-90
`5-90
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`Advanced Configuration and Power Management Specification
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`5.3 ACPI Name Space
`5.3.1 Defined Root Names Spaces
`5.3.2 Objects
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`5.4 Definition Block Encoding
`
`5.5 Using the ACPI Control Method Source Language
`5.5.1 ASL Statements
`5.5.2 ASL Macros
`5.5.3 Control Method Execution
`5.5.3.1 Control Methods, Objects, and Operation Regions
`5.5.4 Control Method Arguments, Local Variables, and Return Values
`
`5.6 ACPI Event Programming Model
`5.6.1 ACPI Event Programming Model Components
`5.6.2 Types of ACPI Events
`5.6.2.1 Fixed ACPI Event Handling
`5.6.2.2 General-Purpose Event Handling
`5.6.3 Device Object Notifications
`5.6.4 Device Class-Specific Objects
`5.6.5 Defined Generic Object and Control Methods
`
`5.7 OS-Defined Object Names
`5.7.1 \_GL Global Lock Mutex
`5.7.2 \_OS Name object
`5.7.3 \_REV data object
`
`6. CONFIGURATION
`
`6.1 Device Identification Objects
`6.1.1 _ADR
`6.1.2 _CID
`6.1.3 _HID
`6.1.4 _SUN
`6.1.5 _UID
`
`6.2 Device Configuration Objects
`6.2.1 _CRS
`6.2.2 _DIS
`6.2.3 _PRT
`6.2.3.1 Example: Using _PRT to describe PCI IRQ routing
`6.2.4 _PRS
`6.2.5 _SRS
`
`6.3 Device Insertion and Removal Objects
`6.3.1 _EJD
`6.3.2 _EJx
`6.3.3 _LCK
`6.3.4 _RMV
`6.3.5 _STA
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`6.4 Resource Data Types for ACPI
`6.4.1 ASL Macros for Resource Descriptors
`6.4.2 Small Resource Data Type
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`Intel/Microsoft/Toshiba
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`5-92
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`

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`Introduction
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`6.4.2.1 IRQ Format (Type 0, Small Item Name 0x4, Length=2 or 3)
`6.4.2.2 DMA Format (Type 0, Small Item Name 0x5, Length=2)
`6.4.2.3 Start Dependent Functions (Type 0, Small Item Name 0x6, Length=0 or 1)
`6.4.2.4 End Dependent Functions (Type 0, Small Item Name 0x7, Length=0)
`6.4.2.5 I/O Port Descriptor (Type 0, Small Item Name 0x8, Length=7)
`6.4.2.6 Fixed Location I/O Port Descriptor (Type 0, Small Item Name 0x9, Length=3)
`6.4.2.7 Vendor Defined (Type 0, Small Item Name 0xE, Length=1-7)
`6.4.2.8 End Tag (Type 0, Small Item Name 0xF, Length 1)
`6.4.3 Large Resource Data Type
`6.4.3.1 24-Bit Memory Range Descriptor (Type 1, Large Item Name 0x1)
`6.4.3.2 Vendor Defined (Type 1, Large Item Name 0x4)
`6.4.3.3 32-Bit Memory Range Descriptor (Type 1, Large Item Name 0x5)
`6.4.3.4 32-Bit Fixed Location Memory Range Descriptor (Type 1, Large Item Name 0x6)
`6.4.3.5 Address Space Descriptors
`6.4.3.6 Extended Interrupt Descriptor (Type 1, Large Item Name 0x9)
`
`7. POWER MANAGEMENT
`
`7.1 Declaring a PowerResource Object
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`7.2 Device Power Management Objects
`7.2.1 _PRW
`7.2.2 _PR0
`7.2.3 _PR1
`7.2.4 _PR2
`
`7.3 Power Resources for OFF
`7.3.1 _IRC
`7.3.2 _PSW
`7.3.3 _PSC
`7.3.4 _PS0
`7.3.5 _PS1
`7.3.6 _PS2
`7.3.7 _PS3
`
`7.4 Defined Child Objects for a Power Resource
`7.4.1 _STA
`7.4.2 _ON
`7.4.3 _OFF
`
`7.5 OEM-Supplied System Level Control Methods
`7.5.1 \_PTS Prepare To Sleep
`7.5.2 System \_Sx states
`7.5.2.1 System \_S0 State (Working)
`7.5.2.2 System \_S1 State (Sleeping with Processor Context Maintained)
`7.5.2.3 System \_S2 State
`7.5.2.4 System \_S3 State
`7.5.2.5 System \_S4 State
`7.5.2.6 System \_S5 State (Soft Off)
`7.5.3 \_WAK (System Wake)
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`7-142
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`8. PROCESSOR CONTROL
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`8-145
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`viii
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`Advanced Configuration and Power Management Specification
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`8.1 Declaring a Processor Object
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`8.2 Processor Power States
`8.2.1 Processor Power State C0
`8.2.2 Processor Power State C1
`8.2.3 Processor Power State C2
`8.2.4 Processor Power State C3
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`8.3 Processor State Policy
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`9. WAKING AND SLEEPING
`
`9.1 Sleeping States
`9.1.1 S1 Sleeping State
`9.1.1.1 S1 Sleeping State Implementation (Example 1)
`9.1.1.2 S1 Sleeping State Implementation (Example 2)
`9.1.2 S2 Sleeping State
`9.1.2.1 S2 Sleeping State Implementation Example
`9.1.3 S3 Sleeping State
`9.1.3.1 S3 Sleeping State Implementation Example
`9.1.4 S4 Sleeping State
`9.1.4.1 OS Initiated S4 Transition
`9.1.4.2 The S4BIOS Transition
`9.1.5 S5 Soft Off State
`9.1.6 Transitioning from the Working to the Sleeping State
`9.1.7 Transitioning from the Working to the Soft Off State
`
`9.2 Flushing Caches
`
`9.3 Initialization
`9.3.1 Turning On ACPI
`9.3.2 BIOS Initialization of Memory
`9.3.3 OS Loading
`9.3.4 Turning Off ACPI
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`8-145
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`9-155
`9-157
`9-157
`9-159
`9-160
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`10. ACPI-SPECIFIC DEVICE OBJECTS
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`10-161
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`10.1 \_SI System Indicators
`10.1.1 _SST
`10.1.2 _MSG
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`10.2 Control Method Battery Device
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`10.3 Control Method Lid Device
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`10.4 Control Method Power and Sleep Button Devices
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`10.5 Embedded Controller Device
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`10.6 Fan Device
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`10.7 Generic Bus Bridge Device
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`10-163
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`Introduction
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`10.8 IDE Controller Device
`10.8.1 _STM
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`11. POWER SOURCE DEVICES
`
`11.1 Smart Battery Subsystems
`11.1.1 ACPI Smart Battery Charger Requirements
`11.1.2 ACPI Smart Battery Selector Requirements
`11.1.3 Smart Battery Objects
`11.1.4 Smart Battery Subsystem Control Methods
`11.1.4.1 Example Single Smart Battery Subsystem
`11.1.4.2 Example: Multiple Smart Battery Subsystem
`
`11.2 Control Method Batteries
`11.2.1 Battery Events
`11.2.2 Battery Control Methods
`11.2.2.1 _BIF
`11.2.2.2 _BST
`11.2.2.3 _BTP
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`11.3 AC Adapters and Power Source Objects
`11.3.1 _PSR
`11.3.2 _PCL
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`11.4 Power Source Name Space Example
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`11-171
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`11-172
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`12. THERMAL MANAGEMENT
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`12-173
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`12.1 Thermal Control
`12.1.1 Active, Passive, and Critical Policies
`12.1.2 Dynamically Changing Cooling Temperatures
`12.1.2.1 Resetting Cooling Temperatures from the User Interface
`12.1.2.2 Resetting Cooling Temperatures to Adjust to Bay Device Insertion or Removal
`12.1.2.3 Resetting Cooling Temperatures to Implement Hysteresis
`12.1.3 Hardware Thermal Events
`12.1.4 Active Cooling Strength
`12.1.5 Passive Cooling Equation
`12.1.6 Critical Shutdown
`
`12.2 Other Implementation Of Thermal Controllable Devices
`
`12.3 Thermal Control Methods
`12.3.1 _ACx
`12.3.2 _ALx
`12.3.3 _CRT
`12.3.4 _PSL
`12.3.5 _PSV
`12.3.6 _SCP
`12.3.7 _TC1
`12.3.8 _TC2
`12.3.9 _TMP
`12.3.10 _TSP
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`x
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`Advanced Configuration and Power Management Specification
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`12.4 Thermal Block and Name Space Example for One Thermal Zone
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`12.5 Controlling Multiple Fans in a Thermal Zone
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`12-179
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`12-179
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`13. ACPI EMBEDDED CONTROLLER INTERFACE SPECIFICATION
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`13-182
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`13.1 Embedded Controller Interface Description
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`13.2 Embedded Controller Register Descriptions
`13.2.1 Embedded Controller Status, EC_SC (R)
`13.2.2 Embedded Controller Command, EC_SC (W)
`13.2.3 Embedded Controller Data, EC_DATA (R/W)
`
`13.3 Embedded Controller Command Set
`13.3.1 Read Embedded Controller, RD_EC (0x80)
`13.3.2 Write Embedded Controller, WR_EC (0x81)
`13.3.3 Burst Enable Embedded Controller, BE_EC (0x82)
`13.3.4 Burst Disable Embedded Controller, BD_EC (0x83)
`13.3.5 Query Embedded Controller, QR_EC (0x84)
`
`13.4 SMBus Host Controller Notification Header (Optional), OS_SMB_EVT
`
`13.5 Embedded Controller Firmware
`
`13.6 Interrupt Model
`13.6.1 Event Interrupt Model
`13.6.2 Command Interrupt Model
`
`13.7 Embedded Controller Interfacing Algorithms
`
`13.8 Embedded Controller Description Information
`
`13.9 SMBus Host Controller Interface via Embedded Controller
`13.9.1 Register Description
`13.9.1.1 Status Register, SMB_STS
`13.9.1.2 Protocol Register, SMB_PRTCL
`13.9.1.3 Address Register, SMB_ADDR
`13.9.1.4 Command Register, SMB_CMD
`13.9.1.5 Data Register Array, SMB_DATA[i], i=0-31
`13.9.1.6 Block Count Register, SMB_BCNT
`13.9.1.7 Alarm Address Register, SMB_ALRM_ADDR
`13.9.1.8 Alarm Data Registers, SMB_ALRM_DATA[0], SMB_ALRM_DATA[1]
`13.9.2 Protocol Description
`13.9.2.1 Write Quick
`13.9.2.2 Read Quick
`13.9.2.3 Send Byte
`13.9.2.4 Receive Byte
`13.9.2.5 Write Byte
`13.9.2.6 Read Byte
`13.9.2.7 Write Word
`13.9.2.8 Read Word
`13.9.2.9 Write Block
`13.9.2.10 Read Block
`13.9.2.11 Process Call
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`13-185
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`13-187
`13-188
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`13-189
`13-189
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`13-190
`13-191
`13-191
`13-192
`13-192
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`13-193
`13-193
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`13-194
`13-194
`13-194
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`Introduction
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`13.9.3 SMBus Register Set
`
`13.10 SMBus Devices
`13.10.1 SMBus Device Access Restrictions
`13.10.2 SMBus Device Command Access Restriction
`
`13.11 Defining an Embedded Controller Device in ACPI Name Space
`13.11.1 Example EC Definition ASL Code
`
`13.12 Defining an EC SMBus Host Controller in ACPI Name Space
`13.12.1 Example EC SMBus Host Controller ASL-Code
`
`14. QUERY SYSTEM ADDRESS MAP
`
`14.1 INT 15H, E820H - Query System Address Map
`
`14.2 Assumptions and Limitations
`
`14.3 Example Address Map
`
`14.4 Sample Operating System Usage
`
`xi
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`13-197
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`13-198
`13-198
`13-198
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`13-198
`13-199
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`13-199
`13-199
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`14-201
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`14-201
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`14-202
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`14-203
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`14-203
`
`15. ACPI SOURCE LANGUAGE (ASL) REFERENCE
`
`15-205
`
`15.1 ASL Language Grammar
`15.1.1 ASL Grammar Notation
`15.1.2 ASL Names
`15.1.3 ASL Language and Terms
`
`15.2 Full ASL Reference
`15.2.1 ASL Names
`15.2.2 ASL Data Types
`15.2.3 ASL Terms
`15.2.3.1 Definition Block Term
`15.2.3.2 Compiler Directive Terms
`15.2.3.3 Data Object Terms
`15.2.3.4 Declaration Terms
`15.2.3.5 Operator Terms
`15.2.3.6 Type 2 Macros
`
`15-205
`15-205
`15-207
`15-207
`
`15-216
`15-216
`15-216
`15-217
`15-217
`15-217
`15-218
`15-220
`15-236
`15-250
`
`16. ACPI MACHINE LANGUAGE (AML) SPECIFICATION
`
`16-251
`
`16.1 Notation Conventions
`
`16.2 AML Grammar Definition
`16.2.1 Names
`16.2.2 Declarations
`16.2.3 Operators
`
`16.3 AML Byte Stream Byte Values
`
`16.4 Examples
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`xii
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`Advanced Configuration and Power Management Specification
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`16.4.1 Relationship Between ASL, AML, and Byte Streams
`
`16.5 AML Encoding of Names in the Name Space
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`16-261
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`Introduction
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`1. Introduction
`The Advanced Configuration and Power Interface (ACPI) specification is the key element in Operating System
`Directed Power Management (OSPM). OSPM and ACPI both apply to all classes of computers, explicitly
`including desktop, mobile, home, and server machines.
`
`ACPI evolves the existing collection of power management BIOS code, APM APIs, PNPBIOS APIs, and so on
`into a well-specified power management and configuration mechanism. It provides support for an orderly
`transition from existing (legacy) hardware to ACPI hardware, and it allows for both mechanisms to exist in a
`single machine and be used as needed.
`
`Further, new system architectures are being built that stretch the limits of current Plug and Play interfaces.
`ACPI evolves the existing motherboard configuration interfaces to support these advanced architectures in a
`more robust, and potentially more efficient manner.
`
`This document describes the structures and mechanisms necessary to move to operating system (OS) directed
`power management and enable advanced configuration architectures — that is, the structures and mechanisms
`necessary to implement ACPI-compatible hardware and to use that hardware to implement OSPM support.
`
`1.1 Principal Goals
`ACPI is the key element in implementing OSPM. ACPI is intended for wide adoption to encourage hardware
`and software vendors to build ACPI-compatible (and, thus, OSPM-compatible) implementations.
`
`The principal goals of ACPI and OSPM are to:
`1. Enable all PCs to implement motherboard configuration and power management functions, using
`appropriate cost/function tradeoffs.
` PCs include mobile, desktop, workstation, server, and home machines.
` Machine implementers have the freedom to implement a wide range of solutions, from the very simple
`to the very aggressive, while still maintaining full OS support.
` Wide implementation of power management will make it practical and compelling for applications to
`support and exploit it. It will make new uses of PCs practical and existing uses of PCs more
`economical.
`
`2. Enhance power management functionality and robustness.
` Power management policies too complicated to implement in a ROM BIOS can be implemented and
`supported in the OS, allowing inexpensive power managed hardware to support very elaborate power
`management policies.
` Gathering power management information from users, applications, and the hardware together into the
`OS, will enable better power management decisions and execution.
` Unification of power management algorithms in the OS will reduce opportunities for miscoordination
`and will enhance reliability.
`3. Facilitate and accelerate industry-wide implementation of power management.
` OSPM and ACPI will reduce the amount of redundant investment in power management throughout the
`industry, as this investment and function will be gathered into the OS. This will allow industry
`participants to focus their efforts and investments on innovation rather than simple parity.
` The OS can evolve independently of the hardware, allowing all ACPI-compatible machines to gain the
`benefits of OS improvements and innovations.
` The hardware can evolve independently from the OS, decoupling hardware ship cycles from OS ship
`cycles and allowing new ACPI-compatible hardware to work well with prior ACPI-compatible
`operating systems.
`4. Create a robust interface for configuring motherboard devices.
` Enable new advanced designs not possible with existing interfaces.
`
`1.2 Power Management Rationale
`It is necessary to move power management into the OS and to use an abstract interface (ACPI) between the OS
`and the hardware to achieve the principal goals set forth above.
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`Advanced Configuration and Power Management Interface Specification
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` Today, power management only exists on a subset of PCs. This inhibits application vendors from
`supporting or exploiting it.
` Moving power management functionality into the OS makes it available on every machine that the OS
`is installed on. The level of functionality (power savings, etc) will vary from machine to machine, but
`users and applications will see the same power interfaces and semantics on all OSPM machines.
` This will enable application vendors to invest in adding power management functionality to their
`products.
` Today, power management algorithms are restricted by the information available to the BIOS that
`implements them. This limits the functionality that can be implemented.
` Centralizing power management information and directives from the user, applications, and hardware
`in the OS allows implementation of more powerful functionality. For example, an OS could have a
`policy of dividing I/O operations into normal and lazy. Lazy I/O operations (such as a word processor
`saving files in the background) would be gathered up into clumps and done only when the required I/O
`device is powered up for some other reason. A non-lazy I/O request when the required device was
`powered down would cause the device to be powered up immediately, the non-lazy I/O request to be
`carried out, and any pending lazy I/O operations to be done. Such a policy requires knowing when I/O
`devices are powered up, knowing which application I/O requests are lazy, and being able to assure that
`such lazy I/O operations do not starve.
` Appliance functions, such as answering machines, require globally coherent power decisions. For
`example, a telephone answering application could call the OS and assert, ―I am waiting for incoming
`phone calls; any sleep state the system enters must allow me to wake up and answer the telephone in 1
`second.‖ Then, when the user presses the ―off‖ button, the system would pick the deepest sleep state
`consistent with the needs of the phone answering service.
` BIOS code has become very complex to deal with power management, it is difficult to make work with an
`OS and is limited to static configurations of the hardware.
` There is much less state for the BIOS to retain and manage (because the OS manages it).
` Power management algorithms are unified in the OS, yielding much better integration between the OS
`and the hardware.
` Because additional ACPI tables are loaded when docks, and so on are connected to the system, the OS
`can deal with dynamic machine configurations.
` Because the BIOS has fewer functions and they are simpler, it is much easier (and, therefore, cheaper)
`to implement.
` The existing structure of the PC platform constrains OS and hardware designs.
` Because ACPI is abstract, the OS can evolve separately from the hardware and, likewise, the hardware
`from the OS.
` ACPI is by nature more portable across operating systems and processors. ACPI‘s command methods
`allow very flexible implementations of particular features.
`
`1.3 Legacy Support
`ACPI provides support for an orderly transition from legacy hardware to ACPI hardware, and allows for both
`mechanisms to exist in a single machine and be used as needed.
`
`Table 1-1 Hardware Type vs. OS Type Interaction
`
`Hardware \ OS
`Legacy hardware
`
`Legacy OS
`A legacy OS on legacy hardware
`does what it always did.
`
`Legacy and ACPI
`hardware support in
`machine
`
`ACPI-only hardware
`
`
`It works just like a legacy OS on
`legacy hardware.
`
`There is no power management.
`
`OSPM/ACPI OS
`If the OS lacks legacy support, legacy
`support is completely contained within the
`hardware functions.
`During boot, the OS tells the hardware to
`switch from legacy to OSPM/ACPI mode
`and from then on the system has full
`OSPM/ACPI support.
`There is full OSPM/ACPI support.
`
`
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`1-3
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`Planned future versions of the Microsoft® Windows 95® and Windows NT® operating systems are examples of
`ACPI-compatible operating systems categorized in the right-most column of the previous table. Future ACPI-
`compatible versions of Windows 95 will provide the same legacy support as the current version of Windows 95.
`
`1.4 OEM Implementation Strategy
`Any OEM is, as always, free to build hardware as they want. Given the existence of the ACPI specification, two
`general implementation strategies are possible.
` An OEM can adopt the OS vendor-provided ACPI driver and implement the hardware part of the ACPI
`specification (for a given platform) in one of many possible ways.
` An OEM can develop a driver and hardware that are not ACPI-compatible. This strategy opens up even
`more hardware implementation possibilities. However, OEMs who implement hardware that is OSPM-
`compatible but not ACPI-compatible will bear the cost of developing, testing, and distributing drivers for
`their implementation.
`
`1.5 Power and Sleep Buttons
`OSPM provides a new appliance interface to consumers. In particular, it provides for a sleep button that is a
`―soft‖ button that does not turn the machine physically off but signals the OS to put the machine in a soft off or
`sleeping state. ACPI defines two types of these ―soft‖ buttons: one for putting the machine to sleep and one for
`putting the machine in soft off.
`This gives the OEM two different ways to implement machines: A one button model or a two button model.
`The one button model has a single button that can be used as a power button or a sleep button as determined by
`user settings. The two-button model has an easily accessible sleep button and a separate power button. In either
`model, an override feature that forces the machine off or reset without OS consent is also needed to deal with
`various rare, but problematic, situations.
`
`1.6 ACPI Specification and the Structure Of ACPI
`This specification defines the ACPI interfaces; that is, the interfaces between the OS software, the hardware, and
`BIOS software. This specification also defines the semantics of these interfaces.
`
`Figure 1-1 lays out the software and hardware components relevant to ACPI and how they relate to each other.
`This specification describes the interfaces between components, the contents of the ACPI Tables, and the related
`semantics of the other ACPI components. Note that the ACPI Tables, which describe a particular platform‘s
`hardware, are at heart of the ACPI implementation and the role of the ACPI BIOS is primarily to supply the
`ACPI Tables (rather than an API).
`
`ACPI is not a software specification, it is not a hardware specification, although it addresses both software and
`hardware and how they must behave. ACPI is, instead, an interface specification.
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`Advanced Configuration and Power Management Interface Specification
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`1-4
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`. I
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`I
`
`
`
`Figure 1-1 OSPM/ACPI Global System
`
`There are three runtime components to ACPI:
` ACPI Tables - These tables describe the interfaces to the hardware. Some descriptions limit what can be
`built (for example, some controls are embedded in fixed blocks of registers, and the table specifies the
`address of the register block). Most descriptions allow the hardware to be built in arbitrary ways, and can
`describe arbitrary operation sequences needed to make the hardware function. ACPI Tables can make use of
`a p-code type of language, the interpretation of which is performed by the OS. That is, the OS contains and
`uses an AML interpreter that executes procedures encoded in AM and stored in the ACPI tables; ACPI
`Machine Language (AML) is a compact, tokenized, abstract kind of machine language.
` ACPI Registers - The constrained part of the hardware interface, described (at least in location) by the
`ACPI Tables.
` ACPI BIOS - Refers to the portion of the firmware that is compatible with the ACPI specifications.
`Typically, this is the code that boots the machine (as legacy BIOSs have done) and implements interfaces
`
`
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`Intel/Microsoft/Toshiba
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`Applications
`
`OS
`Dependent
`Application
`APIs
`
`Kernel
`
`OSPM System Code
`
`Device
`Driver
`
`ACPI Driver/
`AML Interpreter
`
`OS Specific
`technologies,
`interfaces, and code.
`
`ACPI
`Register
`Interface
`
`ACPI Table
`Interface
`
`ACPI BIOS
`Interface
`
`OS
`Independent
`technologies,
`interfaces,
`code, and
`hardware.
`
`ACPI Registers
`
`ACPI BIOS
`
`ACPI Tables
`
`Existing
`industry
`standard
`register
`interfaces to:
`CMOS, PIC,
`PITs, ...
`
`Platform Hardware
`
`BIOS
`
`- ACPI Spec Cov ers this area.
`- OS specific technology, not part of ACPI.
`- Hardw are/Platform specific technology, not part of ACPI.
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`Introduction
`
`1-5
`
`for sleep, wake, and some restart operations. It is called rarely, compared to a legacy BIOS. The ACPI
`Description Tables are also provided by the ACPI BIOS. Note that in the figure above, the boxes labeled
`―BIOS‖ and ―ACPI BIOS‖ refer to the same component on a platform; the box labeled ―ACPI BIOS‖ is
`broken out to emphasize that a portion of the BIOS is compatible with the ACPI specifications.
`
`1.7 Minimum Requirements for OSPM/ACPI Systems
`
`The minimum requirements for an OSPM/ACPI-compatible system are:
` A power-management timer (for more information, see section 4.7.2.1).
` A power or sleep button (for more information, see section 4.7.2.2).
` A real time clock wakeup alarm, (for more information, see section 4.7.2.4).
`
`Implementation of at least one system sleep state (for more information, see section 9.1).
`
`Interrupt events generate System Control Interrupts (SCIs) and the GP_STS hardware registers are
`implemented (for more information, see section 4.7.4.3).
` A Descriptio