I 1111111111111111 11111 1111111111 11111 11111 1111111111 111111111111111 IIII IIII
`US007870404B2
`
`c12) United States Patent
`Read et al.
`
`(IO) Patent No.:
`(45) Date of Patent:
`
`US 7,870,404 B2
`Jan. 11, 2011
`
`(54) TRANSITIONING TO AND FROM A SLEEP
`STATE OF A PROCESSOR
`
`(76)
`
`Inventors: Andrew Read, 1621 Eagle Dr.,
`Sunnyvale, CA (US) 94087; Sameer
`Halepete, 373 River Oaks Cir., #1608,
`San Jose, CA (US) 95134; Keith
`Klayman, 613 San Conradoter #2,
`Sunnyvale, CA (US) 94086
`
`( *) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 378 days.
`
`(21) Appl. No.: 11/894,991
`
`(22) Filed:
`
`Aug. 21, 2007
`
`(65)
`
`Prior Publication Data
`
`US 2007/0294555 Al
`
`Dec. 20, 2007
`
`Related U.S. Application Data
`
`(62) Division of application No. 09/694,433, filed on Oct.
`23, 2000, now Pat. No. 7,260,731.
`
`(51)
`
`Int. Cl.
`(2006.01)
`G06F 1132
`(52) U.S. Cl. ....................................... 713/320; 713/323
`(58) Field of Classification Search ................. 713/320,
`713/323
`See application file for complete search history.
`
`(56)
`
`References Cited
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`(Continued)
`
`Primary Examiner-Chun Cao
`
`(57)
`
`ABSTRACT
`
`A method for reducing power utilized by a processor includ(cid:173)
`ing determining that a processor is transitioning from a com(cid:173)
`puter mode to a mode in which system clock to the processor
`is disabled, and reducing core voltage to the processor to a
`value sufficient to maintain state during the mode in which
`system clock is disabled.
`
`21 Claims, 2 Drawing Sheets
`
`voltage regulator 11
`hi-eff/
`cont-.---------.---1SO
`
`---12
`
`51
`
`control
`
`bidirectional
`- - - - charge pump 53
`
`core
`voltage
`
`MICROCHIP TECH. INC. - EXHIBIT 1001
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 001
`
`

`

`US 7,870,404 B2
`Page 2
`
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`
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`(ICH3-M)" Datasheet; Jul. 2001.
`* cited by examiner
`
`MICROCHIP TECH. INC. - EXHIBIT 1001
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 002
`
`

`

`U.S. Patent
`
`Jan. 11, 2011
`
`Sheet 1 of 2
`
`US 7,870,404 B2
`
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`MICROCHIP TECH. INC. - EXHIBIT 1001
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 003
`
`

`

`U.S. Patent
`
`Jan. 11, 2011
`
`Sheet 2 of 2
`
`US 7,870,404 B2
`
`[',.
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`
`13 7
`l
`I
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`
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`
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`
`voltage regulator
`
`12
`
`core voltage
`
`11
`
`Figure 3
`
`40
`
`-----112
`
`voltage regulator
`
`core voltage
`
`feed
`backi-----1
`11
`
`41
`
`stop_clock ---!
`
`Figure 4
`
`voltage regulator 11
`hi-eff/
`conf,..._-'----t--"1SO
`
`---"112
`
`51
`
`control
`
`core
`~ voltage
`
`Figure 5
`
`MICROCHIP TECH. INC. - EXHIBIT 1001
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 004
`
`

`

`US 7,870,404 B2
`
`1
`TRANSITIONING TO AND FROM A SLEEP
`STATE OF A PROCESSOR
`
`RELATED APPLICATION
`
`2
`significant when a processor functions in the deep sleep mode
`as much as ninety percent of the time. As process technolo(cid:173)
`gies continue to shrink in dimension and lower operating
`voltages, this static power increases due to lower threshold
`5 voltages and thinner gate oxides.
`It is desirable to furnish apparatus and methods for reduc(cid:173)
`ing the power use of a processor in the state in which its clocks
`are disabled.
`
`SUMMARY OF THE INVENTION
`
`This application is a Divisional Application of co-pending,
`commonly owned U.S. patent application Ser. No. 09/694,
`433, attorney docket TRAN-P059, filed Oct. 23, 2000 now
`U.S. Pat. No. 7,260,731, entitled "SAVING POWER WHEN
`INOR TRANSITIONINGTOASTATICMODEOFAPRO- 10
`CESSOR" to Read et al., which is hereby incorporated herein
`by reference in its entirety.
`
`BACKGROUND OF THE INVENTION
`
`The present invention is realized by a method for reducing
`power utilized by a processor including the steps of determin(cid:173)
`ing that a processor is transitioning from a computing mode to
`15 a mode in which system clock to the processor is disabled,
`and reducing core voltage to the processor to a value sufficient
`to maintain state during the mode in which system clock is
`disabled.
`These and other features of the invention will be better
`20 understood by reference to the detailed description which
`follows taken together with the drawings in which like ele(cid:173)
`ments are referred to by like designations throughout the
`several views.
`
`1. Field of the Invention
`This invention relates to computer systems and, more par(cid:173)
`ticularly, to apparatus and methods for reducing power use by
`a computer system during intervals in which processing is
`stopped.
`2. History of the Prior Art
`As computer processors have increased in ability, the num(cid:173)
`ber of transistors utilized has increased almost exponentially.
`This increase in circuit elements has drastically increased the
`power requirements of such processors. As the need of power 25
`increases, the temperature at which a computer operates
`increases and the battery life of portable computers decreases.
`The loss of battery life with modern portable computers
`greatly reduces the time during which the computer can func(cid:173)
`tion as a portable device. In fact, the power usage has become 30
`so great that even with significant reduction in the process
`size utilized, a plethora of techniques have been implemented
`to reduce power usage to maintain the efficacy of portable
`computers.
`One of these techniques monitors the use of the various
`devices within the computer and disables those devices that
`have not been utilized for some period. Because the processor
`utilizes a significant amount of the power ( e.g., 50%) used by
`a portable computer, this technique is utilized to disable the
`processor itself when its processing requirements are unused 40
`for some interval. In the typical case, disabling the processor
`is accomplished by terminating the system clocks furnished
`to the processor. When processor clocks have been disabled,
`controlling circuitry (typically a portion of the "Southbridge"
`circuitry of an X86-processor-based computer) remains 45
`enabled to detect interrupts requiring processor operation.
`The receipt of such an interrupt causes the controlling cir(cid:173)
`cuitry to once again enable clocks to the processor so that the
`processor may take whatever steps are necessary to handle the
`basis of the interrupt.
`The technique of disabling the processor reduces signifi(cid:173)
`cantly the dissipation of power caused by the operation of the
`processor even at a low frequency. In fact, the technique
`works quite well; and it is estimated that with many portable
`computers the processor is placed in the state in which system 55
`clocks are disabled during approximately ninety percent of
`the operation of the computer. However, use of this technique
`emphasizes another aspect of power loss using advanced
`processors. When system clocks for a processor are disabled,
`the processor must remain in a state (sometimes called "deep 60
`sleep") in which it is capable of rapidly responding to inter(cid:173)
`rupts. Such a state requires the application of core voltage to
`the various circuits. The application of this voltage generates
`a power dissipation referred to in this specification as "static
`power" usage because the processor is in its static state in 65
`which clocks are disabled. To date there has been little atten-
`tion paid to this static power usage. However, the usage is very
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a diagram illustrating current-voltage character(cid:173)
`istics of CMOS transistor devices utilized in microproces(cid:173)
`sors.
`FIG. 2 is another diagram illustrating current-voltage char(cid:173)
`acteristics of CMOS transistor devices utilized in micropro(cid:173)
`cessors.
`FIG. 3 is a circuit diagram illustrating a first circuit
`35 designed in accordance with the present invention for reduc(cid:173)
`ing static power usage.
`FIG. 4 is a circuit diagram illustrating a second circuit
`designed in accordance with the present invention for reduc(cid:173)
`ing static power usage.
`FIG. 5 is another circuit diagram illustrating a circuit
`designed in accordance with the present invention for reduc(cid:173)
`ing static power usage.
`
`DETAILED DESCRIPTION
`
`FIG. 1 is a first diagram displaying a number of curves
`illustrating the current-voltage characteristics of CMOS tran(cid:173)
`sistor devices utilized in the circuits of a microprocessor. This
`first diagram utilizes a linear scale for both current and volt-
`50 age. As may be seen, each of the curves illustrates that the
`drain-to-source current of a transistor is essentially nonexist(cid:173)
`ent until the voltage at the gate terminal of the transistor is
`raised to a threshold voltage. Once the threshold voltage of
`the transistor is reached, drain-to-source current increases
`either linearly or quadratically depending on whether the
`transistor is in the linear region or saturation region of opera-
`tion.
`Although the diagram of FIG. 1 appears to illustrate that
`current flowing below the threshold value of the gate voltage
`is insignificant, this is not the case in some situations. FIG. 2
`illustrates current versus voltage curves of the typical transis-
`tor device below the threshold voltage with the voltage being
`plotted on a log scale. As may be seen, current in fact flows
`below the threshold voltage. If a transistor functions in the
`state below the threshold voltage for ninety percent of com(cid:173)
`puter processor operation, then this current has a significant
`affect on power usage by the processor.
`
`MICROCHIP TECH. INC. - EXHIBIT 1001
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 005
`
`

`

`US 7,870,404 B2
`
`3
`Since a processor is not capable of computing in the mode
`in which its clocks are disabled, it would at first glance appear
`that the solution would be to terminate the application of
`voltage to the processor. However, as suggested above, it is
`necessary that the processor be maintained in a condition in 5
`which it can respond rapidly to interrupts provided by the
`circuitry that controls application of the system clocks. To do
`this, the processor must maintain state sufficient to immedi(cid:173)
`ately return to an operating condition. Thus, prior art proces(cid:173)
`sors have been provided sufficient voltage to maintain such 10
`state and to keep their transistors ready to immediately
`respond to interrupts. In general, this has been accomplished
`by maintaining the processor core voltage at the same level as
`the operating voltage. With most prior art processors, the core
`voltage used by a processor is selected by use of motherboard 15
`switches or setup software at a level sufficient to provide the
`highest frequency operations specified for the particular pro(cid:173)
`cessor. For example, many processors provide 1.8 volts as a
`core voltage. On the other hand, the voltage required to main(cid:173)
`tain state in a deep sleep mode may be significantly less, e.g., 20
`one volt or less. Since such processors function at the same
`voltage whether in a computing or a deep sleep mode, a
`significant amount of unnecessary power may be expended.
`In one typical state of the art X86 processor, the power usage
`averages approximately one-half watt in the deep sleep state 25
`because of the leakage illustrated by the diagram of FIG. 2.
`The present invention reduces the voltage applied to the
`processor significantly below the lowest voltage normally
`furnished as a core voltage for the processor during the mode
`in which system clocks are disabled thereby reducing the 30
`power utilized by the processor in the deep sleep state.
`FIG. 3 is a circuit diagram illustrating a first embodiment of
`the invention. In the circuit 10 illustrated, a switching voltage
`regulator 11 receives an input signal at a terminal 12 which
`determines its output voltage value. Most modern processors 35
`utilize a voltage regulator which is capable of furnishing a
`range of core voltages for operating transistors; a typical
`regulator may furnish a range of voltages between2 and0.925
`volts from which a particular core voltage may be selected for
`operation. Typically, a binary signal is provided a the terminal 40
`12 which selects the particular output voltage level to be
`furnished by the regulator 11; in such a case, a number of
`individual pins may be utilized as the terminal 12.
`Recently, a new power saving technique has been utilized
`which dynamically adjusts both the voltage and operating 45
`frequency to a level sufficient to maintain computing opera(cid:173)
`tions being conducted by a processor. The technique which
`offers significant power savings is described in detail in U.S.
`patent application Ser. No. 09/484,516, filed Jan. 18, 2000,
`entitled Adaptive Power Control, assigned to the assignee of 50
`the present invention. A processor which utilizes this tech(cid:173)
`nique monitors operations within the processor to determine
`the frequency level at which the processor should operate.
`Depending on the particular operations being carried out by
`the processor, the value furnished at the terminal 12 of a 55
`regulator functioning in such a system will cause the regulator
`to produce an output voltage at some level between the high
`and low values necessary for the particular processor to carry
`out computing functions.
`In the circuit of FIG. 3, input to the terminal 12 is furnished 60
`via a circuit 13 such as a multiplexor that is capable of pro(cid:173)
`viding one or more input values. In the embodiment illus(cid:173)
`trated, a value is provided at a first input 14 to the circuit 13 by
`the processor ( or other circuitry) which determines the oper(cid:173)
`ating condition of the processor in its computing range; and a 65
`second value is provided at a second input 15 which is
`selected especially for the deep sleep condition. Either of
`
`4
`these input values may be selected by a control signal pro(cid:173)
`vided at a control terminal 16 of the circuit 13. In one embodi(cid:173)
`ment, a system control signal normally utilized to signal entry
`into the deep sleep condition (a stop clock signal) is used as
`the control signal to be furnished at the control terminal 16.
`This control signal selects the input value furnished at the
`input 15 which is especially chosen to cause a typical prior art
`regulator 11 to produce a voltage output for operating the
`processor in the deep sleep mode. In one embodiment of the
`invention, the value furnished for deep sleep mode is chosen
`to cause the regulator 11 to produce the lowest voltage pos(cid:173)
`sible in its range of output voltages. In one exemplary pro(cid:173)
`cessor that utilizes the technique described in the above(cid:173)
`mentioned patent application, the processor is specified as
`capable of conducting computing operations in a core voltage
`range from a low voltage of 1.2 volts to a high voltage of 1.6
`volts. On the other hand, the processor when operating in
`deep sleep mode has no problem maintaining that state nec(cid:173)
`essary to resume computing even though functioning at a core
`voltage of0.925 volts, the lowest voltage which the regulator
`can provide. Thus, although the voltage regulator 11 may
`typically provide a range of varying output voltage levels, the
`lowest voltage at which a processor is specified for conduct(cid:173)
`ing computing operations is typically significantly above the
`lowest value which the regulator is capable of furnishing.
`In order to reduce power usage in one embodiment of the
`present invention, in response to a control signal indicating
`that the processor is about to go into the deep sleep state, the
`value at the input 15 is furnished by the circuit 13 to the
`regulator causing the regulator 11 to generate its lowest pos(cid:173)
`sible output voltage level for the deep sleep condition. In one
`exemplary embodiment, the high and low voltages generated
`in a computing mode are 1.6 volts and 1.2 volts while the deep
`sleep voltage is 0.925 volts.
`Although the voltage level furnished by the regulator 11 for
`the deep sleep mode of the processor might appear to be only
`slightly lower than that furnished in the lowest operating
`condition for the exemplary processor, the reduction in power
`usage is quite significant. Because both the voltage and the
`leakage current are reduced, the reduction in power is
`approximately equal to the ratio in voltage levels raised to the
`power of about three to four. Over any period of processor use
`involving the deep sleep state, such a reduction is quite large.
`One problem with this approach to reducing power is that
`it does not reduce the voltage level as far as might be possible
`and, thus, does not conserve as much power as could be saved.
`This approach only reduces the voltage level to the lowest
`level furnished by the regulator. This voltage is significantly
`greater than appears to be necessary for a processor which
`also dynamically regulates voltage furnished during comput(cid:173)
`ing operations to save power. Two criteria control the level to
`which the core voltage may be reduced in deep sleep. The
`level must be sufficient to maintain state that the processor
`requires to function after returning from the deep sleep state.
`The level must be one that can be reached during the times
`allowed for transition to and from the deep sleep mode.
`The first criterion is met so long as values of state stored are
`not lost during the deep sleep mode. Tests have shown that a
`core voltage significantly below one-half volt allows the
`retention of the memory state of a processor. Thus, using this
`criterion, it would be desirable to reduce the core voltage to a
`value such as one-half volt or lower.
`However, depending on system configuration, the time
`allowed to transition to and from deep sleep in an X86 pro(cid:173)
`cessor can be as low as 50 microseconds. Depending on the
`
`MICROCHIP TECH. INC. - EXHIBIT 1001
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 006
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`capacitive load of the particular circuitry, a voltage variation
`of about 0.5 to 0.6 volts may take place during this time in one
`exemplary configuration.
`Thus, if the exemplary processor is operating at its lowest
`processing core voltage of 1.2 volts, its core voltage may be
`lowered in the time available to 0.6-0.7 volts. On the other
`hand, if the processor is operating at a processing core voltage
`of 1.5 volts, its core voltage may only be lowered in the time
`available to 0.9-1 volts. Consequently, it is desirable that the
`core voltage furnished during deep sleep be lowered to a level
`which may be below the level provided by a typical voltage
`regulator but which varies depending on the core operating
`voltage from which it transitions.
`This desirable result may be reached utilizing a circuit such
`as that described in FIG. 4. The circuit of FIG. 4 includes a
`feedback network 41 for controlling the level of voltage at the
`output of the regulator 11. Prior art regulators such as the
`Maxim 1711 provide a feedback terminal and describe how
`that terminal may be utilized with a resistor-voltage-divider
`network joined between the output terminal and ground to
`raise the output voltage level.
`The embodiment of the present invention illustrated in
`FIG. 4 utilizes the same feedback terminal and a similar
`resistor-voltage-divider network but
`joins
`the divider
`between the output terminal and a source of voltage 42 higher
`than the normal output voltage of the regulator to force the
`output voltage level to a lower value rather than a higher level.
`The particular source voltage and the particular resistor val(cid:173)
`ues may be selected to cause the voltage level at the output of
`the regulator to drop from a particular output value to a
`desired value such as 0.6 volts when transitioning from a
`computing level of 1.2 volts.
`By appropriate choice of the resistor values of the divider
`network 41 and the source 42, the voltage drop provided by
`such a divider network accomplishes the desired result of
`providing an output voltage for the deep sleep mode of opera(cid:173)
`tion that varies from the previous processor computing core
`voltage by an amount attainable during the transition period
`available. In one embodiment, resistor 43 was chosen to be 1
`Kohms, resistor 45 to be 2.7 Kohms, and source 42 to be 3.3
`volts. Such values cause the voltage drop into deep sleep
`mode to be between 0.5 and 0.6 volts whether beginning at
`core voltages of 1.2 or 1.6 volts. On the other hand, by using
`a higher value of voltage at source 45 and adjusting the values
`of resistors 41 and 43, the increments of voltage drop reached 45
`from different starting voltages to final deep sleep voltage
`values at the terminal 12 may be brought closer to one
`another.
`It should be noted that the circuitry of FIGS. 3 and 4 may be
`combined so that both input selection and output adjustment 50
`are both used to adjust the core voltage value produced by a
`voltage regulator for deep sleep mode in particular instances
`where the load capacitance is relatively low.
`Prior art voltage regulators function in at least two different
`modes of operation. A first mode of operation is often referred 55
`to as "low noise" or "continuous" mode. In this mode, the
`regulator responds as rapidly as possible to each change in
`voltage thereby maintaining the output voltage at the desired
`output level as accurately as possible. In order to maintain this
`mode of rapid response, regulators consume a certain amount 60
`of power. When a regulator is supplying a significant amount
`of power to the load, the power required to operate in con(cid:173)
`tinuous mode is relatively small. But, when a regulator is
`supplying a small amount of power to the load, the power
`used to operate the regulator in continuous mode becomes 65
`significant, and reduces the efficiency of the regulator signifi(cid:173)
`cantly. It is common for regulators operating in the continu-
`
`6
`ous mode to transfer charge from the supply capacitors back
`into the power source when the output voltage is changed
`from a higher voltage to a lower voltage. The regulator can
`later transfer that charge back to the regulator output capaci-
`tors. Thus, most of the charge is not wasted.
`A second mode of operation by voltage regulators is often
`referred to as "high efficiency," "burst," or "skip" mode. In
`this mode, a regulator detects the reduction in load require(cid:173)
`ments (such as that caused by a transition into the deep sleep
`10 state) and switches to a mode whereby the regulator corrects
`the output voltage less frequently. When there is an increase
`in load requirements, the regulator switches back to the con(cid:173)
`tinuous mode of regulation during which more rapid correc(cid:173)
`tion occurs. This has the positive effect of reducing the power
`15 consumed by the regulator during deep sleep thereby increas(cid:173)
`ing the regulator efficiency and saving system power. But, as
`a result of reducing the regulator response rate, there is more
`noise on the regulator output.
`It is common for regulators operating in the high efficiency
`20 mode to drain the charge on the supply capacitors during a
`high to low voltage transition on the power supply output orto
`allow the load to drain the charge. Thus, the charge is wasted
`during high to low voltage transitions.
`It is typical to operate a voltage regulator in the high effi-
`25 ciency mode. Consequently, there is some waste of power
`whenever a regulated processor goes into the lower voltage
`deep sleep mode. If the processor is constantly being placed
`in deep sleep mode, then the loss of power may be quite high.
`Different operating systems may increase the waste of power
`30 by their operations. For example, an operating system that
`detects changes in operation through a polling process must
`constantly bring a processor out of deep sleep to determine
`whether a change in operating mode should be implemented.
`For many such systems, such a system causes an inordinate
`35 amount of power waste if a processor would otherwise spend
`long periods in the deep sleep mode. On the other hand, an
`operating system that remains in deep sleep until an exter(cid:173)
`nally-generated interrupt brings it out of that state wastes
`power through operating the regulator in the high efficiency
`40 mode only when the processor is placed in the deep sleep
`state.
`The present invention utilizes the ability of regulators to
`function in both the high efficiency mode and the continuous
`mode to substantially reduce power wasted by transitioning
`between a computing and a lower voltage deep sleep mode.
`Although regulators have not been dynamically switched
`between high efficiency and continuous modes, in one
`embodiment of the invention, an additional controlling input
`50 as shown in FIG. 5 is added to the regulator for selecting
`the mode of operation of the regulator based on whether the
`processor being regulated is transitioning between states. If
`the regulator receives a control signal 51 indicating that the
`processor is to be placed into the deep sleep mode, for
`example, then a regulator operating in the high efficiency
`mode immediately switches to the continuous mode during
`the voltage transition. Assuming that the regulator returns the
`charge to the battery during continuous mode, this has the
`effect of reducing the waste of power caused during the tran(cid:173)
`sition. Once the transition has completed, the regulator
`switches back to the high efficiency state for operation during
`the deep sleep mode of the processor.
`For regulators that do not conserve capacitive charge by
`transferring the charge to the battery, a circuit for accomplish(cid:173)
`ing this may be implemented or a capacitor storage arrange(cid:173)
`ment such as a charge pump 53 for storage may be added.
`Alternatively, when transitioning to deep sleep, the regulator
`could switch to a mode where the regulator does not actively
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`MICROCHIP TECH. INC. - EXHIBIT 1001
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 007
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`45
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`drive the voltage low but allows the capacitor charge to drain
`thr