97(cid:27)(cid:21)&(cid:24)(cid:27)(cid:25)%
`
`3,3&
`3&,(cid:3),QWHJUDWHG(cid:3)3HULSKHUDO(cid:3)&RQWUROOHU
`
`3&(cid:28)(cid:26)(cid:3)&RPSOLDQW(cid:3)3&,(cid:16)WR(cid:16),6$(cid:3)%ULGJH
`ZLWK(cid:3)$&3,(cid:15)(cid:3)’LVWULEXWHG(cid:3)’0$(cid:15)(cid:3)3OXJ(cid:3)DQG(cid:3)3OD\(cid:15)
`0DVWHU(cid:3)0RGH(cid:3)3&,(cid:16),’((cid:3)&RQWUROOHU(cid:3)ZLWK(cid:3)8OWUD’0$(cid:16)(cid:22)(cid:22)
`86%(cid:3)&RQWUROOHU(cid:15)(cid:3).H\ERDUG(cid:3)&RQWUROOHU(cid:15)(cid:3)DQG(cid:3)57&
`
`5HYLVLRQ(cid:3)(cid:20)(cid:17)(cid:19)
`0D\(cid:3)(cid:20)(cid:22)(cid:15)(cid:3)(cid:20)(cid:28)(cid:28)(cid:26)
`
`9,$(cid:3)7(&+12/2*,(6(cid:15)(cid:3),1&(cid:17)
`
`MICROCHIP TECH. INC. - EXHIBIT 1031
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 001
`
`

`

`Copyright Notice:
`
`Copyright© 1996, 1997 VIA Technologies Incorporated. Printed in the United States . .AL.L RIGHTS RESERVED.
`
`No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into
`any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise
`without the prior written permission of VIA Technologies Incorporated.
`
`The VT82C586, VT82C586A, and VT82C586B may only be used to identify products of VIA Technologies.
`
`YA is a registered trademark of VIA Technologies, Incorporated.
`
`PS/2™ is a registered trademark of International Business Machines Corp.
`Pentium-Pro™, GTL +™ and APIC™ are registered trademarks of Intel Corp.
`Windows 95fM and Plug and Play™ are registered trademarks of Microsoft Corp.
`PCI™ is a registered trademark of the PCI Special Interest Group.
`VESA TM is a trademark of the Video Electronics Standards Association.
`All trademarks are the properties of their respective owners.
`
`Disclaimer Notice:
`
`No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies. VIA Technologies
`makes no warranties, implied or otherwise, in regard to this document and to the products described in this document.
`The information provided by this document is believed to be accurate and reliable to the publication date of this
`document However, VIA Technologies assumes no responsibility for any errors in this document. Furthermore, VIA
`Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent
`infringements that may arise from the use of this document. The information and product specifications within this
`document are subject to change at any time, without notice and without obligation to notify any person of such change.
`
`Offices:
`USA Office:
`5020 Brandin Court
`Fremont, CA
`94538
`USA
`Tel:
`Fax:
`
`(510) 683-3300
`(510) 683-3301
`
`Online Services:
`Home Page:
`http://www. via. com. tw/
`FTP Server:
`ftp. via.com.tw
`886-2-2185208
`BBS:
`
`Taipei Office:
`8th Floor, No. 533
`Chung-Cheng Road, Hsin-Tien
`Taipei, Taiwan ROC
`Tel:
`(886-2) 218-5452
`Fax:
`(886-2) 218-5453
`
`MICROCHIP TECH. INC. - EXHIBIT 1031
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 002
`
`

`

`YA VIA Technologies, Inc.
`
`VT82C586B
`
`REVISION HISTORY
`
`Document Release
`Revision 0 .I
`Revision 0 .5
`
`Incorrect
`Change
`
`Revision 1.0
`
`Initials
`DH
`DH
`
`DH
`
`5/13/97
`
`reprinted
`1/8/97
`to fix
`Acrobat
`PDF file
`size
`problem
`
`Revision
`Date
`Initial release for 586A
`10/13/96
`12/23/96 Update to reflect 586B:
`• Updated pin definitions:
`Pins 18,31,33,58,60,131,133 (removed EXTSMI2-7 & DACEN)
`Pins 77-78,80-83,85-86 (added GPI8-15 and GPO8-15)
`Pins 94,87-88,92,136 (changed to GPI00-4 and added alternate functions)
`Pins 90,106,137 (added MIRQ0, MIRQl, and MIRQ2 functions)
`Pins 91,93,103,107 (changed to PWRBTN#, RI#, VDD-SVSB, PWRON)
`Pins 113-114,116-119 ,121-122 (added GPI, GPO, and EXTSMI functions)
`Fixed doc error DACK0-7 pin names changed to active low (DACK0-7#)
`Removed options: IRQ12 (pin 137), strap (pin 48), RTCAS (pin 94)
`• Updated register definitions
`Removed VIA-specific port A8/A9 registers
`Updated function 0 RxS-4[3], Rx7-6[13], Rx41[0-4,6-7], Rx42[4-7], Rx44,
`Rx46[2-4], Rx47[3], Rx48[3], Rx4A[4-6], Removed Rx50 (MDRQ)
`Rx55[7-4] change PIRQD# to MIRQl, Rx56 swap A/B, Rx57 swap CID
`Added 58-SB for PnP, XD, KBC/RTC config; added 60-6F for DDMA ctrl
`Removed power mgmt regs 80-94 & added function 3 ACPI Power Mgmt
`• Straps: moved 95-96 to SA, allow RW after powernp, removed strap XD3
`• Expanded CMOS RAM: added ports 72-75 & table 5 CMOS Reg Summary
`• Added Power Management Subs::i:stem Overview
`• Incomorated App Note #53 APM-Compliant Pwr Mgmt Model of 82C586A
`• Added AC Timing Section with IDE Interfac•e Timing Diaerams & S~cs
`• Overview Changes: Added System Block Diagram
`• Pin Function Changes:
`Pin 90 added alternate function "POS" output (3040F and 3041 silicon)
`Pin 106 added alternate function "IRQ8#" input (3040F and 3041 silicon)
`Pin 137 added alternate function "SDDIR" output (3041 only silicon)
`• Register Definition Changes:
`Fixed typos: Port 75 note, Fn0 Rx48[3], Rx55-57[7:0]; Fnl Rx4[7]; Fn2
`Rx3C-3D; Fn3 Rx26[9], Rx2F, Rx62-63, Table 7
`Added missing register: Function 0 Rx59[3] MIRQ Pin Config Register
`Function 0 PCI-to-ISA Bridge (3041 only silicon)
`Rx08[7:0] (changed) Revision Code Register
`Rx2C[3 l :0] (new) Subsystem ID Register (read)
`Rx41[0] (changed) ISA Test Mode Register
`Rx46[7:5] and Rx48[5:4] (new) Misc Control Registers 1 and 3
`RxSC[0] (new) DMA Control Register
`Rx70[31:0] (new) Subsystem ID Register (write)
`Function 1 IDE Controller (3041 only silicon)
`Rx43[7] (new) FIFO Configuration Register
`Rx44[1:0] (new) Misc Control Register 1
`Function 3 Power Management (3040F and 3041 silicon)
`Rx04[0] (moved to Rx41[7]) Command Register
`Rx08[7:0] (changed) Revision ID Register
`Rx10[4:l], Rxl4 (changed) Processor Control and Processor Level 2
`Rx20[3 l :0] (moved to Rx48) 1/0 Base Address Register
`Power Management l/O(3040F and 3041 silicon)
`Rx40[6:5] (new) GPIO Direction Control Register
`• Electrical S~c Changes: Added PCI Cycle Timing
`• Mechanical Snee 01an!>es: Added marking specs for 3040E/F, 3041 silicon
`
`Revision 1.0 May 13, 1997
`
`-1-
`
`Revision History
`
`MICROCHIP TECH. INC. - EXHIBIT 1031
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 003
`
`

`

`YA VIA Technologies, Inc.
`
`VT82C586B
`
`TABLE OF CONTENTS
`
`REVISION HISTORY ....................................................................................................................................................................... .1
`
`TABLE OF CONTENTS .................................................................................................................................................................. U
`
`LIST OF FIGURES ......................................................................................................................................................................... .10
`
`LIST OF TABLES ........................................................................................................................................................................... IV
`
`OVERVIEW ....................................................................................................................................................................................... 3
`
`PINOUTS ............................................................................................................................................................................................ 4
`
`REGISTERS ..................................................................................................................................................................................... 14
`
`REGISTER OVERVIEV\' .................................................................................................................................................................
`
`CONFIGURATIONSPACEl/O
`
`.......................................................................................................................................................
`
`14
`
`20
`
`21
`REGISTER DESCRIPTIONS ............................................................................................................................................................
`Legacy 1/0 Ports ................................................................................................................................................................... 21
`Keyboard Controller Registers ..............................................................................................................................................................
`22
`DMA Controller I/O Registers ..............................................................................................................................................................
`24
`lntem1pt Controller Registers ...............................................................................................................................................................
`25
`Timer/ Counter Registers .....................................................................................................................................................................
`25
`CMOS I RTC Registers .........................................................................................................................................................................
`26
`PCI to ISA Bridge Registers (Function 0) .......................................................................................................................... 27
`PCI Configuration Space Header ..........................................................................................................................................................
`27
`ISA Bus Control ....................................................................................................................................................................................
`27
`30
`Plug and Play Control ...........................................................................................................................................................................
`Distributed DMA Control .....................................................................................................................................................................
`32
`Miscellaneous .......................................................................................................................................................................................
`32
`Enhanced IDE Controller Registers (Function 1) ............................................................................... ·-····························33
`33
`PCI Configuration Space Header ..........................................................................................................................................................
`IDE·Controller-Specific Confiiguration Registers ................................................................................................................................
`35
`IDE I/O Registers ..................................................................................................................................................................................
`37
`Universal Serial Bus Controller Registers (Function 2) ········································································-··························38
`PCI Configuration Space Header ..........................................................................................................................................................
`38
`USB·Specific Configuration Registers ..................................................................................................................................................
`39
`USB I/O Registers .................................................................................................................................................................................
`39
`Power Manage1nent Registers (Function 3) ........................................................................................................................ 40
`PCI Configuration Space Header ..........................................................................................................................................................
`40
`41
`Power Management-Specific PCI Configuration Registers .................................................................................................................
`Power Management Subsystem Overview ...........................................................................................................................................
`43
`Power Management I/O-Space Registers ..............................................................................................................................................
`46
`
`ELECTRICAL SPECIFICATIONS·····································································································-········································ 55
`ABSOLUTE MAXIMm1 RA TINGS ................................................................................................................................................. 55
`
`
`
`DC CHARACTERISTICS ..............•................................................................................................................................................. 55
`
`
`
`AC TIMING SPECIFICATIONS ....•................................................................................................................................................. 56
`
`PACKAGE MECHANICAL SPECIFICATIONS·····························································································-························· 63
`
`Revision 1.0 May 13, 1997
`
`-ii-
`
`Table of Contents
`
`MICROCHIP TECH. INC. - EXHIBIT 1031
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 004
`
`

`

`YA VIA Technologies, Inc.
`
`VT82C586B
`
`LIST OF FIGURES
`
`FIGURE 1. PC SYSTEM CONFIGURATION USING THE VT82C586B ................................................................................. 3
`FIGURE 2. PIN DIAGRAM ............................................................................................................................................................. 4
`FIGURE 3. STRAP OPTION CIRCUIT ....................................................................................................................................... 31
`FIGURE 4. POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM ........................................................................... 43
`FIGURE 5. ULTRADMA-33 IDE TIMING - DRIVE INITIATING DMA BURST FOR READ COMMAND .................... 58
`FIGURE 6. ULTRADMA-33 IDE TIMING - DRIVE INITIATING BURST FOR WRITE COMMAND ............................ 58
`FIGURE 7. ULTRADMA-33 IDE TIMING - PAUSING A DMA BURST ............................................................................... 59
`FIGURE 8. ULTRADMA-33 IDE TIMING - DRIVE TERMINATING DMA BURST DURING READ COMMAND ...... 60
`FIGURE 9. ULTRADMA-33 IDE TIMING - DRIVE TERMINATING DMA BURST DURING WRITE COMMAND ... 60
`FIGURE 10. ULTRADMA-33 IDE TIMING - HOST TERMINATING DMA BURST DURING READ COMMAND ...... 61
`FIGURE 11. ULTRADMA-33 IDE TIMING - HOST TERMINATING DMA BURST DURING WRITE COMMAND ... 61
`FIGURE 12. ULTRADMA-33 IDE TIMING- PIO CYCLE ...................................................................................................... 62
`FIGURE 13. MECHANICAL SPECIFICATIONS - 208-PIN PLASTIC FLAT PACKAGE .................................................. 63
`
`Revision 1.0 May 13, 1997
`
`-lll-
`
`List of Figures
`
`MICROCHIP TECH. INC. - EXHIBIT 1031
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 005
`
`

`

`YA VIA Technologies, Inc.
`
`VT82C586B
`
`LIST OFT ABLES
`
`TABLE 1. PIN DESCRIPTIONS ..................................................................................................................................................... 5
`TABLE 2. SYSTEM 1/0 MAP ....................................................................................................................................................... 14
`TABLE 3. REGISTERS .................................................................................................................................................................. 14
`TABLE 4. KEYBOARD CONTROLLER COMMAND CODES .............................................................................................. 23
`TABLE 5. CMOS REGISTER SUMMARY ................................................................................................................................. 26
`TABLE 6. SCI/SMI/RESUME CONTROL FOR PM EVENTS ................................................................................................. 44
`TABLE 7. SUSPEND RESUME EVENTS AND CONDITIONS ················································································-·············44
`TABLE 8. AC CHARACTERISTICS-
`PCI CYCLE TIMING .............................................................................. ·-·················56
`TABLE 9. AC CHARACTERISTICS
`- ULTRADMA-33 IDE BUS INTERFACE TIMING .................................................. 57
`
`Revision 1.0 May 13, 1997
`
`-IV-
`
`List of Tables
`
`MICROCHIP TECH. INC. - EXHIBIT 1031
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 006
`
`

`

`YA VIA Technologies, Inc.
`
`VT82C586B
`
`VT82C586B PIPC
`PCI INTEGRATED PERIPHERAL CONTROLLER
`
`BRIDGE
`PC97 COMPLIANT PCI-To-lSA
`WITH ACPI, DISTRIBUTED DMA, PLUG AND PLAY,
`MASTER MODE PCI IDE CONTROLLER WITH ULTRADMA-33,
`USB CONTROLLER, KEYBOARD CONTROLLER, AND REAL TIME CLOCK
`
`• PC97 Compliant PCI to ISA Bridge
`
`Integrated ISA Bus Controller with integrated DMA, timer, and intem1pt controller
`Integrated Keyboard Controller with PS2 mouse support
`Integrated DS 12885-style Real Time Clock with extended 256 byte CMOS RAM and Day/Month Alarm for ACPI
`Integrated USB Controller with root hub and two function ports
`Integrated master mode enhanced IDE controller with enhanced PCI bus commands and UltraDMA-33 extensions
`PCI-2.1 compliant with delay transaction
`Eight double-word line buffer between PCI and ISA bus
`One level of PCI to ISA post-write buffer
`Supports type F DMA transfers
`Distributed DMA support for ISA legacy DMA across the PCI bus
`Fast reset and Gate A20 operation
`Edge trigger or level sensitive intem1pt
`Flash EPROM, 2MB EPROM and combined BIOS support
`Programmable ISA bus clock
`Supports external IOAPIC interfac•e for symmetrical multiprocessor configurations
`
`•
`
`Inter-operable with VIA and other Host-to-PCI Bridges
`
`for a complete 75MHz 6x86 / PCI / ISA system (Apollo VPX)
`Combine with VT82C585VPX/587VP
`Combine with VT82C595 for a complete Pentium/ PCI / ISA system (Apollo VP2)
`Combine with VT82C685/687 for a complete Pentium-Pro /PCI / ISA system (Apollo P6)
`Combine with VIA Apollo-AGP and Apollo Pro chipsets for new high-performance/
`enhanced-functionality systems
`Inter-operable with other Intel or non-Intel Host-to-PCI bridges for a complete PC97 compliant PCI/ISA system
`
`• Enhanced Master Mode PCI IDE Controller with Extension to UltraDMA-33
`
`Dual channel master mode PCI supporting four Enhanced IDE devices
`Transfer rate up to 33MB/sec to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-33 interface
`Sixteen levels (doublewords) of prefetch and write buffers
`Interlaced commands between two channels
`Bus master programming interface for SFF-8038i rev .1.0 and Windows-95 compliant
`Full scatter gather capability
`Support AT API compliant devices including DVD devices
`Support PCI native and ATA compatibility modes
`Complete software driver support
`
`Revision 1.0 May 13, 1997
`
`-1-
`
`Features
`
`MICROCHIP TECH. INC. - EXHIBIT 1031
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 007
`
`

`

`YA VIA Technologies, Inc.
`
`VT82C586B
`
`• Universal Serial Bus Controller
`USB v.1.0 and Intel Universal HCI v.1.1 compatible
`Eighteen level (doublewords) data FIFO with full scatter and gather capability
`Root hub and two function ports
`Integrated physical layer transceivers with over-current detection status on USB inputs
`Legacy keyboard and PS/2 mouse support
`
`• Sophisticated PC97-Compatible Power Management
`Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management
`ACPI vl.O Compliant (all required features plus extensions for most efficient desktop power management)
`APM v 1.2 Compliant
`Supports soft-off (suspend to disk) and power-on suspend with hardware automatic wake-up
`One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer
`Dedicated input pin for extemal modem ring indicator for system wake-up
`Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field
`Normal, doze, sleep, suspend and conserve modes
`System event monitoring with two event classes
`Five multi-purpose UO pins plus support for up to 16 general purpose input ports and 16 output ports
`l 2C serial bus support for JEDEC-compatible DIMM identification and on-board-device power control
`Seven extemal event input ports with programmable SMI condition
`Primary and secondary interrupt differentiation for individual channels
`Clock throttling control
`Multiple intemal and extemal SMI sources for flexible power management models
`
`• Plug and Play Controller
`PCI intem1pts steerable to any interrupt channel
`Three steerable interrupt channels for on-board plug and play devices
`Microsoft Windows 95™ and plug and play BIOS compliant
`
`• Pin-compatible upgrade from VT82CS86 and VT82CS86A for existing designs
`
`• Built-in Nand-tree pin scan test capability
`
`• 0.Sum mixed voltage, high speed and low power CMOS process
`
`• Single chip 208 pin PQFP
`
`Revision 1.0 May 13, 1997
`
`-2-
`
`Features
`
`MICROCHIP TECH. INC. - EXHIBIT 1031
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 008
`
`

`

`YA VIA Technologies, Inc.
`
`VT82C586B
`
`OVERVIEW
`
`The VT82C586B PIPC (PCI Integrated Peripheral Controller) is a high integration, high performance and high compatibility
`device that supports Intel and non-Intel based processor to PCI bus bridge functionality to make a complete Microsoft PC97-
`compliant PCI/ISA system. In addition to complete ISA extension bus functionality, the VT82C586B includes standard intelligent
`peripheral controllers:
`
`a) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands. Dedicated
`FIFO coupled with scatter and gather master mode operation allows high perfonnance transfers between PCI and IDE
`devices. In addition to standard PIO and DMA mode operation, the VT82C586B also supports the emerging UltraDMA-33
`standard to allow reliable data transfer rates up to 33MB/sec throughput. The IDE controller is SFF-8038i vl.0 and
`Microsoft Windows-95 compliant.
`
`b) Universal Serial Bus controller that is USB v 1.0 and Universal HCI v 1.1 compliant. The VT82C586B includes the root hub
`with two function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and
`isochronous peripherals to be inserted into the system with universal driver support. The controller also implements legacy
`keyboard and mouse support so that legacy software can nm transparently in a non-USE-aware operating system
`environment.
`
`c) Keyboard controller with PS2 mouse support.
`
`d) Real Time Clock witl1 256 byte extended CMOS. In addition to tl1e standard ISA RTC functionality, the integrated RTC also
`includes the date alann and otl1er enhancements for compatibility with the ACPI standard.
`
`e) Notebook-class power management functionality that is compliant witl1 ACPI and legacy APM requirements. Two types of
`sleep states (soft-off and power-on-suspend) are supported with hardware automatic wake-up. Additional functionality
`includes event monitoring, CPU clock throttling (Intel processor protocol), modular power control, hardware- and software(cid:173)
`based event handling, general purpose IO, chip select and external SMI.
`
`f) Distributed DMA capability for support of ISA legacy DMA over the PCI bus.
`
`g) Plug and Play controller that allows complete steerability of all PCI interrupts to any interrupt channel. Three additional
`steerable interrupt channels are provided to allow plug and play and reconfigurability of on-board peripherals for Windows
`95 compliance.
`
`h) External IOAPIC support for Intel-compliant symmetrical multiprocessor systems.
`
`The VT82C586B also enhances the functionality of the standard ISA peripherals. The integrated interrupt controller supports both
`edge and level triggered interrupts channel by channel. The integrated DMA controller supports type F DMA in addition to
`standard ISA DMA modes. Compliant with tl1e PCI-2.1 specification, tl1e VT82C586B supports delayed transactions so tl1at
`slower ISA peripherals do not block the traffic of the PCI bus. Special circuitry is built in to allow concurrent operation without
`causing dead lock even in a PCI-to-PCI bridge environment The chip also includes eight levels (doublewords) of line buffers from
`the PCI bus to tl1e ISA bus to furtl1er enhance overall system perfonnance.
`
`CPU /Cache
`
`North Bridge
`
`MA/RAS/CAS
`
`System Memory
`
`Sideband Signals:
`Init I CPUreset
`IRQ/NMI
`SMI / StopC!k
`FERR/IGNNE
`
`Crystal
`
`Boot ROM
`
`VT82C586B
`208PQFP
`
`PCI
`
`12C (Module ID)
`
`USB
`KBC
`IDE
`GPIO, Power Control, Reset
`ISA
`
`Expansion
`Cards
`
`Figure l. PC System Configuration Using the VT82C586B
`
`Revision 1.0 May 13, 1997
`
`-3-
`
`Overview
`
`MICROCHIP TECH. INC. - EXHIBIT 1031
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 009
`
`

`

`YA VIA Technologies, Inc.
`
`VT82C586B
`
`PINOUTS
`
`Figure 2. Pin Diagram
`
`.... ~
`.;;-
`~::!:~
`t:;~
`::.::. ::.::.:::;;
`00
`O'
`"'
`"'"' "'"'"'
`...
`.;;-
`::::.
`F-F-E-,
`!-!-
`tjtjx
`_,,,
`>(>(
`~ 3
`~;;-
`~U-
`="'~
`-;;;: 0.0.
`:: ~ f! e~ ~"'-
`ci::F-U g-
`~
`0.0.
`~ :!
`a::<cc~
`-1-
`§
`~ §
`{i § ~ &;
`
`->(CC'-
`
`0.0.
`
`,,.._,-_ ~--
`
`VDD-PCI
`AD4
`ADS
`AD6
`AD7
`CBE0I
`ADS
`AD9
`ADIO
`GND
`ADll
`AD12
`AD13
`ADl4
`VDD-PCI
`AD15
`CBEII
`PAR
`SERRI
`STOP#
`GND
`DEVSEU
`TRDY#
`IRDY#
`FRAMH
`CBE21
`AD16
`VDD-PCI
`ADI?
`ADIS
`AD19
`GND
`AD20
`AD21
`AD22
`AD23
`IDSEL
`CBE31
`AD24
`AD25
`GND
`VDD-PCI
`AD26
`AD27
`AD28
`AD29
`AD30
`AD31
`PIR~I
`PIR C#
`PIR Bl
`G D
`
`----------------------------------------------------
`
`~~~MM-O~~~~~~MN-O~~~~~~MM-O~~~~~~MM-O~~~~~~MM-0~~~~~
`~~~~~~~~~~~~~~~~~MMMMMMMMMMMNNMNNMMMN----------00000
`22220-00000
`ooo o-22020-0------2222
`
`2222
`
`22022220-0
`(IRQS#) I 104
`103
`I 102
`101
`100
`I 99
`IO 98
`IO 97
`IO 96
`IO 95
`(EXTSMIOI) 0 94
`I 93
`(GPI_RE#) (EXTSMB#) IO 92
`I 91
`
`t (POS) (MIRQ0) IP i~
`
`157
`158 IO
`159 IO
`160 IO
`161 IO
`162 IO
`163 IO
`164 IO
`165 IO
`166
`167 IO
`168 IO
`169 IO
`170 IO
`171
`172 IO
`173 IO
`174 IO
`175 I
`176 IO
`177
`178 IO
`179 IO
`180 IO
`181 IO
`182 IO
`183 IO
`184
`185 IO
`186 IO
`187 IO
`188
`189 IO
`190 IO
`191 IO
`192 IO
`193 I
`194 IO
`195 IO
`196 IO
`197
`198
`199 IO
`200 IO
`201 IO
`202 IO
`203 IO
`204 IO
`205 I
`206 I
`207 I
`208
`000-000
`00000000
`oo-
`--00----0022
`O-MM~~~~~~O-MM~~~~~~O-MM~~~~~~O-MM~~~~~~O-M
`-MM~~~~~~----------MMMMMMMMMMMMMMMMMMMM~~~~~~~~~~~~~
`
`II
`VT82c586B i!:::::ili!:!!::l:!
`PCI Integrated
`Peripheral Controller
`
`(Datal (12CD~l (EXTSMI2#j IO 88
`(Clock (12CDIP ~EXTSMil#l IO 87
`
`GPI12 GPO12 IO 82
`GPill GPOll IO 81
`GPIIO GPOI0 IO 80
`79
`(GPI9l (GPO9) IO 78
`(GPIS (GPOS) IO 77
`I 76
`I 75
`I 74
`I 73
`I 72
`I 71
`IO 70
`IO 69
`68
`IO 67
`IO 66
`IO 65
`IO 64
`IO 63
`IO 62
`I 61
`0 60
`I 59
`0 58
`I 57
`0 56
`0 55
`0 54
`53
`
`PQFP-208
`5/5/97
`
`Note: Pin names in parentheses( ... ) indicate alternate function
`* 3040 Rev F and Later Revisions
`t 3041 Rev A and Later Revisions
`
`0
`
`0000
`
`22222--oo-oo
`
`RTCXI
`VDD-SVSB
`VBAT
`AGND
`AVDD
`USBCLK
`USBDATAI(cid:173)
`USBDATAI+
`USBDATA0-
`USBDATA0+
`GPIO0
`RII
`GPI03
`PWRBTN#
`APICCS#
`DRDYBI
`GPI02
`GPIOI
`SD15
`SDl4
`GND
`SD13
`SD12
`SDI!
`SDI0
`VDD5
`SD9
`SDS
`MEMCS16#
`IR 4
`IR~3
`IR 5
`IR 6
`IR 7
`LA 7/DA0
`LAIS/DAI
`GND
`LA19/DA2
`LA20/DCS IA#
`LA21/DCS3A#
`LA22/DCS IB#
`LA23/DCS3B#
`SBHH
`IRO9
`DA'CK0#
`DRO0
`DACK5#
`DRO5
`son
`DIOWB#
`DIORBI
`VDD5
`
`Revision 1.0 May 13, 1997
`
`-4-
`
`Pinouts
`
`MICROCHIP TECH. INC. - EXHIBIT 1031
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 010
`
`

`

`YA VIA Technologies, Inc.
`
`VT82C586B
`
`Table 1. Pin Descriptions
`
`CPU Interface
`
`Signal Name
`CPURST
`INTR
`
`Pin No.
`142
`145
`
`NMI
`
`INIT
`
`STPCLK#
`
`SMI#
`
`FERR#
`
`IGNNE#
`
`146
`
`143
`
`148
`
`149
`
`141
`
`139
`
`1/0 Signal Description
`0
`CPU Reset. The VT82C586B asserts CPURST to reset the CPU during power-up.
`CPU Interrupt. INTR is driven by the VT82C586B to signal the CPU that an
`0
`interrupt request is pending and needs service.
`0 Non-Maskable Interrupt. NMI is used to forc•e a non-maskable interrupt to the
`CPU. The VT82C586B generates an NMI when either SERR# or IOCHK# is
`asserted.
`Initialization. The VT82C586B asserts INIT if it detects a shut-down special cycle
`on the PCI bus or if a soft reset is initiated by the register
`Stop Clock. STPCLK# is asserted by the VT82C586B to the CPU in response to
`different Power-Management events.
`System Management Interrupt. SMI# is asserted by the VT82C586B to the CPU
`in response to different Power-Management events.
`0 Numerical Coprocessor Error. This signal is tied to the coprocessor error signal on
`the CPU.
`fonore Numeric Error. This oin is connected to the "ignore error" oin on the CPU.
`
`0
`
`0
`
`0
`
`0
`
`Revision 1.0 May 13, 1997
`
`-5-
`
`Pinouts
`
`MICROCHIP TECH. INC. - EXHIBIT 1031
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 011
`
`

`

`YA VIA Technologies, Inc.
`
`VT82C586B
`
`PCI Bus Interface
`
`1/0 Signal Description
`PCI Clock. PCLK provides timing for all transactions on the PCI Bus.
`I
`Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates
`B
`that one more data transfer is desired by the cycle initiator.
`B Address/Data Bus. The standard PCI address and data lines. The address is driven
`with FRAME# assertion and data is driven or received in following cycles.
`
`B
`I
`
`I
`
`I
`
`B Command/Byte Enable. The coillllland is driven with FRAME# assertion. Byte
`enables corresponding to supplied or requested data are driven on following clocks.
`Initiator Ready. Asserted when the initiator is ready for data transfer.
`B
`Tar2et Ready. Asserted when the target is ready for data transfer.
`B
`Stop. Asserted bv the target to reauest the master to stop the current transaction.
`B
`B Device Select. The VT82C586B asserts this signal to claim PCI transactions through
`positive or subtractive decoding.
`Paritv. A single paritv bit is provided over AD[31:0] and C/BE[3:0]#.
`System Error. SERR# can be pulsed active by any PCI device that detects a system
`error condition. Upon sampling SERR# active, the VT82C586B can be programmed
`to generate an NMI to the CPU.
`Initialization Device Select. IDSEL is used as a chip select during configuration
`read and write cycles.
`PCI Interrupt Request. These pins are typically connected to the PCI bus INTA#-
`INTD# pins as follows:
`PIRQD#
`PIRQC#
`PIRQB#
`PIRQA#
`INTD#
`INTC#
`INTB#
`INTA#
`PCI Slot I
`INTD#
`INTA#
`INTC#
`INTB#
`PCI Slot2
`INTA#
`INTB#
`INTD#
`INTC#
`PCI Slot 3
`INTA#
`INTC#
`INTB#
`INTD#
`PCI Slot4
`PCI Request. This signal goes to the North Bridge to request the PCI bus.
`PCI Grant. This signal is driven by the North Bridge to grant PCI access to the
`VT82C586B.
`
`Signal Name
`PCLK
`FRAME#
`
`AD[31:0]
`
`C/BE[3:0]#
`
`IRDY#
`TRDY#
`STOP#
`DEVSEL#
`
`PAR
`SERR#
`
`IDSEL
`
`Pin No.
`2
`181
`
`204-199, 196-
`195, 192-189,
`187-185, 183,
`172, 170-167,
`165-163, 161-
`158, 155-152
`194, 182, 173,
`162
`180
`179
`176
`178
`
`174
`175
`
`193
`
`PIRQA-D#
`
`1, 207-205
`
`PREQ#
`PGNT#
`
`151
`150
`
`0
`I
`
`Revision 1.0 May 13, 1997
`
`-6-
`
`Pinouts
`
`MICROCHIP TECH. INC. - EXHIBIT 1031
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 012
`
`

`

`YA VIA Technologies, Inc.
`
`VT82C586B
`
`ISA Bus Control
`
`1/0
`B
`
`Signal Description
`System Address Bus / IDE Data Bus
`
`Pin No.
`20-25, 27-28,
`36-38, 40-44
`19
`63-67, 69-70
`
`Signal Name
`SA[15:0] /
`DD[15:0]
`SA16
`LA23/DCS3B#,
`LA22/DCS IB#,
`LA21/DCS3A#,
`LA20/DCS1A#,
`LA[19:17] /
`DA[2:0]
`
`SD[15:8] /
`GPI[15:8] /
`GPO[15:8]
`
`86-85, 83-80,
`78-77
`
`SBHE#
`
`IOR#
`
`IOW#
`
`MEMR#
`
`MEMW#
`
`SMEMR#
`
`SMEMW#
`
`BALE
`
`IOCS16#
`
`MEMCS16#
`
`IOCHCK#
`
`IOCHRDY
`
`62
`
`12
`
`11
`
`123
`
`124
`
`10
`
`9
`
`3