United States Patent c191
`Fairbanks et al.
`
`[11] Patent Number:
`[45] Date of Patent:
`
`5,021,679
`Jun.4, 1991
`
`[54] POWER SUPPLY AND OSCILLATOR FOR A
`COMPUTER SYSTEM PROVIDING
`AUTOMATIC SELECTION OF SUPPLY
`VOLTAGE AND FREQUENCY
`[75] Inventors: John P. Fairbanks, Sunnyvale; Andy
`C. Yuan, Saratoga, both of Calif.
`[73] Assignee: Poqet Computer Corporation, Santa
`Clara, Calif.
`[21] Appl. No.: 374,514
`[22] Filed:
`Jun. 30, 1989
`[51] Int. Cl.5 ..........................
`GOSF 1/613; H02J 9/06
`[52] U.S. Cl . ...................................... 307/66; 323/222;
`323/272; 323/318; 323/350; 323/351; 364/707
`[58] Field of Search .................... 307/66, 296.1, 296.3,
`307/296.4,28,43-48, 72-76;364/700, 706,707,
`708;323/318, 349,350,351,222,223,225,268,
`272,282,283,284; 455/343; 331/177 V
`References Cited
`U.S. PATENT DOCUMENTS
`3,922,526 11/1975 Cochran .............................. 364/707
`4,355,277 10/1982 Davis et al .......................... 323/351
`4,435,679 3/1984 Bedard et al. ....................... 323/350
`
`[56]
`
`4,502,152 2/1985 Sinclair ................................. 455/73
`4,634,956 1/1987 Davis et al. ......................... 323/222
`4,890,003 12/1989 Seibert et al. ......................... 307/66
`Primary Examiner-J. R. Scott
`Assistant Examiner-David Osborn
`Attorney, Agent, or Firm-Skjerven, Morrill,
`MacPherson, Franklin & Friel
`ABSTRACT
`[57]
`Disclosed is a power system for use with a computer,
`the power system having incorporated in it circuitry for
`automatically varying the supply voltage output to the
`computer system based upon the magnitude of the cur(cid:173)
`rent being supplied to the computer by the power sys(cid:173)
`tem. Also included in the computer system is a variable
`frequency clock circuit,
`the frequency of which
`changes based upon the supply voltage produced by the
`power system. This permits, during computer system
`operation where low voltage and low clock speeds will
`be sufficient
`to provide
`the performance needed,
`achievement of a power saving since both the voltage
`and frequency at which the system operates is reduced,
`thereby markedly reducing the power consumption.
`
`15 Claims, 7 Drawing Sheets
`
`BATTERY CHANGE
`
`MICROCHIP TECH. INC. - EXHIBIT 1019
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 001
`
`

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`MICROCHIP TECH. INC. - EXHIBIT 1019
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 002
`
`

`

`U.S. Patent
`
`June 4, 1991
`
`Sheet 2 of 7
`
`5,021,679
`
`~;....._ __
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`
`ENABLE 2
`ENABLE 1 B
`N22
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`FIG.2A
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`29
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`SYMMETRICAL OSCILLATOR
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`
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`FIG.2D
`
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`
`MICROCHIP TECH. INC. - EXHIBIT 1019
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 003
`
`

`

`U.S. Patent
`
`June 4, 1991
`
`Sheet 3 of 7
`
`5,021,679
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`MICROCHIP TECH. INC. - EXHIBIT 1019
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 004
`
`

`

`U.S. Patent
`
`June 4, 1991
`
`Sheet 4 of 7
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`5,021,679
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`MICROCHIP TECH. INC. - EXHIBIT 1019
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 005
`
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`MICROCHIP TECH. INC. - EXHIBIT 1019
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 006
`
`

`

`U.S. Patent
`
`June 4, 1991
`
`Sheet 6 of 7
`
`5,021,679
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`MICROCHIP TECH. INC. - EXHIBIT 1019
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 007
`
`

`

`U.S. Patent
`
`June 4, 1991
`
`Sheet 7 of 7
`
`5,021,679
`
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`MICROCHIP TECH. INC. - EXHIBIT 1019
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 008
`
`

`

`1
`
`5,021,679
`
`POWER SUPPLY AND OSCILLATOR FOR A
`COMPUTER SYSTEM PROVIDING AUTOMATIC
`SELECTION OF SUPPLY VOLTAGE AND
`FREQUENCY
`
`15
`
`2
`07/375,721, filed on Jun. 30, 1989, entitled "Portable
`Low Power Computer," which is incorporated herein by
`reference. For the convenience of the reader, certain
`reference characters utilized in this application corre-
`5 spond to those utilized in the above-identified copend(cid:173)
`ing application.
`In certain tasks performed by a computer system,
`such as word processing, it is possible to operate the
`system clock at a slower clock rate than is required for
`computational tasks. Similarly, in the word processing
`mode of operation the circuits in the system may be
`operated at a lower voltage than is required when com(cid:173)
`putations are being performed. Thus by operating at a
`slower clock frequency and lower voltage the perfor(cid:173)
`mance of the system is not degraded from the user's
`perspective and the power consumed is reduced. Simi-
`larly, if the system clock is operating at a lower fre(cid:173)
`quency, the devices utilized in the system may also be
`operated at a lower voltage since the reduced voltage
`will still be adequate to provide switching at the lower
`frequency. For example, in the computer system de-
`scribed and claimed in the above-identified co-pending
`patent application which uses the present invention, it
`has been found that quite adequate performance may be
`achieved by using a VDD of approximately 3 volts and
`a 2.3 mHz system clock frequency to process informa-
`tion in the word processing mode of operation. How(cid:173)
`ever, when the mode of operation of the computer
`30 involves the computation of numerical data, it is desir(cid:173)
`able, under most circumstances, to perform that func(cid:173)
`tion quickly. Accordingly, in the computational mode
`the power supply output is changed from 3 volts to 5
`volts and the system clock frequency changed from 2.3
`mHz to 6.6 mHz. Under these latter conditions the
`maximum speed of processing is achieved. As men(cid:173)
`tioned above, the advantageous use of a variable fre(cid:173)
`quency oscillator to produce the clock signals (hereinaf(cid:173)
`ter the variable frequency oscillator for producing
`clock signals will be referred to as the VCO) permits the
`increased computational frequencies as well as protect-
`ing data when the system power supply is unable to
`provide the current required by the load placed on it or
`when the batteries become discharged by an amount
`sufficient to degrade system performance. Circuitry is
`included in the VCO to achieve a percent reduction in
`operating frequency which is greater than the percent
`reduction in supply voltage. For example, if the VCD
`frequency at 5 volts is 6.6 mHz, it would be expected
`50 that at 3 volts, based on the same percent reduction in
`frequency, the VCO operation would be at 3.96 mHz.
`However it has been found that additional power sav(cid:173)
`ings may be achieved by providing for a greater percent
`reduction and the preferable ratio is that, as noted
`above, at VDD=3 volts the VCO frequency is 2.3
`mHz. Under
`these conditions, with
`the
`formula
`P=CV 2F, power consumption, by changing the volt(cid:173)
`age from 5 to 3 volts provides almost a 3:1 power sav(cid:173)
`ings and additional power saving is achieved by chang(cid:173)
`ing the frequency from 6.6 mHz to 2.3 mHz, giving
`another factor of almost 3 to 1 power reduction. The
`combination therefore achieves about an 8: 1 reduction
`of power.
`In the present invention, the power system is opera(cid:173)
`ble in the automatic mode, in which the supply voltage
`(VDD) is either 3 or 5 volts, or in an override mode,
`which under control from the processor of the system
`the power supply output voltage is forced to regulate to
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`This invention relates to a power system for a com(cid:173)
`puter, and more particularly, to a power system for a lO
`computer which automatically selects the voltage to the
`computer system and also the frequency of operation of
`the computer system based on the current requirements
`of the system or upon a control signal from the com-
`puter system.
`2. Description of the Prior Art
`Present day portable computers have limitations on
`the length of time they operate before exhausting the
`batteries in the system. Typical portable computers
`heretofore known operate at a single voltage, typically 20
`5 volts, and utilize system clocks having a fixed fre(cid:173)
`quency. There are certain disadvantages to this in that
`they do not incorporate features to reduce the load on
`the batteries and therefore extend their life. In a typical
`integrated circuit device utilizing CMOS semiconduc- 25
`tor devices, the power consumed by the system is ex(cid:173)
`pressed by the equation
`
`Since the capacitance of a system is a variable not avail(cid:173)
`able for adjustment by designers, the possible variables
`which could be changed are the system voltage and the
`operating frequency. Prior art computer systems are
`known which include clocks having more than one 35
`frequency, however the variable frequency clocks were
`utilized as a function of the mode of operation and not
`responsive to the average usage over a period of time.
`In the prior art systems if the power supply was unable
`to provide the required voltage for a high frequency 40
`clock operation, the system would lose data because the
`clock could not operate at a frequency less than its
`maximum and was not tailored to permit operation at a
`lower supply voltage if that was all that was available.
`Also in the prior art systems there was not the ability to 45
`provide a continuing voltage and system clock fre(cid:173)
`quency relationship in which the system clock varied
`over a continuum of possible supply voltages.
`
`SUMMARY OF THE INVENTION
`The present invention relates to a power system and
`oscillators for use with the computer system which
`together function to provide operating voltage for the
`system which is the minimum required for performing
`the functions of the system and secondly to reduce the 55
`frequency of the system clock to also reduce the power
`consumption of the system. In addition to reducing
`power by lowering the voltage and frequency, the utili(cid:173)
`zation of a variable frequency oscillator to provide the
`system clock signals, with the oscillator's frequency 60
`varying as a function of the system supply voltage,
`permits the safeguard of saving system data in circum(cid:173)
`stanc·;;,, where a heavy load on the system reduces the
`supply voltage to below that normally required for
`performing the computational tasks of the system.
`The present invention discloses the power system and
`the oscillators utilized in the computer system described
`and claimed in copending patent application Ser. No.
`
`65
`
`MICROCHIP TECH. INC. - EXHIBIT 1019
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`
`

`

`5,021,679
`
`4
`FIG. 2B illustrates the voltage across capacitor C21
`in the power system of FIG. 1;
`FIG. 2C illustrates the voltage across capacitor C22
`in the power system of FIG. l;
`FIG. 2D illustrates the output frequency of oscillator
`circuit 19 of FIG. 2A with respect to supply voltage
`VDD;
`FIG. 2E illustrates the output frequency of system
`clock circuit 18 of FIG. 2A with respect to supply
`voltage VDD;
`FIG. 3A illustrates pulse width modulation regula(cid:173)
`tion utilized in the prior art;
`FIG. 3B illustrates the on/off regulation technique
`utilized in the power system of FIG. 1;
`FIG. 4 is an enlarged circuit diagram of the voltage
`selection circuit of the power system;
`FIG. 5 illustrates the equivalent circuit of a portion of
`the voltage selection section of the power system for
`low current operation of the power system; and
`FIG. 6 illustrates the equivalent circuit of the same
`portion of the voltage selection circuit as illustrated in
`FIG. 5, but under high current and high voltage condi(cid:173)
`tions.
`
`3
`the 5 volt limit without regard to the magnitude of the
`current being drawn by the computer system.
`It is an object of the present invention to provide a
`power system having a plurality of voltage outputs
`available and a processor clock having a variable fre- 5
`quency to permit the operation of the system to be
`performed at the lowest voltage and frequency based on
`the demand of the system to reduce the power con(cid:173)
`sumption.
`It is a further object of the present invention to re- 10
`duce the operating frequency of the processor by
`changing the frequency of the VCO in order to pre(cid:173)
`serve the integrity of data under conditions such as
`when the battery voltage is below that required to oper(cid:173)
`ate the system without loss of data and in those situa- 15
`tions in which the power supply voltage can not be
`maintained because of the excessive loading on the
`system.
`In accordance with the present invention, a power
`system is provided for use with a computer, with a 20
`power system automatically establishing the magnitude
`of the supply voltage provided to the computer in re(cid:173)
`sponse to the magnitude of the current being supplied
`by the power supply to the computer, the power system
`comprising a supply voltage generating circuit, a volt(cid:173)
`age selection circuit for automatically changing the
`magnitude of the supply voltage based on the current
`demands of the computer system, with the automatic
`voltage selection circuit including means for monitoring 30
`the magnitude of the current drawn by the computer
`system.
`In accordance with another feature of the present
`invention, the system clock frequency is changed in
`response to the magnitude of the supply voltage. Also, 35
`the system clock operates over a continuous range of
`stable voltage and frequency operating points.
`In accordance with another feature of the present
`invention, the power system includes a battery change
`backup circuit for providing supply voltage to the sys- 40
`tern during a battery change operation.
`In accordance with yet another feature of the present
`invention, the power system includes a battery condi(cid:173)
`tion monitor circuit for providing an output to the com(cid:173)
`puter indicative of the charge condition of the battery. 45
`In accordance with yet another feature of the present
`invention, an automatic voltage selection override cir(cid:173)
`cuit is provided which, in response to a control signal
`from the computer system, causes the supply voltage to
`be limited to a predetermined maximum without regard 50
`to the current being drawn by the computer system.
`In accordance with a further feature of the invention,
`a temperature compensation circuit is provided to in(cid:173)
`crease the supply voltage as the ambient temperature
`increases to maintain the devices in the circuit operating 55
`efficiently as their resistance increases with the increase
`in temperature.
`
`25
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`Referring to FIG. 1, power system 13 of the present
`invention is illustrated in schematic form and for conve(cid:173)
`nience of description is divided into functional blocks
`indicated by dashed lines around sections of the sche-
`matic. Si.;pply voltage VDD produced by power system
`13 is utilized throughout the computer system and as
`stated above, may be switched between three and five
`volts based upon the power demands of the computer
`system or based upon voltage selection control from the
`computer
`system which
`is provided over
`lines
`SEL VDD. The lines SEL VDD, LOW BAT /DEAD
`BAT, and BA TMON indicated in the lower right hand
`portion of the figure adjacent to reference character 17
`are control lines coming from and condition indication
`lines ,going to peripheral ASIC of the computer system,
`- which is illustrated in the above-identified copending
`patent application. The control over SEL VDD from
`the computer system is used to place the power system
`13 in either the automatic or the override/forced mode
`to establish the value of supply voltage VDD. The
`operation of the power system will be explained in
`detail hereinafter, however for the purposes of intro(cid:173)
`duction a LOW on SEL VDD line (LOW indicating
`ground) will force the magnitude ofVDD to be approx-
`imately five volts and the power system will be regu(cid:173)
`lated to maintain VDD at that level. A second condition
`for SEL VDD is to provide for automatic operation in
`which the magnitude of VDD is automatically deter(cid:173)
`mined. That is, an output of VDD of three volts or five
`volts depends upon the current drawn by the system,
`and this automatic mode is established by placing
`SEL VDD at float or VDD. With SEL VDD at float or
`60 VDD, the magnitude of the current drawn by the sys(cid:173)
`tem determines whether the output will be three or five
`volts. Under most circumstances it is preferable that the
`system output voltage (VDD) be three volts. However,
`it has been found that the preferable parameters for
`changing VDD from three volts to five volts is that the
`current requirements of the system be equal to or
`greater than 10 milliamps and that in addition this flow
`level continue for approximately 500 milliseconds.
`
`BRIEF DESCRIPTION OF THE ORA WINGS
`Other objects and advantages of the invention will
`become apparent from a study of the specification and
`drawings in which:
`FIG. 1 illustrates the power system;
`FIG. 2A illustrates system clock circuit 18 for use in
`conjunction with the power system of FIG. 1, and FIG. 65
`2A also illustrates oscillator circuit 19 which is a second
`oscillator for a computer system utilizing the power
`system of FIG. 1;
`
`MICROCHIP TECH. INC. - EXHIBIT 1019
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 010
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`

`5,021,679
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`5
`The BA TMON line is utilized to control the opera(cid:173)
`tion of the battery condition monitor portion of the
`power system. The source of potential for the power
`system is battery BTl, which is preferably a pair of AA
`alkaline cells with initial output of approximately three 5
`volts. When the battery voltage drops to 1.8 volts, a low
`battery indication is provided on the LOW BAT/(cid:173)
`DEAD BAT line and when the battery voltage reaches
`approximately 1.6 volts, a dead battery indication is
`provided to the system over the LOW BAT /DEAD 10
`BAT line.
`A battery change backup circuit, indicated within the
`dashed line to the right hand portion of FIG. 1, pro(cid:173)
`vides a source of supply voltage for battery change. The
`operation of the battery change circuit will be explained 15
`hereinafter. The remaining portions of power system 13
`include the voltage selection section and the supply
`voltage generation section.
`The supply voltage generation section includes bat(cid:173)
`tery BTl having its negative terminal grounded and its 20
`positive terminal connected to line V BAIT• Included in
`the supply voltage generation section is bipolar transis-
`tor Tl, having its emitter connected to V BA IT, its col(cid:173)
`lector connected to one terminal of resistor R18, which 25
`is in turn connected to resistor RlS which is connected
`to ground. A pair of switching transistor T2 and T3 are
`coupled in parallel for current handling purposes, each
`of their emitters being connected to ground, their col(cid:173)
`lectors commonly connected and their bases commonly 30
`connected and coupled to the junction between resistor
`R18 and resistor RlS. Included in the primary current
`flow path of transistors T2 and T3 is inductor Ll, hav-
`ing one terminal thereof connected to the commonly
`connected collectors of transistors T2 and T3, and its 35
`other terminal connected to V BAIT line. Feedback be(cid:173)
`tween the collectors of transistors T2 and T3 and the
`base of transistors Tl is achieved by a first path with
`includes capacitor C23 and a second path which in(cid:173)
`cludes resistor R16 and Schottky diode DlO. Schottky 40
`diode DlO may be, for example, a Hewlett Packard
`Corporation Schottky diode part number HP-5082-
`2810. Resistor R22 provides a path to ground from the
`base of transistor Tl. Schottky diode D9 is coupled
`between node N4 and node Nl. Capacitor C24 is cou- 45
`pied between node Nl and ground. The supply voltage
`circuit of power system 13 provides a DC to DC -con(cid:173)
`version of the voltage from battery BTl, this conver(cid:173)
`sion being performed by the oscillator function of the
`supply voltage circuit which includes transistors Tl, 50
`T2, and T3, along with their feedback paths, switching
`on and off. The energy stored in inductor Ll while it is
`conducting is converted, upon the switching of transis(cid:173)
`tors T2 and T3 to a nonconducting state, to a DC volt(cid:173)
`age by the rectification through diode D9. The resulting 55
`storage of DC potential produces VDD at node Nl.
`More detail of the operation of the supply voltage sec(cid:173)
`tion will be provided hereinafter in a general descrip(cid:173)
`tion of the power system operation. In practicing the
`present invention the above described supply voltage 60
`generation circuit, which is regulated by an ON-OFF
`regulation method which is described hereinafter, is the
`prefe:,. cd circuit for use in generating the supply volt(cid:173)
`age(\ DD). However, in practicing our invention other
`types of supply voltage generation circuits, such as, for 65
`example, a linear series regulator circuit, may be uti(cid:173)
`lized. An example of this latter type of circuit is the
`National Semiconductor 3-Terminal Adjustable Regu-
`
`6
`lator available under part numbers LM117, LM217 and
`LM317.
`Turning to the voltage selection section illustrated in
`FIG. 1, this section provides voltage regulation as well
`as voltage selection. As pointed out above, this voltage
`selection may be automatic as a result of the amount of
`current ·supplied to the system over VDD line or may
`be established at a predetermined level depending on
`the control signal on line SEL VDD, In the present
`invention the supply voltage circuit is implemented
`using a switching DC to DC converter and the magni(cid:173)
`tude of the current supply to the system is sensed based
`on the duty cycle of the oscillator in the supply voltage
`circuit. It will of course be appreciated that the present
`invention may be practiced by utilizing a supply voltage
`circuit other than a DC to DC switching supply. The
`voltage selection section is also illustrated in FIG. 4 in
`a larger scale and reference to FIG. 4 in addition to
`FIG. 1 may be helpful in understanding the description
`of the circuit operation as well as its interconnection to
`the remaining portion of power system 13. To establish
`a point of reference from which to determine and regu(cid:173)
`late the supply voltage VDD, a reference voltage is
`generated at node N3 by connecting resistor R13 be(cid:173)
`tween V BAIT and node 3 and connecting the Zener
`diode D6 between node 3 and ground. As illustrated in
`FIGS. 1 and 4, anode 1 of Zener diode D6 is connected
`to ground and cathode 2 of Zener diode D6 is con(cid:173)
`nected to node 3. It has been found advantageous to use
`for diode D6 a Motorola Inc. 1.2 volt band gap refer(cid:173)
`ence diode, part number LM385, which provides a
`potential of 1.2 volts at node N3. Current limiting resis(cid:173)
`tor R13 has a value preferably of 100 K ohms. Node N3
`is connected to the noninverting input of comparator
`USA. The inverting input of comparator USA is con(cid:173)
`nected to node N2. The voltage at node N2, which is
`established by voltage divider action, current level to
`the computer system and the control signal over
`SEL VDD from the computer system, determines the
`voltage level to which the power system regulates
`VDD to achieve either, in the preferred embodiment,
`three or five volts. Resistor Rl2, preferably 270 K
`ohms, is connected between VDD and node N2. Diode
`DU has its anode 3 connected to node N2, its cathode
`4 connected to one terminal of resistor RU (preferably
`75 K ohms) and the other terminal of resistor RU is
`connected to ground. Diode DU may be for example a
`Motorola
`Inc. 1N914 silicon diode, part number
`MMBD914L. Diode DU serves to provide tempera(cid:173)
`ture compensation for the power system, which will be
`more fully described hereinafter. Resistor R21 is con(cid:173)
`nected between node N2 and node NS and resistor RIO
`is connected between VDD and node NS. Capacitor
`C26 has one terminal connected to node NS and the
`other to ground. Connected between node NS and node
`N6 is resistor R19 (preferably 6.2 K ohms) and between
`node N6 and ground is connected capacitor C22, hav(cid:173)
`ing a capacitance of 0.1 µ,f. Diode D13 (which may be
`of the same type as diode DU) has its cathode S con(cid:173)
`nected to control line SEL VDD, and its anode 6 con(cid:173)
`nected to node NS. When diode 13 is forward biased by
`providing ground to cathode S via line SEL VDD, the
`resulting voltage level at node NS will cause VDD to be
`regulated at five volts independent of the current drawn
`by the computer system. How this is achieved will be
`explained fully in the operational description of the
`voltage selection circuit.
`
`MICROCHIP TECH. INC. - EXHIBIT 1019
`MICROCHIP TECH. INC. V. HD SILICON SOLS. - IPR2021-01265 - Page 011
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`5,021,679
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`7
`To provide an indication of the level of current being
`drawn by the computer system, a novel circuit compris(cid:173)
`ing resistor R19 (6.2 K ohms), which is connected be(cid:173)
`tween node NS and node N6, along with Schottky
`diode D14 which has its anode 7 connected to node N6 5
`and its cathode 8 connected to node N4, and capacitor
`C22 (0.1 µf) which is coupled between node N6 and
`ground, provides to the voltage selection section an
`indication of the magnitude of the current supplied to
`the computer system over supply voltage line VDD. 10
`Schottky diode D14 may be for example a Hewlett
`Packard Corporation Schottky diode part number HP-
`508202810 and Schottky diode D9 may be, for example,
`a General Instruments Corporation Schottky diode part
`number SGL41-30.
`Comparator USA operates to regulate the on/off
`switching of the oscillator in the supply voltage circuit.
`The output of comparator USA is connected via line 9
`to resistor R17 (30 K ohms) which is connected to the
`base of transistor T4. Transistor T4 has its emitter con- 20
`nected to V BATT line and its collector connected to the
`base of transistor Tl in the supply voltage circuit. Pull
`up resistor R14 is connected between V BA TT line and
`the base of transistor T4. Transistor T4 may be for
`example a Motorola Inc. part number MMPQ6700. The 25
`necessity of having the oscillator in supply voltage
`circuit of the power system 13 running to produce DC
`voltage at node Nl to keep supply voltage line VDD at
`a prescribed level is determined by the relative voltages
`at node N2 and N3 which are connected to comparator 30
`USA at the inverting and noninverting inputs respec(cid:173)
`tively. The output signal on line 9 from comparator
`USA controls the conduction of transistor T4 and the
`voltage on the collector of transistor T4 determines
`whether transistor Tl is conducting or nonconducting. 35
`Briefly, when transistor T4 is conducting, transistors
`Tl, T2 and T3 in supply voltage circuit are nonconduct(cid:173)
`ing and correspondingly the converse applies; that is,
`when T4 is in a nonconducting state, transistors Tl, T2
`and T3 are permitted to conduct allowing current to 40
`flow through inductor Ll. When transistors T2 and T3
`turn off, the energy stored in Ll is released through
`Schottky diode D9 where it is rectified and supply
`voltage VDD generated and stored on capacitor C24.
`More details of the operation of this circuit will follow. 45
`To help ensure that system data is not lost when the
`charge condition of the battery becomes low, battery
`condition monitor circuit (illustrated in FIG. 1) is in(cid:173)
`cluded in power system 13 to warn the user of the low
`battery condition. The battery condition monitor in- 50
`eludes a comparator USB, which receives a control
`signal from the peripheral ASIC of the computer sys(cid:173)
`tem over BA TMON line which is connected to the
`inverting input of comparator USB through resistor
`R29. The output of comparator USB provides a signal 55
`on the LOW BAT /DEAD BAT line to the computer
`to indicate a low battery or dead battery condition
`which is sensed by the battery condition monitor. The
`V BATT line connected to the inverting input of compara(cid:173)
`tor USB through resistor R26 and the junction of resis- 60
`tors R26 and R29 is coupled to ground through resistor
`R27. Power to comparator USB is provided by conduc(cid:173)
`tor 10 which connects the VDD line to the power input
`terminal of comparator USB. Comparator USB is of
`course also grounded, which connection is not shown. 65
`Feedback resistor R28 is connected between the LOW
`BAT /DEAD BAT line and conductor 10. The opera(cid:173)
`tion of the battery condition monitor circuit will be
`
`8
`described hereinafter in the overall description of the
`operation of the power system.
`To provide power to the system so that operations
`may continue during the replacement of weak or dead
`batteries, battery change backup circuit, illustrated in
`dashed line to the right hand portion of FIG. 1, is pro-
`vided. Battery change backup circuit includes diode D8
`having its anode 12 connected to VDD
`line and its
`cathode connected to one terminal of capacitor C21.
`The second terminal of capacitor C21 is connected to
`ground. The capacitance of C21 is preferably 0.047
`farads. Capacitor C21 serves to store a charge and pro(cid:173)
`vide operating potential to the system when the batter(cid:173)
`ies are removed. The other leg of the battery change
`15 backup circuit includes diode D7 and transistor TS.
`Cathode 15 of diode D7 is connected to VDD supply
`line, and anode 16 of diode D7 is connected to the emit(cid:173)
`ter of transistor TS. The base and collector of transistor
`TS are tied together and conn