Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`MICROCHIP TECHNOLOGY INC.,
`Petitioner,
`
`v.
`
`HD SILICON SOLUTIONS LLC
`Patent Owner
`
`
`
`Case No. IPR2021-01265
`U.S. Patent No. 7,870,404
`Issue Date: January 11, 2011
`
`Title: TRANSITIONING TO AND FROM A SLEEP STATE OF A PROCESSOR
`
`
`
`
`
`DECLARATION OF DONALD ALPERT, PH.D. IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 7,870,404
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
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`

`

`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`
`
`TABLE OF CONTENTS
`
`
`I.
`
`INTRODUCTION AND QUALIFICATIONS ............................................... 1
`
`A.
`
`B.
`
`Introduction ........................................................................................... 1
`
`Qualifications and Experience .............................................................. 2
`
`C. Materials Considered ............................................................................. 5
`
`II.
`
`LEGAL PRINCIPLES ..................................................................................... 8
`
`A.
`
`B.
`
`Prior Art ................................................................................................. 8
`
`Claim Construction................................................................................ 8
`
`C. Anticipation .........................................................................................12
`
`D. Obviousness .........................................................................................13
`
`III. LEVEL OF ORDINARY SKILL IN THE ART ...........................................19
`
`IV. TECHNOLOGY BACKGROUND ...............................................................20
`
`A.
`
`Power and Energy Consumption of Computer Systems .....................22
`
`1.
`
`2.
`
`3.
`
`4.
`
`CMOS and Power .....................................................................22
`
`Slowing the Clock .....................................................................23
`
`Stopping the Clock ....................................................................24
`
`Dynamic Voltage-Frequency Scaling (DVFS) .........................25
`
`Registers and Static Random Access Memory (SRAM) ....................28
`
`Response Time ....................................................................................34
`
`1.
`
`2.
`
`Interrupts ...................................................................................35
`
`Cache Snoops ............................................................................38
`
`B.
`
`C.
`
`
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`D. Voltage Regulation ..............................................................................41
`
`V.
`
`THE ’404 PATENT .......................................................................................45
`
`A. Overview of the ’404 patent ................................................................45
`
`B.
`
`C.
`
`Prosecution History .............................................................................50
`
`The Challenged Claims .......................................................................57
`
`VI. APPLICATION OF THE PRIOR ART TO ASSERTED CLAIMS ............65
`
`A.
`
`Brief Summary of Prior Art ................................................................66
`
`1.
`
`Ground 1 Prior Art ....................................................................66
`
`B.
`
`GROUND 1: Claims 1-21 Are Unpatentable as Obvious Over
`NEC-Databook in View of Stratakos, Further in View of the
`Knowledge of a POSITA ....................................................................79
`
`1. Motivation to Combine NEC-Databook and Stratakos ............79
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`Independent Claim 1 .................................................................99
`
`Claim 2 ....................................................................................157
`
`Claim 3 ....................................................................................166
`
`Claim 4 ....................................................................................167
`
`Claim 5 ....................................................................................168
`
`Claim 6 ....................................................................................171
`
`Independent Claim 7 ...............................................................173
`
`Claim 8 ....................................................................................195
`
`10. Claim 9 ....................................................................................195
`
`11. Claim 10 ..................................................................................199
`
`12.
`
`Independent Claim 11 .............................................................200
`
`13. Claim 12 ..................................................................................214
`
`
`
`ii
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`14. Claim 13 ..................................................................................217
`
`15. Claim 14 ..................................................................................217
`
`16.
`
`Independent Claim 15 .............................................................220
`
`17. Claim 16 ..................................................................................225
`
`18. Claim 17 ..................................................................................231
`
`19.
`
`Independent Claim 18 .............................................................233
`
`20. Claim 19 ..................................................................................246
`
`21. Claims 20 and 21.....................................................................247
`
`VII. NO SECONDARY CONSIDERATIONS OF NON-OBVIOUSNESS .....248
`
`VIII. CONCLUSION ............................................................................................251
`
`
`
`iii
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`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`I, Donald Alpert, Ph.D., declare as follows:
`
`I.
`
`INTRODUCTION AND QUALIFICATIONS
`
`A.
`
`1.
`
`Introduction
`
`I am an independent consultant with Camelback Computer
`
`Architecture, LLC. My residence and place of business is at 2020 21st Street,
`
`Sacramento, CA 95818. I am over the age of eighteen, and I am a citizen of the
`
`United States.
`
`2.
`
`I have been retained by Microchip Technology, Inc. (“Microchip” or
`
`“Petitioner”) as a technical expert witness in connection with the petition for inter
`
`partes review of U.S. Patent No. 7,870,404 (“’404 patent”). I understand that the
`
`ʼ404 patent claims priority to October 23, 2000. For purposes of my analysis
`
`herein, I have used this date as the relevant time period.
`
`3.
`
`I have been asked by Petitioner to offer opinions regarding the ʼ404
`
`patent, including the construction of certain claim terms and the patentability of the
`
`claims in view of certain prior art references and the knowledge of a person of
`
`ordinary skill in the art (“POSITA”). This declaration sets forth the opinions I
`
`have reached to date regarding these matters.
`
`4.
`
`In preparing this Declaration, I have reviewed the ʼ404 patent, its
`
`prosecution history, and each of the documents I reference herein. In reaching my
`
`
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`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`opinions, I have relied upon my experience in the field and have also considered
`
`the viewpoint of a POSITA at the time of the ‘404 patent’s priority date. As
`
`explained below, I am familiar with the level of skill of a POSITA regarding the
`
`technology at issue as of that time frame.
`
`5.
`
`Camelback Computer Architecture is being compensated for my time
`
`working on this matter at my standard hourly rate of $600 per hour, plus expenses.
`
`Neither Camelback Computer Architecture nor I have any personal or financial
`
`stake or interest in the outcome of the present proceeding, and the compensation is
`
`not dependent on the outcome of this IPR and in no way affects the substance of
`
`my statements in this declaration.
`
`B. Qualifications and Experience
`
`6. My qualifications for forming the opinions set forth in this
`
`Declaration are summarized here and explained in more detail in my curriculum
`
`vitae, which is attached as Exhibit Ex.1009.
`
`7.
`
`I have 45 years of academic and industrial experience in applying,
`
`designing, studying, teaching, and writing about microprocessors and computer
`
`systems. I received an Electrical Engineering Ph.D. degree in 1984 from Stanford
`
`University. I earlier received an Electrical Engineering B.S. degree from MIT in
`
`1973 and an Electrical Engineering M.S. degree from Stanford University in 1978.
`
`
`
`2
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`

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`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`I have taught classes in computer architecture at Stanford, Tel Aviv, and Arizona
`
`State Universities.
`
`8.
`
`From 1976 to 1977, I worked at Burroughs Corporation, where I
`
`designed peripheral interface controllers, including those for serial data
`
`communications based on Intel 8080 microprocessor components. From 1980 to
`
`1989, I was the lead architect for the design of three high-performance
`
`microprocessors at Zilog and National Semiconductor. Later, at Intel, I was the
`
`lead architect of the Pentium® Processor from 1989 to 1992 and of the 815 chipset
`
`from 1999 to 2000, both of which became the most widely used PC components of
`
`their time. The 815 chipset comprised two components: (1) a memory controller
`
`hub (MCH) that included a graphics controller and memory controller with
`
`interfaces to the CPU, 133 MHz SDRAM system memory modules, an optional,
`
`external graphics controller and (2) an I/O controller hub (ICH) that included
`
`various I/O controllers (e.g., network, hard drive, USB) for system peripheral
`
`devices and power management control registers. Additionally, I served as co-
`
`manager for the Itanium processor design from 1993-1997.
`
`9.
`
`I am a Senior Member of the Institute of Electrical and Electronics
`
`Engineers (IEEE), and served as the chair of the IEEE Technical Committee on
`
`Microprocessors and Microcomputers from 1999 to 2000. I was the keynote
`
`
`
`3
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`

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`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`speaker at the first Cool Chips conference, dedicated to the study of low-power
`
`microprocessors and systems. I have given invited lectures at several universities,
`
`and published ten papers in various professional journals and conference
`
`proceedings. My paper entitled “Architecture of the Pentium Processor,” was
`
`selected as best paper in IEEE Micro for 1993. I am a named inventor on over 30
`
`U.S. patents that pertain to microprocessors, computer systems, and related
`
`technology.
`
`10.
`
`I have reviewed the ’404 Patent, and I am familiar with the patent’s
`
`subject matter, which is within the scope of my education and professional
`
`experience. Based at least on my background in academia, industry, and
`
`consulting, I am familiar with the issues and technology relating to processors,
`
`chipsets, memory, peripheral devices, and power management for computer
`
`systems. I have personally analyzed, developed, and tested such computer
`
`components and systems. More specifically, the Pentium® Processor and 815
`
`chipset for which I was the lead architect at Intel implemented various features for
`
`supporting power management, including those related to Advanced Power
`
`Management (APM) and Advanced Configuration and Power Interface
`
`Specification (ACPI) industry standards.
`
`
`
`4
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`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`
`C. Materials Considered
`
`11. The analysis that I provide in this Declaration is based on my
`
`education and experience in the field of computer systems, as well as the
`
`documents I have considered, including the ’404 patent (Ex.1001) and its
`
`prosecution history (Ex.1003). The ’404 patent states on its face that it issued from
`
`Application No. 11/894,991, which claims priority to Application No. 09/694,433
`
`(issued as U.S. Patent No. 7,260,731), filed on Oct. 23, 2000. For the purposes of
`
`this Declaration, I have been instructed to assume Oct. 23, 2000 as the effective
`
`filing date for the ʼ404 patent. I have cited to the following documents in my
`
`analysis below:
`
`EXHIBIT NO.
`
`DESCRIPTION
`
`1001
`
`U.S. Patent No. 7,870,404
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`Prosecution History for U.S. Patent Application No.
`11/894,991, which issued as U.S. Patent No. 7,870,404
`
`Excerpts from Single-Chip Microcomputer Databook, NEC
`Electronics Inc. (May 1990)
`
`Anthony J. Stratakos, High-Efficiency Low-Voltage DC-DC
`Conversion for Portable Applications (1998)
`
`Advanced Configuration and Power Interface Specification,
`Intel/Microsoft/Toshiba, Rev. 1.0 (Dec. 22, 1996)
`
`Allan Baril, Using Windows NT in Real-Time Systems, Spar
`Aeorospace Ltd.
`
`
`
`5
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`

`

`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`
`EXHIBIT NO.
`
`DESCRIPTION
`
`1008
`
`PCI Local Bus Specification, PCI Special Interest Group
`Rev. 2.2 (Dec. 18, 1998)
`
`1009
`
`Curriculum Vitae of Dr. Donald Alpert
`
`1014
`
`Prosecution History for U.S. Patent Application No.
`11/894,991 (issued as U.S. Patent No. 7,260,731)
`
`1015
`
`U.S. Patent No. 3,941,989
`
`1016
`
`U.S. Patent No. 4,293,927
`
`1017
`
`CMOS, the Ideal Logic Family
`
`1018
`
`Inki Hong, et al., “Synthesis Techniques for Low-Power
`Hard Real-Time Systems on Variable Voltage Processors,”
`in Proceedings of the 19th IEEE Real-Time Systems
`Symposium, at 178 (Dec. 1998)
`
`1019
`
`U.S. Patent No. 5,021,679
`
`1020
`
`“Terms, Definitions, and Letter Symbols for
`Microcomputers, Microprocessors, and Memory Integrated
`Circuits,” JEDEC Standard JESD-100A (Aug. 1993)
`
`1021
`
`U.S. Patent No. 5,898,235
`
`1022
`
`U.S. Patent No. 6,347,379
`
`1023
`
`L. L. Vadasz, et al., “Silicon-Gate Technology,” IEEE
`Spectrum, vol. 6 no. 10 at 35 (October 1969)
`
`
`
`6
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`

`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`
`EXHIBIT NO.
`
`DESCRIPTION
`
`1024
`
`1025
`
`“Interrupt Latency in 80386EX Based System,” Intel
`Technical Note 2153 (1998)
`
`“PowerPC 604e RISC Microprocessor User’s Manual,”
`Motorola MPC604EUM/AD (Mar. 1998)
`
`1026
`
`U.S. Patent No. 5,677,558
`
`1027
`
`1028
`
`1029
`
`Bang S. Lee, “Technical Review of Low Dropout Voltage
`Regulator Operation and Performance,” Texas Instruments
`Application Report SLVA072 (Aug. 1999)
`
`Bob Wolbert, “Micrel’s Guide to Designing With Low-
`Dropout Voltage Regulators,” (Dec. 1998)
`
`Jim Williams, “Step-Down Switching Regulators,” Linear
`Technology Application Note 35 (Aug. 1989)
`
`1030
`
`U.S. Patent No. 5,731,731
`
`1031
`
`1032
`
`VIA Technologies, Inc., “VT82C586B PIPC PCI Integrated
`Peripheral Controller,” Revision 1.0 (May 13, 1997)
`
`Mobile Power Guidelines ‘99, Rev. 1.00, Intel Corporation
`(December 1, 1997
`
`1033
`
`U.S. Patent No. 6,212,094
`
`Richard B. Lam et al., “Multitasking in Laboratory Personal
`Computers,” 63 Analytical Chemistry, 30A-40A (January
`1991)
`
`U.S. Patent No. 7,451,447 (“Deshpande”)
`
`1034
`
`1035
`
`
`
`7
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`

`

`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`
`EXHIBIT NO.
`
`DESCRIPTION
`
`1036
`
`1037
`
`Intel, lntel486™ Family of Microprocessors - Low Power
`Version Data Sheet (Dec. 1992).
`
`Intel, Introduction to the Intel386TM SL Microprocessor
`SuperSet Technical Overview (1991)
`
`II. LEGAL PRINCIPLES
`
`12.
`
`I am not an attorney. For purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my analysis and
`
`opinions, as set forth below.
`
`A.
`
`Prior Art
`
`13.
`
`I understand that the prior art to the ʼ404 patent includes patents and
`
`printed publications in the relevant art that predate the ʼ404 patent’s priority date.
`
`As I explained previously, I have been instructed to assume for purposes of my
`
`analysis that Oct. 23, 2000 is the relevant date for determining what is “prior art.”
`
`In other words, I should consider as “prior art” anything publicly available prior to
`
`Oct. 23, 2000. I further understand that, for purposes of this proceeding in the
`
`United States Patent Trial and Appeal Board, only patents and documents that have
`
`the legal status of a “printed publication” may be relied on as prior art.
`
`B. Claim Construction
`
`14.
`
`I understand that under the legal principles, claim terms are generally
`
`
`
`8
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`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`given their ordinary and customary meaning, which is the meaning that the term
`
`would have to a POSITA in question at the time of the invention, i.e., as of the
`
`effective filing date of the patent application. I further understand that a POSITA
`
`is deemed to read the claim term not only in the context of the particular claim in
`
`which a claim term appears, but in the context of the entire patent, including the
`
`specification.
`
`15.
`
`I am informed by counsel that the patent specification, under the legal
`
`principles, has been described as the single best guide to the meaning of a claim
`
`term, and is thus highly relevant to the interpretation of claim terms. I understand
`
`for terms that do not have a customary meaning within the art, the specification
`
`usually supplies the best context of understanding the meaning of those terms.
`
`16.
`
`I am further informed by counsel that other claims of the patent in
`
`question, both asserted and unasserted, can be valuable sources of information as
`
`to the meaning of a claim term. Because the claim terms are normally used
`
`consistently throughout the patent, the usage of a term in one claim can often
`
`illuminate the meaning of the same term in other claims. Differences among
`
`claims can also be a useful guide in understanding the meaning of particular claim
`
`terms.
`
`17.
`
`I understand that the prosecution history can further inform the
`
`
`
`9
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`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`meaning of the claim language by demonstrating how the inventors understood the
`
`invention and whether the inventors limited the invention in the course of
`
`prosecution, making the claim scope narrower than it otherwise would be.
`
`Extrinsic evidence may also be consulted in construing the claim terms, such as my
`
`expert testimony.
`
`18.
`
`I have been informed by counsel that, in IPR proceedings, a claim of a
`
`patent shall be construed using the same claim construction standard that would be
`
`used to construe the claim in a civil action filed in a U.S. district court (which I
`
`understand is called the “Phillips” claim construction standard), including
`
`construing the claim in accordance with the ordinary and customary meaning of
`
`such claim as understood by one of ordinary skill in the art and the prosecution
`
`history pertaining to the patent.
`
`19.
`
`I have been instructed by counsel to apply the “Phillips” claim
`
`construction standard for purposes of interpreting the claims in this proceeding, to
`
`the extent they require an explicit construction. The description of the legal
`
`principles set forth above thus provides my understanding of the “Phillips”
`
`standard as provided to me by counsel.
`
`20.
`
`I understand that some claims are independent, and that these claims
`
`are complete by themselves. Other claims refer to these independent claims and
`
`
`
`10
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`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`are “dependent” from those independent claims. The dependent claims include all
`
`the limitations of the claims on which they depend.
`
`21.
`
`I am further informed and understand that certain claim elements
`
`recite “means for” or “means to,” and may therefore be understood as reciting
`
`means-plus-function limitations. I am also informed and understand that,
`
`accordingly, the analysis of each of these claim elements may require the
`
`identification of a respective function recited in each of these claim elements, and
`
`the identification of a respective structure that is disclosed in the specification or
`
`file history of the ʼ404 patent, where the respective identified structure is linked to
`
`and performs the respective recited function.
`
`22.
`
`I am additionally informed and understand that to show that the prior
`
`art teaches any particular one of these claim elements, the prior art should disclose
`
`a structure that performs the function recited in the particular claim element, where
`
`the structure disclosed in the prior art is the same as or equivalent to the structure
`
`disclosed in the ʼ404 patent that performs the recited function.
`
`23.
`
`I am also informed and understand that the determination of
`
`equivalence under 35 U.S.C. § 112 does not involve the function-way-result test
`
`that is generally applied under the doctrine of equivalents in determining
`
`infringement of a claim. Rather, I am informed and understand, that equivalence is
`
`
`
`11
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`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`determined by comparing the prior art structure that performs the claimed function
`
`with the structure disclosed in the specification.
`
`C. Anticipation
`
`24.
`
`I understand that to anticipate a patent claim under 35 U.S.C. § 102, a
`
`single asserted prior art reference must disclose each and every element of the
`
`claimed invention, either explicitly, implicitly, or inherently, to a POSITA. There
`
`must be no difference between the claimed invention and the disclosure of the
`
`alleged prior art reference as viewed from the perspective of a POSITA. Also, I
`
`understand that in order for a reference to be an anticipating reference, it must
`
`describe the claimed subject matter with sufficient clarity to establish that the
`
`subject matter existed and that its existence was recognized by persons of ordinary
`
`skill in the field of the invention. In addition, I understand that in order to establish
`
`that an element of a claim is “inherent” in the disclosure of an asserted prior art
`
`reference, extrinsic evidence (or the evidence outside the four corners of the
`
`asserted prior art reference) must make clear that the missing element is
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`necessarily found in the prior art, and that it would be recognized as necessarily
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`present by persons of ordinary skill in the relevant field.
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`25.
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`In my opinions below, when I say that a POSIA would have
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`understood, readily understood, or recognized that an element or aspect of a claim
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`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
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`is disclosed by a reference, I mean that the element or aspect of the claim is
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`disclosed to a POSITA.
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`D. Obviousness
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`26.
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`I understand that obviousness is a determination of law based on
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`various underlying determinations of fact. In particular, these underlying factual
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`determinations include (1) the scope and content of the prior art; (2) the level of
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`ordinary skill in the art at the time the claimed invention was made; (3) the
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`differences between the claimed invention and the prior art; and (4) the extent of
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`any proffered objective indicia of nonobviousness. I understand that the objective
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`indicia which may be considered in such an analysis include commercial success
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`of the patented invention (including evidence of industry recognition or awards),
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`whether the invention fills a long-felt but unsolved need in the field, the failure of
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`others to arrive at the invention, industry acquiescence and recognition, initial
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`skepticism of others in the field, whether the inventors proceeded in a direction
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`contrary to the accepted wisdom of those of ordinary skill in the art, and the taking
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`of licenses under the patent by others, among other factors.
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`27. To ascertain the scope and content of the prior art, it is necessary to
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`first examine the field of the inventor’s endeavor and the particular problem for
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`which the invention was made. The relevant prior art includes prior art in the field
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`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`of the invention, and also prior art from other fields that a POSITA would look to
`
`when attempting to solve the problem.
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`28.
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`I understand that a determination of obviousness cannot be based on
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`the hindsight combination of components selectively culled from the prior art to fit
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`the parameters of the patented invention. Instead, it is my understanding that in
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`order to render a patent claim invalid as being obvious from a combination of
`
`references, there must be some evidence within the prior art as a whole to suggest
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`the desirability, and thus the obviousness, of making the combination in a way that
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`would produce the patented invention.
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`29.
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`I further understand that in an obviousness analysis, neither the
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`motivation nor the purpose of the patentee dictates. What is important is whether
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`there existed at the time of the invention a known problem for which there was an
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`obvious solution encompassed by the patent’s claims.
`
`30.
`
`I also understand that the combination of familiar elements according
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`to known methods is likely to be obvious when it yields predictable results. I also
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`understand that an example of a solution in one field of endeavor may make that
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`solution obvious in another related field, as well. I am informed that market
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`demands or design considerations may prompt variations of a prior art system or
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`process, in the same field or a different one, where such variations may ordinarily
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`
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`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`be considered obvious, straightforward changes to what has been explicitly
`
`disclosed in the prior art.
`
`31.
`
`I also understand that if a POSITA could have implemented a
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`predictable variation without excessive experimentation, that variation would have
`
`been considered obvious. I understand that for similar reasons, if a technique has
`
`been used to improve one device or processor, and a POSITA would have
`
`recognized that that technique can improve a similar devices or process in the same
`
`way, implementing such an improvement would have been obvious, unless the
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`implementation yields unexpected results or challenges in implementation.
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`32.
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`I understand that the obviousness analysis need not seek out precise
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`teachings directed to the specific subject matter of the challenged claim. Rather, I
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`understand, that the analysis can take into account ordinary innovation and
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`experimentation, e.g., inferences and creative steps that a POSITA would employ,
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`that yields predictable, benefits. In this regard, I understand that a POSITA is also
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`a person of ordinary creativity.
`
`33.
`
`I understand that sometimes it will be necessary to consider
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`interrelated teachings of several prior art references, the demands or current
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`problems known in the design community or present in the marketplace, and/or the
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`background knowledge of a POSITA. I understand that any of these factors may
`
`
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`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`be considered to assess whether there was a reason to combine the teachings of the
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`prior art references, where the combination would reveal the system or process
`
`claimed in the challenged patent.
`
`34.
`
`I understand that the obviousness analysis is not limited to a
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`formalistic conception of “teaching, suggestion, and motivation.” I understand that
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`in 2007, the Supreme Court issued its decision in KSR Int’l Co. v. Teleflex, Inc.,
`
`550 U.S. 398, 418 (2007), where the Court rejected the previous requirement of a
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`“teaching, suggestion, or motivation to combine” known elements of prior art as a
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`precondition for concluding that a combination of those elements would be
`
`obvious. It is my understanding that KSR confirms that any rational reason or
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`motivation that would have been known to a POSITA, including common sense,
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`one derived from the nature of the problem to be solved, etc., can be sufficient to
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`explain why such known prior art elements from one or more prior art references
`
`would have been combined.
`
`35.
`
`I understand that a POSITA attempting to solve a particular problem
`
`will not be led only to those elements that the prior art explicitly discloses and/or
`
`are described as a solution to that particular problem. Rather, I understand that
`
`under the KSR standard, steps suggested by common sense are important and
`
`should be considered. Common sense informs that disclosed elements or solutions
`
`
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`Declaration of Donald Alpert, Ph.D. in Support of
`Petition for Inter Partes Review of
`U.S. Patent No. 7,870,404
`
`may have obvious uses beyond the particular problem or application described in a
`
`reference. Common sense also suggests that if something can be done once it may
`
`be obvious to repeat it multiple times.
`
`36.
`
`I understand that in many cases a POSITA will be able to fit the
`
`teachings of several prior art references together, like pieces of a puzzle. As such,
`
`any need or problem known in the same or related fields that the prior art
`
`considered can provide a reason for combining the teachings of the prior art with
`
`those of another prior art. In other words, the prior art references need not be
`
`directed towards solving the particular problem addressed in the challenged patent.
`
`I also understand that the individual prior art references themselves need not all be
`
`directed towards solving a sing