Trials@uspto.gov
`571-272-7822
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`Paper 12
`Date: September 10, 2020
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`PACT XPP SCHWEIZ AG,
`Patent Owner.
`____________
`
`IPR2020-00532
`Patent 8,471,593 B2
`____________
`
`
`
`Before SALLY C. MEDLEY, KEN B. BARRETT, and
`CHRISTOPHER L. OGDEN, Administrative Patent Judges.
`
`BARRETT, Administrative Patent Judge.
`
`
`
`
`DECISION
`Denying Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`571-272-7822
`
`
`
`
`
`
`
`Paper 12
`Date: September 10, 2020
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`PACT XPP SCHWEIZ AG,
`Patent Owner.
`____________
`
`IPR2020-00532
`Patent 8,471,593 B2
`____________
`
`
`
`Before SALLY C. MEDLEY, KEN B. BARRETT, and
`CHRISTOPHER L. OGDEN, Administrative Patent Judges.
`
`BARRETT, Administrative Patent Judge.
`
`
`
`
`DECISION
`Denying Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`IPR2020-00532
`Patent 8,471,593 B2
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`
`I.
`
`INTRODUCTION
`Background and Summary
`A.
`Intel Corporation (“Petitioner”)1 filed a Petition requesting inter
`
`partes review of U.S. Patent No. 8,471,593 B2 (“the ’593 patent,”
`Ex. 1003). Paper 2 (“Pet.”). The Petition challenges the patentability of
`claims 1, 2, 4–11, 14–17, and 19–27 of the ’593 patent. PACT XPP
`Schweiz AG (“Patent Owner”)2 filed a Preliminary Response to the Petition.
`Paper 6 (“Prelim. Resp.”). As authorized by the Board, Petitioner filed a
`Reply to the Preliminary Response (Paper 9, “Pet. Reply”) and Patent Owner
`filed a Sur-Reply (Paper 10, “PO Sur-Reply”).
`
`An inter partes review may not be instituted “unless . . . the
`information presented in the petition . . . shows that there is a reasonable
`likelihood that the petitioner would prevail with respect to at least 1 of the
`claims challenged in the petition.” 35 U.S.C. § 314(a) (2018). Having
`considered the arguments and evidence presented by Petitioner and Patent
`Owner, we determine that Petitioner has not demonstrated a reasonable
`likelihood of prevailing on at least one of the challenged claims of the ’593
`patent. Accordingly, we do not institute an inter partes review of the
`challenged claims.
`
`Related Proceedings
`B.
`One or both parties identify, as matters involving or related to
`
`the ’593 patent: PACT XPP Schweiz AG v. Intel Corp., No. 19-cv-00267 (D.
`Del. Feb. 7, 2019); PACT XPP Schweiz AG v. Intel Corp., No. 19-cv-00273
`
`
`1 Petitioner identifies Intel Corporation as the real party-in-interest. Pet. 1.
`2 Patent Owner identifies PACT XPP Schweiz AG (formerly known as
`Scientia Sol Mentis AG) as the real party-in-interest. Paper 3, 1.
`2
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`IPR2020-00532
`Patent 8,471,593 B2
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`(W.D. Tex. April 23, 2019); Intel Corp. v. PACT XPP Schweiz AG, No. 19-
`cv-02241 (N.D. Cal. April 25, 2019); and PACT XPP Schweiz AG v. Intel
`Corp., No. 1:19-cv-010063 (D. Del. May 30, 2019). Pet. 2; Paper 3, 1–2.
`
`The ’593 Patent
`C.
`The ’593 patent pertains to logic cell arrays. Ex. 1003, 1:18.
`
`According to the patent, “[o]ne of the difficulties with conventional systems
`is that a large number of cells have to communicate with each other . . .
`[and t]he communication may be required in order to pass the data to be
`processed from one cell to another.” Id. at 1:51–55. Also, certain
`conventional bus systems “become[] problematic when a great many
`communicating units need access to the bus or busses.” Id. at 1:66–2:6. The
`patent describes a “bus system [that] includes different segment lines having
`shorter and longer segments for connecting two points in order to be able to
`minimize the number of bus elements traversed between separate
`communication start and end points.” Id. at 2:38–44. The ’593 patent
`explains that, by configuring the bus using long segments “that are fashioned
`as a single line for bypassing long paths in a logic cell array, an especially
`simple design and an especially efficient operation result . . . [and b]y
`simultaneously providing short segment lines, it is ensured that all points are
`addressable as needed.” Id. at 2:45–50.
`
`The Challenged Claim
`D.
`Of the challenged claims of the ’593 patent, claims 1 and 16 are
`
`independent claims. The remaining challenged claims depend directly or
`
`
`3 Patent Owner identified the case as “19-1066.” Paper 3, 2 (underlining
`added). We understand that to contain a typographical error.
`3
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`Patent 8,471,593 B2
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`indirectly from claim 1 or claim 16. Claim 1, reproduced below with
`emphasis added, is illustrative.
`1.
`A data processor on a chip comprising:
`a plurality of data processing cores, each of at least some of the
`processing cores including:
`at least one arithmetic logic unit that supports at least
`division and multiplication of at least 32-bit wide
`data; and
`at least 3 registers for storing at least 32-bit wide data;
`a plurality of memory units to buffer at least 32-bit wide data;
`at least one interface unit for providing at least one
`communication channel between the data processor and
`external memory; and
`a bus system flexibly interconnecting the plurality of processing
`cores, the plurality of memory units, and the at least one
`interface;
`wherein:
`the bus system includes a first structure dedicated for
`data transfer in a first direction and a second
`structure dedicated for data transfer in a second
`direction; and
`each of at least some of the data processing cores
`includes a physically dedicated connection to at
`least one physically assigned one of the plurality of
`memory units, the assigned one of the plurality of
`memory units being accessible by another of the
`data processing cores via a secondary bus path of
`the bus system.
`Ex. 1003, 12:19–44 (emphasis added).
`
`
`
`Evidence
`E.
`Petitioner relies on the following references:
`Reference
`
`US 5,197,140; filed Nov. 17, 1989; issued Mar. 23, 1993
`(“Balmer”)
`
`Exhibit No.
`
`1005
`
`4
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`Reference
`
`Exhibit No.
`
`EP 0 071 727 A1; filed June 23, 1982; published Feb. 16,
`1983 (“Budzinski”)
`US 6,240,458 B1; filed Dec. 22, 1998; issued May 29, 2001
`(“Gilbertson”)
`John L. Hennessy & David A. Patterson, COMPUTER
`ORGANIZATION AND DESIGN: THE HARDWARE/SOFTWARE
`INTERFACE (2d. ed. 1998) (“Hennessy”)
`
`1006
`
`1007
`
`1012
`
`Petitioner also relies on the Declaration of Dr. Pinaki Mazumder
`
`(Ex. 1001) in support of its arguments. The parties rely on other exhibits as
`discussed below.
`
`Asserted Grounds of Unpatentability
`F.
`Petitioner asserts that the challenged claims are unpatentable on the
`
`following grounds:
`Claim(s) Challenged
`1, 2, 4–11, 14–17, 19–27
`1, 2, 4–11, 14–17, 19–27
`1, 2, 4–11, 14–17, 19–27
`
`Reference(s)/Basis
`Balmer, Hennessy
`Budzinski, Hennessy
`Budzinski, Hennessy,
`Gilbertson
`
`35 U.S.C. §
`103(a)
`103(a)
`103(a)
`
`II. ANALYSIS
`A. Principles of Law
`Petitioner bears the burden of persuasion to prove unpatentability of
`
`the claims challenged in the Petition, and that burden never shifts to Patent
`Owner. Dynamic Drinkware, LLC v. Nat’l Graphics, Inc., 800 F.3d 1375,
`1378 (Fed. Cir. 2015).
`
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and the prior art are such that
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`the subject matter, as a whole, would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of skill in the art; and (4) any objective evidence of obviousness
`or non-obviousness.4 Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`
`B. The Level of Ordinary Skill in the Art
`In determining the level of ordinary skill in the art, various factors
`
`may be considered, including the “type of problems encountered in the art;
`prior art solutions to those problems; rapidity with which innovations are
`made; sophistication of the technology; and educational level of active
`workers in the field.” In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995)
`(internal quotation marks and citation omitted).
`
`Petitioner, relying on its declarant’s testimony, asserts: “A [person of
`ordinary skill in the art] at the time of the alleged invention would have had
`at least [an] M.S. in electrical engineering or computer engineering (or
`equivalent experience), and at least three years of experience with processor
`design and memory architecture.” Pet. 10 (citing Ex. 1001 ¶ 75). Patent
`Owner, at this stage, does not disagree or propose a different definition of
`the person of ordinary skill in the art.
`
`We determine that the definition offered by Petitioner comports with
`the qualifications a person would have needed to understand and implement
`
`4 The parties have not directed our attention to any objective evidence of
`obviousness or non-obviousness.
`
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`the teachings of the ’593 patent and the prior art of record. Cf. Okajima v.
`Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001) (the prior art itself may
`reflect an appropriate level of skill in the art). For purposes of this decision,
`we apply Petitioner’s description of the person of ordinary skill in the art.
`
`Claim Construction
`C.
`In an inter partes review requested in a petition filed on or after
`
`November 13, 2018, we apply the same claim construction standard used in
`district courts, namely that articulated in Phillips v. AWH Corp., 415 F.3d
`1303 (Fed. Cir. 2005) (en banc). See 37 C.F.R. § 42.100(b) (2019). In
`applying that standard, claim terms generally are given their ordinary and
`customary meaning as would have been understood by a person of ordinary
`skill in the art at the time of the invention and in the context of the entire
`patent disclosure. Phillips, 415 F.3d at 1312–13. “In determining the
`meaning of the disputed claim limitation, we look principally to the intrinsic
`evidence of record, examining the claim language itself, the written
`description, and the prosecution history, if in evidence.” DePuy Spine, Inc.
`v. Medtronic Sofamor Danek, Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006)
`(citing Phillips, 415 F.3d at 1312–17).
`A Structure Dedicated for Data Transfer in a Specified Direction
`Both of the challenged independent claims call for a bus system
`
`having structures “dedicated” for directional data transfer. Specifically,
`independent claim 1 recites: “the bus system includes a first structure
`dedicated for data transfer in a first direction and a second structure
`dedicated for data transfer in a second direction.” Ex. 1003, 12:35–37.
`Independent claim 16 contains the same recitation. Id. at 13:42–44. Patent
`Owner argues that Petitioner has failed to show how the cited prior art
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`discloses or teaches these structures and places before us the issue of the
`proper construction of the disputed bus system limitations. See Prelim.
`Resp. 13–17.
`
`Patent Owner argues that the claim term “dedicated” takes on its
`ordinary and customary meaning, asserting that “dedicated” means
`“assigned exclusively.” Prelim. Resp. 13–14 (citing Exs. 2013, 2014
`(technical dictionaries)). Thus, Patent Owner contends that “a first structure
`dedicated for data transfer in a first direction” should be construed to mean
`“a first structure assigned exclusively for data transfer in a first direction.”
`Id. at 13. Patent Owner similarly contends that “‘a second structure
`dedicated for data transfer in a second direction’ should be construed to
`mean ‘a second structure assigned exclusively for data transfer in a second
`direction.’” Id. at 13–14. Patent Owner further contends that its proposed
`construction is consistent with the written description of the ’593 patent. Id.
`at 14–16.
`
`Petitioner offers, in the Petition, no explicit construction for the term
`“dedicated.” See Pet. 5 (asserting that no claim term needs construction).
`After Patent Owner’s Preliminary Response placed at issue the meaning of
`that term, Petitioner requested, and we authorized, additional briefing to
`address Patent Owner’s proposed claim construction. Ex. 3001. In that
`authorized additional claim construction briefing, Petitioner acknowledges
`that the term is in dispute, yet argues that it needs no construction. Pet.
`Reply 7–8 (discussion under the heading “The Terms Require No
`Construction”). Although it bears the ultimate burden in the case,
`Petitioner—rather than offering an explicit construction and explaining why
`it is correct—focuses its arguments on why Patent Owner’s construction
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`purportedly is incorrect. Id. at 7–11. In so doing, Petitioner misstates Patent
`Owner’s position as requiring both exclusivity and permanence. Id. at 8–9.
`Patent Owner reiterates or clarifies its position in its Sur-Reply, stating: “In
`particular, nothing in [Patent Owner] PACT’s plain and ordinary meaning
`construction requires ‘permanent implementations’ or ‘permanence’—only
`that the structure be exclusively allocated for transfer in a given direction.”
`PO Sur-Reply 6.
`
`Notwithstanding its assertion that the subject claim term should not be
`construed, Petitioner argues that it “applies the plain and ordinary meaning
`of the term[]”—without articulating that plain and ordinary meaning—and
`further argues that “a person of ordinary skill reading the intrinsic record
`would understand that the claimed bus systems may have ‘dedicated’
`direction in a variety of ways, including by configuring the ‘connecting
`switches’ disclosed in the specification.” Pet. Reply 8. We understand
`Petitioner to contend that the claimed structure dedicated for directional data
`transfer encompasses a switch that has the ability to change the direction of
`data paths. See id. at 8–9; see also, e.g., Pet. 78–79 (mapping, as both a
`structure dedicated for data transfer in a first direction and a structure
`dedicated for data transfer in a second direction, Budzinski’s bidirectional
`switch 178 for path switching and having double-headed arrows indicating
`data flow in two directions). It also appears that Petitioner contends that a
`structure is dedicated for data transfer in one direction if, at any snapshot in
`time, data is flowing in one direction.5 See id. at 30 (arguing that, “for a
`
`
`5 With Patent Owner making clear that its proposed construction does not
`include the concept of permanence, PO Sur-Reply 6, the parties appear to
`both contend that the recited structures only have to be temporarily
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`given data transfer,” writing to memory via one bus is a “first direction” and
`reading from memory via another bus is a “second direction”); id. (referring
`to a processor connected to a particular memory for “one cycle or for a
`period of time”).
`
`Petitioner emphasizes that the claimed invention pertains to a flexible
`bus system and that the written description of the ’593 patent discloses
`certain components, such as switches, that allow a bus system to flexibly
`interconnect certain other components, such as processors and memory
`units. Pet. Reply 7–8 (citing Ex. 1003, 3:30–35, 3:50–64, claims 1 and 16).
`Petitioner argues that Patent Owner’s purported position regarding
`“exclusive or physically permanent implementations” is inconsistent with
`the intrinsic evidence. Id. at 8–9. To the extent that Petitioner contends that
`the only construction of “dedicated” that is consistent with the intrinsic
`evidence is one that would encompass a flexibly interconnecting structure,
`we disagree.
`
`We first turn to the language of the claims and discuss here
`independent claim 1. The pertinent language of independent claim 16 is the
`same or substantively similar to that of independent claim 1.
`
`Claim 1 does, as Petitioner emphasizes, require a flexible bus system,
`reciting “a bus system flexibly interconnecting the plurality of processing
`cores, the plurality of memory units, and the at least one interface.”
`Ex. 1003, 12:31–33; see Pet. Reply 7 (Petitioner arguing, with our emphasis
`added, that “[t]he disputed claim terms relate to “a ‘bus system’ that must
`
`
`“dedicated,” leaving open the issue as to where the duration of dedication
`lies on the spectrum from fleeting to something less than permanent. For the
`reasons discussed below, we do not need to reach that issue.
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`‘flexibly interconnect[]’ various components.”). However, the claim does
`not stop there, and goes on to add a limitation to that bus system via a
`“wherein” clause. The claim further limits the flexible bus system by
`requiring first and second structures dedicated for data transfer in a
`respective direction. Ex. 1003, 12:35–37. The concept of a “dedicated”
`structure implies some amount of rigidity and is in contrast to the concept of
`an otherwise flexible bus system. To the extent that Petitioner argues that
`“dedicated” should be equated with flexible, we are not persuaded, as that
`effectively would read out explicit limitations in the claim.
`
`Petitioner also points to a separate limitation under the “wherein”
`clause that calls for some data processing cores to include a “physically
`dedicated connection” between the data processing core and an assigned
`memory unit. Pet. Reply 9 (citing Ex. 1003, 12:38–41 (“wherein . . . each of
`at least some of the data processing cores includes a physically dedicated
`connection to at least one physically assigned one of the plurality of memory
`units”). Petitioner, arguing that Patent Owner’s proposed construction is not
`correct, contends that the unadorned term “dedicated” in the disputed
`limitation cannot be limited to the narrow concepts of exclusivity and
`permanence because the use of the phrase “physically dedicated” in the same
`claim indicates that the drafter understood how to claim those requirements.
`Id. Thus, according to Petitioner, the disputed “dedicated” term must have a
`broader scope than that of the narrower “physically dedicated” phrase, again
`implying that “dedicated” means flexible, i.e., neither exclusive nor
`permanent. Id. We do not find Petitioner’s arguments to be persuasive.
`First, Petitioner’s argument is rooted in a mischaracterization of Patent
`Owner’s proposed construction, which, as mentioned above, does not
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`require permanence. See PO Sur-Reply 6. Second, Petitioner does not
`explain adequately how rejecting its apparent argument that “dedicated”
`means flexible renders coterminous the two phrases—“the bus system
`includes a [specified] structure dedicated for data transfer in a [specified]
`direction” and “some of the data processing cores includes a physically
`dedicated connection to at least one physically assigned one of the plurality
`of memory units.” The two claim phrases are addressing different
`concepts—a physically dedicated connection (without regard to data flow
`direction), analogous to a particular data conduit, and a structure dedicated
`for directional data flow via a data conduit. See also PO Sur-Reply 6 (Patent
`Owner arguing that “dedicated” in both claim phrases means exclusively
`allocated); see also Ex. 1003, 12:45–47 (dependent claim 2 further limiting
`the secondary bus path to have “dedicated structures for each of two
`directions of data transfer”).
`
`We next turn to the written description of the ’593 patent. Both
`parties rely on portions of the same disclosure in column 5 of the
`Specification. Pet. Reply 9–10 (citing, inter alia, Ex. 1003, 5:19–37); PO
`Sur-Reply 3–4 (citing, inter alia, Ex. 1003, 5:30–35). Petitioner argues that
`Patent Owner’s proposed construction, which excludes a connecting switch
`from the scope of “dedicated,” “is inconsistent with the specification and
`excludes embodiments of the patent.” Pet. Reply 9. Patent Owner argues
`that the Specification does not, as Petitioner argues, identify a switch as a
`structure to define directional data transfer. PO Sur-Reply 3–4.
`
`The Specification, in column 5, explains how interline elements, and
`specifically switches, may be used to configure the bus system through
`segment changes. Ex. 1003, 5:14–29; cf. id. at 3:45–67 (explaining that
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`interline elements include connecting switches, which may be opened or
`closed to configure the bus structure). In other words, switches are used to
`create a flexible bus system. Column 5 then continues by describing “an
`additional aspect of the present invention.” Id. at 5:30–31.
`
`In an additional aspect of the present invention, two-way
`communication of the cells is possible for the logic cell array.
`In bus systems having interline elements, such as drivers and/or
`registers, directions of travel are defined. In order to enable the
`communication of the cells in two directions, separate bus
`systems are provided for opposite running directions. At least
`in one direction, it is once again possible to provide at least two
`different segment lines with shorter and longer segments, in
`particular ones that are once again generally parallel.
`Id. at 5:30–39 (emphasis added).
`
`Petitioner argues that “[t]hese ‘interline elements,’ which include
`connecting switches, drivers, or registers, allow for the bus system’s
`‘direction[] of travel’ to be dedicated as claimed.” Pet. Reply 10 (quoting
`Ex. 1003, 5:30–33) (alterations in original). Petitioner’s logic is flawed.
`The relied upon portion of the Specification identifies only “drivers and/or
`registers” as examples of interline elements that are structures used to define
`directions of travel. Ex. 1003, 5:32–33. The Specification’s omission of a
`connecting switch in this context does not help Petitioner’s case.
`
`Patent Owner argues that Figure 9 of the ’593 patent depicts an
`embodiment where registers are structures for directional data transfer.
`Prelim. Resp. 14–15. The relied upon portion of Figure 9 is reproduced
`below.
`
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`Ex. 1003, Fig. 9. Figure 9 “shows additional processor details, in particular
`of the busses according to an example embodiment,” Id. at 9:22–24, and the
`excerpt above is captioned “Connecting Elements between Clusters.” Patent
`Owner contends that “Figure 9 shows a first structure (e.g., FReg)
`exclusively dedicated for data transfer in a first direction and a second
`structure (e.g., BReg) exclusively dedicated for data transfer in a second
`direction.” Prelim. Resp. 15.
`
`Petitioner argues that the connecting elements depicted in Figure 9
`cannot be the claimed structures included in a bus system because they
`merely connect to, but are not part of, the bus system. Pet. Reply 10–11.; id.
`at 11 (arguing that the connecting element is “using the identified registers
`to interface to the bus system rather than be part of the bus system.” (citing
`Ex. 1003, 6:47–7:30)). Patent Owner responds by arguing that the
`Specification expressly identifies registers as part of the bus system. PO
`Sur-Reply 7–8 (citing Ex. 1003, 8:59–60 (“Fig. 3 shows an example for a
`forward register of a configuration bus according to the present invention.”),
`5:30–35 (“[i]n bus systems having interline elements, such as drivers and/or
`registers, directions of travel are defined.”), 5:40–45 (“the register may be
`provided in the bus system”)). After asserting that the registers with
`directional arrows shown in Patent Owner’s excerpt of Figure 9 are not part
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`of the bus system, Petitioner argues that the depiction of bus lines and
`switches in that same excerpt “confirms the ‘bus system’ configures
`non-exclusive ‘switches’ to dedicate the direction of travel.” Pet. Reply 11
`(citing Ex. 1003, 3:45–55). Petitioner’s arguments are based on an
`underdeveloped, and therefore unpersuasive, narrow construction of “bus
`system” coupled with the circular assertion that Figure 9 only shows
`switches as elements in the bus system that are used for dedicated directional
`data transfer. See id. Regardless as to whether Patent Owner’s
`characterization of Figure 9 is correct, we do not find that figure to support
`Petitioner’s argument that switches correspond to the directionally dedicated
`structure of the disputed limitation. Further, even if Patent Owner’s
`characterization is incorrect, that does not mean that Petitioner—the party
`bearing the burden—is correct.
`
`Lastly, we consider Patent Owner’s dictionary evidence. Patent
`Owner argues that various dictionaries confirm that the plain meaning of
`“dedicated” is “assigned exclusively.” PO Sur-Reply 5 (citing Exs. 2013,
`2014, 2025).
`
`Although dictionaries typically are regarded as extrinsic evidence,
`citation to at least one pertinent dictionary appears in the ’593 patent itself
`and in the prosecution history file. See Ex. 1003, p.11 (code (56),
`continuation page of the references cited section; “Webster’s Ninth New
`Collegiate Dictionary, Merriam-Webster, Inc., 1990, p. 332 (definition of
`‘dedicated’)”); Ex. 1004, 70 (Information Disclosure Statement listing the
`same as a reference cited by the applicants). Whether properly considered
`intrinsic or extrinsic evidence, we find Patent Owner’s dictionaries
`informative as to the plain and ordinary meaning of “dedicated.”
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`The general dictionary cited in the ’593 patent defines the verb
`
`“dedicate” as “to set apart to a definite use” and the adjective “dedicated” as
`“devoted to a cause, ideal or purpose” and “given over to a particular
`purpose.” Ex. 2025 (Webster’s Ninth New Collegiate Dictionary). A
`technical dictionary, The Illustrated Dictionary of Electronics, defines
`“dedicated” as “[a]ssigned exclusively to a certain purpose [e.g., a dedicated
`facsimile (fax) line].” Ex. 2013, 6 (brackets in original). Another technical
`dictionary, the Modern Dictionary of Electronics, defines “dedicated” as
`“[t]o set apart for some special use” and “[a] piece of equipment that is
`assigned to one particular use only.” Ex. 2014, 6.
`
`These dictionaries further demonstrate the flaw in Petitioner’s
`argument that “assigned exclusively” is not a plain and ordinary meaning of
`“dedicated.” This flaw is highlighted by Petitioner’s failure to explicitly and
`clearly identify what it contends is the “plain and ordinary meaning” of the
`term. See Pet. Reply 8.
`
`In conclusion, Petitioner’s argument that “a first structure dedicated
`for data transfer in a first direction and a second structure dedicated for data
`transfer in a second direction,” as recited in the challenged independent
`claims, encompass a connecting switch is not a correct construction. We
`also determine that, on this record and for purposes of this decision, the
`disputed claim limitations do not require express construction because, as
`discussed further below, Petitioner’s articulated challenges are premised on
`its incorrect implied construction.
`
`D.
`
`The Alleged Obviousness of the Challenged Claims over Balmer and
`Hennessy
`Petitioner alleges that claims 1, 2, 4–11, 14–17, and 19–27 of the ’593
`
`patent would have been obvious over Balmer and Hennessy. See Pet. 16–60.
`
`16
`
`
`
`IPR2020-00532
`Patent 8,471,593 B2
`
`Patent Owner argues that Petitioner has failed to show that the relied on
`prior art, and specifically Balmer, discloses or teaches the claimed first and
`second structures dedicated for data transfer in the specified direction.
`Prelim. Resp. 19–25.
`1. Balmer (Ex. 1005)
`Balmer discloses a multi-processor system arranged as an image and
`
`graphics processor. Ex. 1005, code (57). “The processor is structured with
`several individual processors all having communication links to several
`memories [and a] crossbar switch serves to establish the processor memory
`links.” Id. “The entire image processor, including the individual processors,
`the crossbar switch and the memories, is contained on a single silicon chip.”
`Id. Figure 1 of Balmer is reproduced below.
`
`
`Figure 1 “show[s] an overall view of the elements of the image processing
`system.” Id. at 3:24–25. The image processing system includes “a set of
`parallel processors 100-103 and a master processor 12 connected to a series
`of memories 10 via a cycle-rate local connection network switch matrix 20
`called a crossbar switch.” Id. at 4:45–48. “Transfer processor 11
`communicates with external memory 15 via bus 21.” Id. at 5:4–5.
`
`17
`
`
`
`IPR2020-00532
`Patent 8,471,593 B2
`
`
`
`Balmer’s Figure 4 is shown below.
`
`
`Figure 4 “shows a more detailed view of [Figure 1] where the four parallel
`processors 100-103 are shown interconnected by communication bus 40 and
`also shown connected to memory 10 via crossbar switch matrix 20.” Id.
`at 5:62–66. “[E]ach parallel processor 100-103 has a particular global bus
`and a particular local bus to allow the processor access to the various
`memories.” Id. at 6:30–32. “This structure allows data from
`memories 10-0, 10-2, 10-3 and 10-4 to be distributed to any of the
`processors 100-103.” Id. at 6:49–51. “In operation, any processor can
`access any of a number of memories, while certain memories are dedicated
`to handling instructions for the individual processors.” Id. at 3:14–16.
`2. Hennessy (Ex. 1012)
`Hennessy is a book titled Computer Organization and Design: The
`
`Hardware/Software Interface. Hennessy discusses processor architecture
`and bus systems that interconnect processors with other processors, memory,
`and I/O.
`
`18
`
`
`
`IPR2020-00532
`Patent 8,471,593 B2
`
`
`3. Discussion
`As mentioned, the independent claims limit the bus system by
`
`requiring “a first structure dedicated for data transfer in a first direction and
`a second structure dedicated for data transfer in a second direction.”
`Ex. 1003, 12:35–37 (independent claim 1), 13:42–44 (independent
`claim 16).
`
`Petitioner contends that Balmer discloses these limitations, arguing:
`Balmer’s crossbar includes structures (crosspoints and
`global/local bus interfaces) that can be configured to allow, for
`example, writing from one processor to a memory unit over a
`“local bus” (data transfer in a first direction) and reading from
`the memory unit to another processor over the “global bus”
`(data transfer in a second direction). Ex. 1001, ¶103-105. Thus,
`for a given data transfer, crosspoints within the crossbar are set
`to allow dedicated transfer in the first direction (e.g., a write to
`memory over the “local bus”), and different crosspoints within
`the crossbar are set to allow dedicated transfer in the second
`direction (e.g., a read from memory over the “global bus”).
`Pet. 29–30. Petitioner further argues that “Balmer’s crossbar uses ‘a
`plurality of links to be individually operated at crosspoints thereof to effect
`the different arrangements desired’” and that “Balmer’s crossbar can
`‘interconnect various processors together to work from a single instruction
`for a period of time or to work independently so that data which is stored in
`a first memory can remain in that memory while a different processor is for,
`one cycle or for a period of time, connected to that same memory.’” Id.
`at 30 (quoting Ex. 1005, 5:62–66, 7:15–26, 9:11–20).
`
`Thus, Petitioner’s contention is that switches in the crossbar create a
`flexibly interconnected bus system. That, however, is more properly
`addressing the limitation immediately preceding the “wherein” clause that
`introduces the “dedicated” limitations. See Ex. 1003, 12:31–34 (“a bus
`
`19
`
`
`
`IPR2020-00532
`Patent 8,471,593 B2
`
`system flexibly interconnecting the plurality of processing cores, the
`plurality of memory units, and the at least one interface.”); Pet. 29
`(addressing that “flexibly interconnecting” limitation in arguing, “[a]lso
`referred to as a ‘switch matrix,’ the crossbar uses ‘a plurality of links to be
`individually operated at crosspoints thereof to effect the different
`arrangements desired.’”). Petitioner’s applied construction reads out the
`requirements of first and second structures each dedicated for data transfer in
`the respective direction. For the reasons discussed above, Petitioner’s
`construction of these “dedicated” limitations as broad enough to cover
`switches is not correct.
`
`Although Petitio
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