`
`PACT XPP SCHWEIZ AG
`
`
`
`
`
`INTEL CORPORATION,
`
`
`
`Plaintiff,
`
`
`
`v.
`
`
`
`Defendant.
`
`
`
`
`
`
`
`
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
`
`
`
`
`C.A. No. 19-1006-JDW
`
`
`
`)
`)
`)
`)
`)
`)
`)
`)
`)
`
`JOINT CLAIM CONSTRUCTION CHART
`
`Pursuant to Paragraph 9 of the Scheduling Order (D.I. No. 20), Plaintiff PACT XPP Schweiz AG (“PACT”) and Intel Corporation
`
`(“Intel”) hereby submit this Joint Claim Construction Chart, identifying for the Court the terms and phrases of the claims in issue,
`
`including each party’s proposed construction of the disputed claim language with citations only to the intrinsic evidence in support of
`
`their respective proposed constructions.
`
`
`
`
`
`1
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`INTEL - 1009
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`
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`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 2 of 19 PagelD #: 2086
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`TABLE OF EXHIBITS
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`
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`1 2 3
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`4 5 6 7 8 9 1
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`0
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`11
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`12
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`13
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`14
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`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`24
`
`25
`
`26
`
`27
`
` ——
`
`US. Patent No. 8,312,301
`
`Plaintiff
`
`
`
`Excelpts of File History of US Patent No. 9,552,047 relied on by
`Plaintiff
`
`Intentional] Lefi Blank
`Intentional] Left Blank
`_—
`Intentional] Left Blank
`_—
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`INTEL - 1009
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`
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`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 3 of 19 PagelD #: 2087
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`28
`
`29
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`30
`
`31
`
`32
`
`33
`
`34
`
`35
`
`36
`
`37
`
`Document
`
`Intentional] Left Blank
`
`Intentional] Left Blank
`
`Excerpts of File History of US. Patent No. 8,819,505 relied on by
`Defendant
`
`Intentional] Lefi Blank
`
`Excerpts of File History of US. Patent No. 9,075,605 relied on by
`Defendant
`
`Excerpts of File History of US. Patent No. 9,170,812 relied on by
`Ddhmmn
`
`Intentional] Left Blank
`
`Excerpts of File History of US. Patent No. 9,436,631 relied on by
`Ddhmmn
`
`Excerpts of File History of US. Patent No. 9,552,047 relied on by
`Defendant
`
`DE 196 54 846 A]
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`INTEL - 1009
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`
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`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 4 of 19 PagelD #: 2088
`
`STIPULATED CLAINI TERMS
`
`Patent
`
`Claim Terms and Phrases
`
`Sti n ulated Claim Construction
`
`29, 32, 44, and 73-74
`
`’605
`
`’908
`
`’631
`
`,807
`
`Preamble claim 1
`
`Preamble is limitin .
`
`“train mission” claim 4
`
`“ma executed” claiml
`
`transmission
`
`ma be executed
`
`Preambles claims 2, 10, 14, 15
`Preambles (claims 1-6, 24, 26-27,
`
`Preambles are not limitin- .
`Preambles are not limiting.
`
`.
`Claim Terms
`d Ph
`
`rases
`
`TERMS PROPOSED BY PLAINTIFF
`
`Plaintifi’s
`
`Defendant’s
`
`Proposed
`Construction
`
`Proposed
`Construction
`
`Plaintiff’s Intrinsic
`.
`Evrdence
`
`Defendant’s Intrinsic Evidence
`
`“interconnecting connect at
`at runtime at
`least one data
`least one of data
`processing
`processing cells
`cell, at least
`and memory
`one memory
`cells with at
`cell, and at
`least one of
`least one
`memory cells
`interface unit
`and one or more with each
`
`of the at least
`
`one interface
`
`other at
`
`runtime.
`
`Ex. 1, Figs. 1, 2(a)—2(c), 3, See e.g., Ex. 1 (’763 patent) at 2: 16-23;
`See Intel’s
`construction for 4, 5
`12:5—17; 4:4-10; 12:38-83; 9:3-9:6;
`“programmably 7:47-11:12; 11:21-45.
`6:56-7:6; 1:26-28; 8:45-55.
`interconnecting
`at runtime” /
`“dynamically
`interconnecting
`at runtime”
`
`Patent
`
`an
`
`unit” (claims 1,
`
`INTEL - 1009
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`
`
`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 5 of 19 PagelD #: 2089
`
`Plaintiff’s Intrinsic
`.
`Evrdence
`
`Defendant’s Intrinsic Evidence
`
`Ex. 1, Figs. 1, 2(a)-2(c), 3, See e.g., Ex. 1 (’763 patent) at 2:16-23;
`See Intel’s
`each of the
`construction for 4, 5
`12:5-17; 4:4-10; 12:38-83; 9:3-9:6;
`data
`“the data
`“programmably 7:47-11:12; 11:21-45.
`6:56-7:6; 1:26-28; 8:45-55.
`processing
`processing cells
`interconnecting
`cells is
`are adapted to
`at nmtime” /
`adapted to
`connect
`simultaneously “dynamically
`simultaneously
`connect to a
`interconnecting
`to a plurality of
`plurality of
`at nmtime”
`at least one of
`elements; each
`cells and units
`of at least one of of the
`
`
`
`Patent
`
`.
`Claim Terms
`and Phrases
`
`Plaintiff’s
`
`Defendant’s
`
`Proposed
`Construction
`
`Proposed
`Construction
`
`the memory
`cells, the data
`processing cells,
`and the at least
`one interface
`
`units” (claim
`10)
`
`elements is
`either one of
`the memory
`cells, another
`one of the data
`
`processing
`cells, or the
`interface unit.
`
`INTEL - 1009
`
`
`
`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 6 of 19 PagelD #: 2090
`
`Patent
`
`.
`Claim Terms
`and Phrases
`
`Plaintiff’s
`
`Defendant’s
`
`Proposed
`Construction
`
`Proposed
`Construction
`
`Plaintiff’s Intrinsic
`.
`Evrdence
`
`Defendant’s Intrinsic Evidence
`
`units” (claim
`
`Ex. 1, Figs. 1, 2(a)-2(c), 3, See e.g., Ex. 1 (’763 patent) at 2:16-23;
`See Intel’s
`the data
`“cells of the
`construction for 4, 5
`12:5-17; 4:4-10; 12:38-83; 9:3-9z6;
`processing
`data processing
`“programmably 7:47-11:12; 11:21-45.
`6:56-7:6; 1:26-28; 8:45-55.
`cells are adapted cells are
`interconnecting
`to connect
`adapted to
`simultaneously
`simultaneously at nmtime” /
`to other cells of
`connect each
`“dynamically
`the data
`other and to a
`interconnecting
`processing cells
`plurality of
`at nmtime”
`and to a
`elements; each
`
`plurality of at
`least one of
`
`of the
`elements is
`
`cells and units
`
`either one of
`
`of at least one of
`the memory
`cells, the data
`
`the memory
`cells, another
`one of the data
`
`processing cells, processing
`and the at least
`cells, or the
`one interface
`interface unit.
`
`INTEL - 1009
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`
`
`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 7 of 19 PagelD #: 2091
`
`Patent
`
`.
`Claim Terms
`and Phrases
`
`Plaintiff’s
`
`Defendant’s
`
`Proposed
`Construction
`
`Proposed
`Construction
`
`the memory
`cells, others of
`the data
`
`processing cells,
`and the at least
`one interface
`units” (claim
`
`either one of
`the memory
`cells, another
`
`one of the data
`processing
`cells, or the
`
`Plaintiff’s Intrinsic
`.
`EVIdence
`
`Defendant’s Intrinsic Evidence
`
`Ex. 1, Figs. 1, 2(a)-2(c), 3, See e.g., Ex. 1 (’763 patent) at 2:16-23;
`simultaneously See Intel’s
`“interconnect a
`interconnect a
`construction for 4, 5
`12:5-17; 4:4-10; 12:38-83; 9:3-9z6;
`data processing
`data
`“programmably 7:47-11:12; 11:21-45.
`6:56-7:6; 1:26—28; 8:45-55;
`cell
`processing cell
`interconnecting
`simultaneously
`to a plurality
`at nmtime” /
`to a plurality of
`of elements;
`“dynamically
`at least one of
`each of the
`interconnecting
`cells and units
`of at least one of elements is
`at nmtime”
`
`interface unit.
`
`INTEL - 1009
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`
`
`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 8 of 19 PagelD #: 2092
`
`Patent
`
`.
`Claim Terms
`and Phrases
`
`Plaintiff’s
`
`Defendant’s
`
`Proposed
`Construction
`
`Proposed
`Construction
`
`Plaintiff’s Intrinsic
`.
`EVIdence
`
`Defendant’s Intrinsic Evidence
`
`the memory
`cells and the
`
`interface units”
`(claim 13)
`
`elements is
`either one of
`
`the memory
`cells or the
`interface unit.
`
`Ex. 1, Figs. 1, 2(a)-2(c), 3, See e.g., Ex. 1 (’763 patent) at 2:16-23;
`simultaneously See Intel’s
`interconnect
`construction for 4, 5
`1225-17; 4:4-10; 12:38-83; 9:3-9:6;
`each one of a
`“programmably 7:47-1 1 : 12; 11:21-45.
`6:56-7:6; 1:26-28; 8:45-55.
`“interconnect a
`plurality of
`interconnecting
`plurality of data
`data
`at nmtime” /
`processing cells
`processing
`“dynamically
`simultaneously
`cells to a
`interconnecting
`to a plurality of
`plurality of
`at nmtime”
`at least one of
`elements; each
`cells and units
`of at least one of of the
`
`31)
`
`Preambles
`
`(claims 1 and
`
`Preambles are
`limiting.
`
`Preambles are
`not limiting /
`no construction
`
`Ex. 1, Fig. 1, 2(a)-(c), 3,
`4, 5, 6,
`2:52—59; 5:53-6:21; 7:31-
`
`Preambles are not limiting / no
`construction necessary
`
`necessary
`
`8: 10; 8:26-31; 10:34-11:2;
`1 1:13-20;
`
`Claims 20, 50.
`
`INTEL - 1009
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`
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`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 9 of 19 PagelD #: 2093
`
`.
`Claim Terms
`and Phrases
`
`Plaintiff’s
`
`Defendant’s
`
`Proposed
`Construction
`
`Proposed
`Construction
`
`Plaintiff’s Intrinsic
`.
`EVIdence
`
`Defendant’s Intrinsic Evidence
`
`Preambles are
`limiting.
`
`Ex. 3, Fig. 1;
`1:25-36; 2: 1-19; 4:43-46;
`6:7—61; 8:64-92; 9:3-11;
`9:44-55; 10:23-36; 12:66-
`13:1 1;
`claim 3.
`
`Claims 6, 8, 10, Ex. 24, August 10, 2016
`12: Preambles
`Remarks at 13-16;
`are not limiting
`/ no
`construction
`necessary.
`Claim 3: See
`Intel’s
`construction for
`“data
`processing
`element”
`and/or “data
`processing
`elements
`
`Claims 6, 8, 10, 12: Preambles are not
`limiting / no construction necessary.
`
`Claim 3: “reconfigurable and
`sequential data processors where the
`data results from one processor are fed
`to another, for each processor to
`perform a separate computation” (See
`term “reconfigurable and sequential
`data processors where the data results
`from one processor are fed to another,
`for each processor to perform a
`separate computation”)
`
`Preambles
`(claims 3, 6, 8,
`10, 12)
`
`
`
`Preambles are
`limiting.
`
`Preambles are
`limiting.
`
`Preambles
`(claims 1 and
`16)
`
`Preambles
`(claims 1, 14,
`16-18, 27)
`
`adapted for
`programmably
`processing
`seuences”
`
`Preambles are
`not limiting/
`no construction
`necessary
`
`Preambles are
`not limiting/
`no construction
`necessary
`
`Ex. 4, 2:17—36, 3:34-39,
`6:7-58, 7:41-59, 8:55-58,
`9:22—26, 9:34-10:26, 12:7—
`16;
`Fi s. 1-2, 9
`
`Ex. 6, Figs. 1-19;
`1:20-60; 6:55-67; 7:5-35;
`12:20-13:17.
`
`See e.g., Ex. 4 (’593 patent) at 3:34-44;
`2:18-34.
`
`See, e.g., Ex. 6 (’505 patent) at 2:40-
`42;
`
`See, e.g., Ex. 30 (’505 File History) at
`4863.
`
`INTEL - 1009
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`
`
`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 10 of 19 PagelD #: 2094
`
`Patent
`
`.
`Claim Terms
`and Phrases
`
`Plaintiff’s
`
`Defendant’s
`
`Proposed
`Construction
`
`Proposed
`Construction
`
`Plaintiff’s Intrinsic
`.
`EVIdence
`
`Defendant’s Intrinsic Evidence
`
`Oflice Action (Feb. 3,
`
`passing results
`onto one or
`more other
`data
`processing
`units which
`
`are
`subsequently
`processing
`data
`
`Preamble is
`limiting.
`
`“sequentially
`processing data”
`
`Preamble (claim
`12)
`
`See term “data processing element”
`and/or “data processing elements
`adapted for programmably processing
`sequences”
`
`Ex. 24, August 10, 2016
`See Intel’s
`construction for Remarks at 13-16.
`“data
`processing
`unit” and/or
`“data
`
`Ex. 8, 4:50-53;
`Figs. 1, 2,
`7:66—8: l8, 8:34—59, 9:4-
`
`18, 9:37-44, 11:31-12:3;
`claim 1.
`
`processing
`unit. . .adapted
`for sequentially
`processing
`data”
`
`See, e.g., Ex. 9 (’812 patent) at
`Preamble is not Ex. 9, Abstract, 2:5—14,
`limiting /no
`2:47—3:15, 827-20, 11:17- Abstract, 2:10—14, 2:473:15, 3:47-
`construction
`26, 31:56-32z6, 34:30-38
`4:37, 5:29-7:2, 7:52-8:62, 9:1-10:29.
`
`necessary
`
`44:19-22, 159:20-23;
`Figs. 16, 18, 20, 77, 80.
`
`Ex. 21, Amendment &
`
`Remarks May 18, 2015),
`
`INTEL - 1009
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`
`
`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 11 of 19 PagelD #: 2095
`
`Patent
`
`.
`Claim Terms
`and Phrases
`
`Plaintiff’s
`
`Defendant’s
`
`Proposed
`Construction
`
`Proposed
`Construction
`
`Plaintiff’s Intrinsic
`.
`Evrdence
`
`Defendant’s Intrinsic Evidence
`
`passing results
`onto one or
`more other
`data
`“sequentially
`processing data” processing
`(claims 1-5, 8,
`units which
`10, 15, 19, 22,
`are
`24)
`subsequently
`processing
`data
`
`Ex. 12, 4:54-57.
`
`Ex. 24, August 10, 2016
`See Intel’s
`construction for Remarks at 13-16.
`“data
`processing
`element”
`Ex. 8, 7:66—8:18, 8:34—59,
`and/or “data
`9:37-44 (corresponding
`processing
`unit. . .adaptable disclosures in Ex. 12)
`for sequentially
`processing
`data”
`
`See term “data processing element”
`and/or “data processing elements
`adapted for programmably processing
`sequences”
`
`
`
`Preambles are
`limiting.
`
`Preambles are
`not limiting /
`no construction
`
`necessary
`
`Preambles
`(Clams 1’ 19)
`
`Ex. 12, Fig. l;
`
`Preamble is not limiting / no
`construction necessary
`
`2:24-34; 4:58-67; 8:1-7;
`
`9:20-37; 11:57-2:4;
`Clanns 19, 33.
`Ex. 8, 1:28-48, 2:45-67,
`3:61—4:49, 6:14-67, 8:29—
`9:3, 13:54-1423, Fig. 4, 5
`(corresponding
`disclosures in Ex. 12
`
`INTEL - 1009
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`
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`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 12 of 19 PagelD #: 2096
`
`TERMS PROPOSED BY DEFENDANT
`
`.
`Claim Terms and
`Phrases
`
`Patent
`
`Plaintiff’s
`
`Defendant’s
`
`Proposed
`Construction
`
`Proposed
`Construction
`
`Plaintiffs Intrinsic
`.
`Evndence
`
`Defendant’s Intrinsic Evidence
`
`“data processing
`cells, each adapted
`for sequentially
`
`ixgigtmg (clauns
`
`Plain and
`ordinary
`meaning. N0
`construction
`
`necessary.
`
`sequentially
`
`executin ' ”
`
`10:30; 10:23-30.
`
`“reconfigurable
`processor
`fimction cells
`adapted for
`
`Ex. 1, Figs. 2(a)—2(c),
`
`1:23-44; 2:16-45;
`3:18-33; 4:19-39;
`
`5:17-6:35; 8:61-
`
`See e.g. Ex. 1 (’ 763 patent) at 7:20—28;
`1:23—25; 1:61 -:22; 3: 18-33; 10: 61—
`11:2; 3:58-4:2; 1:23-25; 3:34-51; 7:52-
`60; see e.g., Ex. 37 (DE 196 54 846
`
`A1) at Col. 17.
`
`INTEL - 1009
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`
`
`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 13 of 19 PagelD #: 2097
`
`Plaintiffs
`
`Defendant’s
`
`Plaintiffs Intrinsic
`
`Defendant’s Intrinsic Evidence
`
`Patent Claim Terms and
`Phrases
`
`Proposed
`Construction
`
`Proposed
`Construction
`
`Evidence
`
`“programmably Ex. 1, Figs. 2(a)-2(c);
`1:23-44; 2:16-45;
`reconfiguring
`interconnects at
`
`See e.g., Ex. 1 (’763 patent) at 2:16-23;
`12:5-17; 4:4-10; 12:38-83; 9:3-9z6;
`
`nmtime” /
`
`“dynamically
`reconfiguring
`interconnects at
`
`nmtime”
`
`5:17-6:35; 8:61-10:30 6:56-7:6; 1:26-28; 8:45-55.
`
`“programmably
`interconnecting at
`runtime”/
`
`“dynamically
`interconnecting at
`runtime” (claims
`1, 31)
`
`No construction
`
`necessary for
`“programmably
`” or
`
`“dynamically.”
`Plain and
`
`ordinary
`meaning.
`
`For
`
`“interconnectin
`
`g at runtime,”
`See PACT’s
`
`proposed
`construction of
`
`“interconnectin
`
`g at nmtime at
`least one of data
`
`processing cells
`and memory
`cells with at
`
`least one of
`
`memory cells
`and one or more
`
`of the at least
`
`one interface
`
`unit ”
`
`INTEL - 1009
`
`
`
`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 14 of 19 PagelD #: 2098
`
`Plaintiff
`
`Defendant’s
`
`Plaintiffs Intrinsic
`
`Defendant’s Intrinsic Evidence
`
`Patent Claim Terms and
`Phrases
`
`Proposed
`Construction
`
`Proposed
`Construction
`
`Evidence
`
`“data processing
`element” and/or
`
`“data processing
`elements adapted
`for programmably
`processing
`sequences”
`(claims 3, 6, 8-10,
`12-14, 16-18, 23-
`
`26, 30, 32, 35)
`
`See PACT’s
`
`proposed
`construction of
`
`“sequentially
`processing
`data.”
`
`“data processing
`unit” and/or “data
`
`.
`
`.
`
`processing unit .
`adapted for
`sequentially
`processing data”
`(claim 1)
`
`See e.g., Ex. 36 (’047 File History) at
`551-53;
`
`See, e.g., Ex. 3 (’301 patent) at 4:43-
`46; 2:1-3; 11:23-28; 10:62; 11:49-58;
`
`2:22-24; 1:26-36; 4:66-5:4; 5:21-32;
`8:27-30.
`
`See term “data processing element”
`and/or “data processing elements
`adapted for programmably processing
`sequences”
`
`
`
`Plain and
`
`ordinary
`meaning. No
`construction
`
`necessary.
`
`“reconfigurable
`and sequential
`data processors
`where the data
`
`results from one
`
`Ex. 24, August 10,
`2016 Remarks at 13-
`16.
`
`Ex. 3, 1:25-36; 2:1-
`
`processor are
`
`19; 3:31-40, 7:58-
`
`fed to another,
`for each
`
`processor to
`perform a
`
`separate
`computation”
`
`“reconfigurable
`and sequential
`data processors
`Where the data
`
`results from one
`
`processor are
`
`fed to another,
`for each
`
`processor to
`perform a
`separate
`com | utation”
`
`8:11; 4:43-46, 6:7-61;
`9:44-55;
`claim 3.
`
`Ex. 8, Abstract, 1:28-
`
`48, 2:45-67, 3:61-
`
`4:49, 6:14-67, 8:29-
`
`923, 11231-123,
`
`12:16-34, 13:53-
`
`14:3, Fig. l, 4, 5
`(corresponding
`disclosures in Ex. 3
`
`Ex. 24, August 10,
`2016 Remarks at l3—
`
`16.
`
`Ex. 8, 1:25—38; 2:4-
`23; 4:50-53.
`claim 1.
`
`Ex. 8, Abstract, 2:45-
`
`63,11:31-12:3,
`
`12:16-34, 13:53-59,
`
`Fi. 1, 4
`
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`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 15 of 19 PagelD #: 2099
`
`Plaintiffs
`
`Defendant’s
`
`Plaintiffs Intrinsic
`
`Defendant’s Intrinsic Evidence
`
`Patent Claim Terms and
`Phrases
`
`Proposed
`Construction
`
`Proposed
`Construction
`
`Evidence
`
`Ex. 8, col.3:22-36;
`
`See, e.g., Ex. 32 (’605 File History) at
`
`4:18-33; 4:57-58;
`
`5:28-56; 5:63-6:14;
`
`7:3-20; 7:24-54;
`
`7:55-61; 8:34-59;
`
`1021-19; 11:67—12z3;
`13:8-30.
`
`Ex. 12, claims 16, 30.
`
`378; Ex. 8 at 3:24-30.
`
`Plain and
`
`ordinary
`meaning. No
`construction
`
`necessary.
`
`“to a level no
`
`more than is
`
`required for the
`preservation of
`memory
`contents or the
`
`like”
`
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`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 16 of 19 PagelD #: 2100
`
`Plaintiff
`
`Defendant’s
`
`Plaintiffs Intrinsic
`
`Defendant’s Intrinsic Evidence
`
`Patent Claim Terms and
`Phrases
`
`Proposed
`Construction
`
`Proposed
`Construction
`
`Evidence
`
`Subject to 35
`U.S.C . §1 12,
`sixth paragraph
`Function:
`
`Ex. 9, 13:55-59,
`
`16:44-45, 19:60-20:8,
`
`20:56-58, 25:9-12,
`
`26:37-46, 28:55-29:2,
`
`See e.g., Ex. 33 (’812 File History) at
`Response to Rejection (5/18/15), Non-
`Final Rejection (2/17/15).
`
`See e.g., Ex. 9 (’812 patent) at Fig.
`
`77A-J, 80A-C.
`
`“instruction
`
`dispatch
`unit. . .configured
`to dispatch
`software threads to
`
`the array data
`processor for
`parallel execution
`by the parallel
`processing
`arithmetic units”
`
`(claim 12)
`
`Dispatch
`soflware
`
`threads to the
`
`array data
`processor for
`parallel
`execution by
`the parallel
`processing
`arithmetic units.
`
`Structure: Fig.
`80A,
`
`configuration
`unit (CT).
`
`31:43-55, 32:60-
`
`33:24, 34:29-48,
`
`35:34-37, 36:7-14,
`
`39:26-37, 43:33-35,
`
`44:1-10, 44:42-58,
`
`138:37-139:4,
`
`140:21-27, 140:44-
`
`56, 158:46-49,
`
`159:20-160:38,
`
`162:62-66, 163:11-
`
`22, 164:53-56,
`165:16-21
`
`Figs. 13, 16-18, 20,
`80A-C
`
`Ex. 21, Amendment
`
`& Remarks May 18,
`2015), Office Action
`eb. 3, 2015
`
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`
`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 17 of 19 PagelD #: 2101
`
`Plaintiff
`
`Defendant’s
`
`Plaintiffs Intrinsic
`
`Defendant’s Intrinsic Evidence
`
`Patent Claim Terms and
`Phrases
`
`Proposed
`Construction
`
`Proposed
`Construction
`
`Evidence
`
`Ex. 11,
`Claim 1;
`
`See, e.g., Ex. 11 (’631 patent) at Figs.
`5, 6; 15:25-27, 24:58-61, 26:42-47,
`
`13:52-15:60;
`
`27:22-35;
`
`See, e.g., Ex. 35 (’631 File History) at
`Response After Final, 1/14/16; see also
`Final Rejection, 10/29/15 (Claim
`Rejections - 35 USC 103).
`
`See term “data processing element”
`and/or “data processing elements
`adapted for programmably processing
`
`Fig. 5
`
`25:49-62;
`
`Fig. 6
`26:38-41.
`
`Ex. 24, August 10,
`2016 Remarks at 13—
`16.
`
`’047 Patent, col.4:54-
`57.
`
`Ex. 12, 1:29-39; 2:4-
`23; claims 1-5, 8, 10,
`
`15, 19, 22, 24;
`
`Ex. 8, Abstract, 2:45-
`
`63, 11131-123,
`
`12:16-34, 13:53-59,
`Fig. 1, 4
`(corresponding
`disclosures in Ex. 12
`
`“a plurality of bus
`segments for each
`processor of the
`multiprocessor
`system” (claim 1)
`
`“data processing
`unit” and/or “data
`
`.
`
`.
`
`processing unit .
`adaptable for
`sequentially
`processing data”
`(claims 1-5, 8, 10,
`15, 19, 22, 24)
`
`Plain and
`
`ordinary
`meaning. No
`construction
`
`necessary.
`
`See PACT’s
`
`proposed
`construction of
`
`“sequentially
`processing
`data.”
`
`“a plurality of
`bus segments
`for each
`
`processor of the
`multiprocessor
`system, each
`bus segment
`connected to
`
`only one of the
`. rocessors”
`
`“reconfigurable
`and sequential
`data processors
`where the data
`
`results from one
`
`processor are
`
`fed to another,
`for each
`
`processor to
`perform a
`
`separate
`computation”
`
`sequences”
`
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`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 18 of 19 PageID #: 2102
`
`Dated: January 31, 2020
`
`FARNAN LLP
`
`By: /s/ Brian E. Farnan
`Brian E. Farnan (Bar No. 4089)
`Michael J. Farnan (Bar No. 5165)
`919 North Market Street, 12th Floor
`Wilmington, DE 19801
`Telephone: (302) 777-0300
`Facsimile: (302) 777-0301
`bfarnan@farnanlaw.com
`mfarnan@farnanlaw.com
`
`Danielle L. Gilmore (Pro Hac Vice)
`daniellegilmore@quinnemanuel.com
`Frederick A. Lorig (Pro Hac Vice)
`fredericklorig@quinnemanuel.com
`Pushkal Mishra (Pro Hac Vice)
`pushkalmishra@quinnemanuel.com
`QUINN EMANUEL URQUHART &
`SULLIVAN, LLP
`865 S. Figueroa Street, 10th Floor
`Los Angeles, CA 90017
`Tel : (213) 443-3047
`
`Mark Tung (Pro Hac Vice)
`marktung@quinnemanuel.com
`QUINN EMANUEL URQUHART &
`SULLIVAN, LLP
`555 Twin Dolphin Dr., 5th Floor
`Redwood Shores, CA 94065
`Tel.: (650) 801-5016
`
`Respectfully submitted,
`
`Morris, Nichols, Arsht & Tunnell LLP
`
`By: /s/ Jack B. Blumenfeld__
`Jack B. Blumenfeld (#1014)
`Brian P. Egan (#6227)
`1201 North Market Street
`P.O. Box 1347
`Wilmington, DE 19899
`(302) 658-9200
`jblumenfeld@mnat.com
`began@mnat.com
`
`Gregory S. Arovas P. C.
`KIRKLAND & ELLIS LLP
`601 Lexington Avenue
`New York, NY 10022
`(212) 446-4800
`greg.arovas@kirkland.com
`
`Adam R. Alper
`Brandon Brown
`KIRKLAND & ELLIS LLP
`555 California Street, Suite 2700
`San Francisco, CA 94104
`(415) 439-1400
`adam.alper@kirkland.com
`
`Michael W. De Vries
`Christopher M. Lawless
`Sharre Lotfollahi
`Kevin Bendix
`
`
`
`18
`
`INTEL - 1009
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`
`
`Case 1:19-cv-01006-JDW Document 67 Filed 01/31/20 Page 19 of 19 PageID #: 2103
`
`
`Ziyong Li (Pro Hac Vice)
`seanli@quinnemanuel.com
`QUINN EMANUEL URQUHART &
`SULLIVAN, LLP
`50 California Street, 22nd Floor
`San Francisco, CA 94111
`Tel.: (415) 875-6600
`
`ATTORNEYS FOR PLAINTIFF
`PACT XPP Schweiz AG
`
`
`
`Allison W. Buchner
`KIRKLAND & ELLIS LLP
`333 South Hope Street
`Los Angeles, CA 90071
`(213) 680-8400
`michael.devries@kirkland.com
`christopher.lawless@kirkland.com
`sharre.lotfollahi@kirkland.com
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`allison.buchner@kirkland.com
`
`ATTORNEYS FOR DEFENDANT
`Intel Corporation
`
`19
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`
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`INTEL - 1009
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